Dual JK flip-flop with reset; negative-edge trigger

Transcription

1 Rev November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance with JEDEC standard no. 7. The 74HC is a dual negative-edge triggered JK flip-flop featuring individual J, K, clock (ncp) and reset (nr) inputs; also complementary nq and nq outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. The reset (nr) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the nq output LOW and the nq output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Low-power dissipation Complies with JEDEC standard no. 7 ESD protection: HBM EI/JESD B exceeds 2000 V MM EI/JESD exceeds 200 V. Multiple package options Specified from 40 C to+80 C and from 40 C to +125 C.

2 3. Quick reference data 4. Ordering information Table 1: Quick reference data GND = 0 V; T amb =25 C; t r =t f = 6 ns. Symbol Parameter Conditions Min Typ Max Unit t PHL, t PLH propagation delay C L = 15 pf; V CC =5 V - - ncp to nq ns ncp to nq ns nr to nq, nq ns f max maximum clock C L = 15 pf; V CC = 5 V MHz frequency C I input capacitance pf C PD power dissipation capacitance per flip-flop V I = GND to V CC [1] pf [1] C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. Table 2: Type number Ordering information Package Temperature range Name Description Version N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 Product data sheet Rev November of 21

3 5. Functional diagram 14 1J J Q 1Q CP FF1 CP 3 1K K Q 1Q 13 R 2 1R 7 2J J Q 2Q 9 5 2CP FF2 CP 10 2K K Q 2Q 8 6 2R R 001aab981 Fig 1. Functional diagram J 2J 1CP 2CP J CP FF Q 1Q 12 2Q J C1 1K R K 2K K R 1R 2R 2 6 Q 1Q 13 2Q 8 001aab J C1 1K R 001aab Fig 2. Logic symbol Fig 3. IEC logic symbol Product data sheet Rev November of 21

4 K C C C C Q J C C C C R Q CP C C 001aab982 Fig 4. Logic diagram (one flip-flop) 6. Pinning information 6.1 Pinning 1CP J 1R Q 1K Q V CC GND 2CP K 2R 6 9 2Q 2J aab978 2Q Fig 5. Pin configuration 6.2 Pin description Table 3: Pin description Symbol Pin Description 1CP 1 clock input for flip-flop 1 (HIGH-to-LOW, edge-triggered) 1R 2 asynchronous reset input for flip-flop 1 (active LOW) 1K 3 synchronous K input for flip-flop 1 V CC 4 positive supply voltage 2CP 5 clock input for flip-flop 2 (HIGH-to-LOW, edge-triggered) 2R 6 asynchronous reset input for flip-flop 2 (active LOW) 2J 7 synchronous J input for flip-flop 2 2Q 8 complement flip-flop 2 output 2Q 9 true flip-flop 2 output 2K 10 synchronous K input for flip-flop 2 Product data sheet Rev November of 21

5 7. Functional description Table 3: Pin description continued Symbol Pin Description GND 11 ground (0 V) 1Q 12 true flip-flop 1 output 1Q 13 complement flip-flop 1 output 1J 14 synchronous J input for flip-flop 1 8. Limiting values 7.1 Function table Table 4: Function table [1] Input Output Operating mode nr ncp nj nk nq nq L X X X L H asynchronous reset H h h q q toggle l h L H load 0 (reset) h l H L load 1 (set) l l q q hold (no change) [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition; q = state of referenced output one set-up time prior to the HIGH-to-LOW CP transition; X = don t care; = HIGH-to-LOW CP transition. Table 5: Limiting values In accordance with the bsolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input diode current V I < 0.5 V or V I >V CC V - ±20 m I OK output diode current V O < 0.5 V or V O >V CC V - ±20 m I O output source or sink V O = 0.5 V to V CC V - ±25 m current I CC, I GND V CC or GND current - ±50 m T stg storage temperature C P tot power dissipation DIP14 package [1] mw SO14, SSOP14 and TSSOP14 packages [2] mw [1] bove 70 C: P tot derates linearly with 12 mw/k. [2] bove 70 C: P tot derates linearly with 8 mw/k. Product data sheet Rev November of 21

6 9. Recommended operating conditions Table 6: 10. Static characteristics Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit V CC supply voltage V V I input voltage 0 - V CC V V O output voltage 0 - V CC V t r, t f input rise and fall V CC = 2.0 V ns times except for V CC = 4.5 V ns ncp V CC = 6.0 V ns T amb ambient temperature C Table 7: Static characteristics t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit T amb =25 C V IH HIGH-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V I O = 4 m; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V V OL LOW-level output voltage V I =V IH or V IL I O =20µ; V CC = 2.0 V V I O =20µ; V CC = 4.5 V V I O =20µ; V CC = 6.0 V V I O = 4 m; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V I LI input leakage current V I =V CC or GND; V CC = 6.0 V - - ±0.1 µ I CC quiescent supply current V I =V CC or GND; I O = 0 ; V CC = 6.0 V µ C I input capacitance pf Product data sheet Rev November of 21

7 Table 7: Static characteristics continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit T amb = 40 C to +85 C V IH HIGH-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V I O = 4 m; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V V OL LOW-level output voltage V I =V IH or V IL I O =20µ; V CC = 2.0 V V I O =20µ; V CC = 4.5 V V I O =20µ; V CC = 6.0 V V I O = 4 m; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V I LI input leakage current V I =V CC or GND; V CC = 6.0 V - - ±1.0 µ I CC quiescent supply current V I =V CC or GND; I O = 0 ; V CC = 6.0 V µ Product data sheet Rev November of 21

8 Table 7: Static characteristics continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit T amb = 40 C to +125 C V IH HIGH-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V I O = 4 m; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V V OL LOW-level output voltage V I =V IH or V IL I O =20µ; V CC = 2.0 V V I O =20µ; V CC = 4.5 V V I O =20µ; V CC = 6.0 V V I O = 4 m; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V I LI input leakage current V I =V CC or GND; V CC = 6.0 V - - ±1.0 µ I CC quiescent supply current V I =V CC or GND; I O = 0 ; V CC = 6.0 V µ Product data sheet Rev November of 21

9 11. Dynamic characteristics Table 8: Dynamic characteristics GND = 0 V; t r =t f = 6 ns; C L = 50 pf; see Figure 8. Symbol Parameter Conditions Min Typ Max Unit T amb = 25 C t PHL, t PLH propagation delay ncp to nq see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns V CC = 5.0 V; C L =15pF ns propagation delay ncp to nq see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns V CC = 5.0 V; C L =15pF ns propagation delay nr to nq, nq see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns V CC = 5.0 V; C L =15pF ns t THL, t TLH output transition time see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t W ncp clock pulse width HIGH or LOW see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns nr reset pulse width HIGH or LOW see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t rem removal time nr to ncp see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t su set-up time nj, nk to ncp see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet Rev November of 21

10 Table 8: Dynamic characteristics continued GND = 0 V; t r =t f = 6 ns; C L = 50 pf; see Figure 8. Symbol Parameter Conditions Min Typ Max Unit t h hold time nj, nk to ncp see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns f max maximum clock frequency see Figure 6 V CC = 2.0 V MHz V CC = 4.5 V MHz V CC = 6.0 V MHz V CC = 5.0 V; C L = 15 pf MHz C PD power dissipation capacitance per flip-flop V I = GND to V CC [1] pf T amb = 40 C to +85 C t PHL, t PLH propagation delay ncp to nq see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns propagation delay ncp to nq see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns propagation delay nr to nq, nq see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t THL, t TLH output transition time see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t W ncp clock pulse width HIGH or LOW see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns nr reset pulse width HIGH or LOW see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t rem removal time nr to ncp see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet Rev November of 21

11 Table 8: Dynamic characteristics continued GND = 0 V; t r =t f = 6 ns; C L = 50 pf; see Figure 8. Symbol Parameter Conditions Min Typ Max Unit t su set-up time nj, nk to ncp see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t h hold time nj, nk to ncp see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns f max maximum clock frequency see Figure 6 V CC = 2.0 V MHz V CC = 4.5 V MHz V CC = 6.0 V MHz T amb = 40 C to +125 C t PHL, t PLH propagation delay ncp to nq see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns propagation delay ncp to nq see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns propagation delay nr to nq, nq see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t THL, t TLH output transition time see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t W ncp clock pulse width HIGH or LOW see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns nr reset pulse width HIGH or LOW see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet Rev November of 21

12 Table 8: Dynamic characteristics continued GND = 0 V; t r =t f = 6 ns; C L = 50 pf; see Figure 8. Symbol Parameter Conditions Min Typ Max Unit t rem removal time nr to ncp see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t su set-up time nj, nk to ncp see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t h hold time nj, nk to ncp see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns f max maximum clock frequency see Figure 6 V CC = 2.0 V MHz V CC = 4.5 V MHz V CC = 6.0 V MHz [1] C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. Product data sheet Rev November of 21

13 12. Waveforms nj, nk input V M t su t h 1/f max t su t h ncp input V M t W t PHL t PLH nq output V M t THL t TLH nq output V M t TLH t PLH t THL t PHL 001aab983 Fig 6. The shaded areas indicate when the input is permitted to change for predictable output performance. V M = 0.5 V I. Waveforms showing the clock (ncp) to output (nq, nq) propagation delays, the clock pulse width, the J and K to ncp set-up and hold times, the output transition times and the maximum clock frequency ncp input V M t rem t W nr input V M t PHL nq output t PLH nq input 001aab984 Fig 7. V M = 0.5 V I. Waveforms showing the reset (nr) input to output (nq, nq) propagation delays and the reset pulse width and the nr to ncp removal time Product data sheet Rev November of 21

14 V CC PULSE GENERTOR V I D.U.T. V O R T C L mna101 Fig 8. Test data is given in Table 9. Definitions for test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator. C L = Load capacitance including jig and probe capacitance. Load circuitry for switching times Table 9: Test data Supply Input Load V CC V I t r, t f C L 2.0 V V CC 6 ns 50 pf 4.5 V V CC 6 ns 50 pf 6.0 V V CC 6 ns 50 pf 5.0 V V CC 6 ns 15 pf Product data sheet Rev November of 21

15 13. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 D M E seating plane 2 L 1 Z 14 e b b 1 8 w M c (e ) 1 M H pin 1 index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 1 2 (1) (1) min. max. b b 1 c D E e e 1 L M E M H w (1) Z max Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT G04 MO-001 SC Fig 9. Package outline SOT27-1 (DIP14) Product data sheet Rev November of 21

16 SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E X c y H E v M Z 14 8 Q pin 1 index 2 1 ( ) 3 θ L p 1 7 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D (1) E (1) e H (1) E L L p Q v w y Z Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT E06 MS Fig 10. Package outline SOT108-1 (SO14) Product data sheet Rev November of 21

17 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E X c y H E v M Z 14 8 Q 2 1 ( ) 3 pin 1 index 1 7 L detail X L p θ e b p w M mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (1) e H E L L p Q v w y Z(1) max. mm θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT337-1 MO Fig 11. Package outline SOT337-1 (SSOP14) Product data sheet Rev November of 21

18 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E X c y H E v M Z 14 8 pin 1 index 2 1 Q ( ) 3 θ 1 7 e b p w M L detail X L p mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (2) e H (1) E L L p Q v w y Z max. mm θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT402-1 MO-153 EUROPEN PROJECTION ISSUE DTE Fig 12. Package outline SOT402-1 (TSSOP14) Product data sheet Rev November of 21

19 14. Revision history Table 10: Revision history Document ID Release Data sheet status Change notice Doc. number Supersedes date _ Product data sheet HC_HCT73_CNV_2 Modifications: The format of this data sheet has been redesigned to comply with the current presentation and information standard of Philips Semiconductors. Removed type number 74HCT73. Inserted family specification. 74HC_HCT73_CNV_ Product specification HC_HCT73_1 74HC_HCT73_ Product specification Product data sheet Rev November of 21

20 15. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. Definitions 17. Disclaimers Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the bsolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. pplication information pplications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Life support These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status Production ), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 18. Contact information For additional information, please visit: For sales office addresses, send an to: sales.addresses@ Product data sheet Rev November of 21

21 19. Contents 1 General description Features Quick reference data Ordering information Functional diagram Pinning information Pinning Pin description Functional description Function table Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline Revision history Data sheet status Definitions Disclaimers Contact information Koninklijke Philips Electronics N.V ll rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 12 November 2004 Document number: Published in The Netherlands