Comparison of Single Bit 14T and 8T Full Adder for Low-Power VLSI Design

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1 Proc. of Int. Conf. on Emerging Trends in Engineering and Technology Comparison of Single Bit 14T and 8T Full Adder for Low-Power VLSI Design Shikha Singh 1, Seema Narwal 2 1 Electronic Science Department, Kurukshetra University, Haryana shikhasingh0606@gmail.com 2 Electronic Science Department, Kurukshetra University, Haryana seemanarwal@gmail.com Abstract This paper presents a new design for 14 transistor single bit full adder, implemented using five transistor XNOR/XOR cell and transmission gate multiplexer. For transmission gate multiplexer complementary gate control signals are required and in 14 transistor full Adder both XOR and XNOR signals are generated. XNOR/XOR cell shows high power consumption than single XNOR gate. So, 8 transistor full adder has been designed using 3 transistor XNOR gate and comparison is made between 14 T and 8 T full adder. Simulation has been done using 0.35µm technology. These circuits were redesigned at the transistor-level in tsmc 0.18µm technology and comparison reported here uses Mentor Graphics ELDO simulations to assess their performance. Circuit works well with reduced supply voltage and simulations have been carried out up to 1.8V supply voltage. 8T full adder shows better performance in terms of power consumption and transistor count as compared to 14 T full adder. Index Terms CMOS, exclusive-or (XOR), exclusive-nor (XNOR), full adder, lowpower, pass transistor logic, transmission gate multiplexer. I. INTRODUCTION With rise in number of transistors on chip, power consumption of VLSI systems is also raising which raises chip temperature and affect battery life. So research efforts in the field of low-power VLSI (very large-scale integration)[9] systems have increased[2]. Adders are extensively used component in data path which consumes roughly 30% of the total power of the system therefore careful design analysis is required [3]. The function of full adder is based on following two equations, A, B, Cin are the three single bit inputs and generates two single bit outputs Sum and Carry (Cout)[5], where: Sum = (A xor B) xor Cin (1) Cout = A and B + Cin (A xor B) (2) Structure approach for implementation of single bit full adders using XOR/XNOR[1] is shown in Fig. 1. With decomposition of full adder cell into smaller cells, equation (1) and equation (2) can be rewritten as: Sum= H' xnor Cin = H.Cin '+H'Cin (3) Cout= AH '+CinH (4) Where H is half sum (A xor B) and H ' is complement of H. DOI: 03.AETS Association of Computer Electronics and Electrical Engineers, 2013

2 II. SYSTEM DESCRIPTION A new single bit full adder with 14 transistors based on XNOR/XOR cell and transmission gate multiplexer has been presented. Gate lengths of all three transistors have been taken as 0.35µm and 0.18µm for 0.35µm and 0.18µm technology respectively. Width (Wn) of NMOS transistors N1 and N2 has been taken 5.0µm and 1.0µm for 0.35µm technology and 2.5µm and 0.5µm for 0.18µm technology. Width (Wp) for transistor P1 has been taken as 2.0µm and 1.0µm for 0.35µm and 0.18µm technology. Width for Wn and Wp for inverter have been taken as 2.5µm and 1.0µm for 0.35µm technology and 1.25µm and.5µm for 0.18µm technology[7],[8]. Figure 1: Structure Approach of single bit full adder For multiplexer section, values of width (Wn &Wp) for NMOS and PMOS transistors have been taken as 1.0µm & 2µm respectively for 0.35µm technology and 0.5µm and 1.0µm for 0.18µm technology. Sum is generated by two XNOR/XOR cell and Cout by transmission gate multiplexer. For transmission gate multiplexer complementary gate control signals are required and in 14 transistor full Adder both XOR and XNOR signals are generated. For 8 T full adder sum is generated by two XNOR gates and Cout is generated by two transistors multiplexer block. The output of the first stage is used as a selector circuit for the carry output. When the output of the first stage a XNOR b is 0, the carry output is equal to the carry in i.e. Cin. When the output of the first stage a XNOR b is 1, the carry output is equal to the input a. Fig. 2(a) and Fig. 2(b) shows the implemented single bit full adder using proposed XNOR gates with 14 T and 8 T[4],[6]. Figure2 (a): 14 T Full adder using XNOR/ XOR cell Figure2 (b): 8 T Full Adder using 3 T XNOR gate 873

3 III. RESULTS AND DISCUSSIONS Fig. 3 shows input and output waveform results for 14 T full adder. Output voltage levels are improved with 0.18µm than in 0.35µm technology. Fig. 4 shows input and output waveform results for 8 T full adder. Output voltage levels are improved with 0.18µm than in 0.35µm technology. Figure 3(a) Figure 3(b) Figure 3: 14 T Full Adder Waveform (a)using 0.35µm technology (b) using 0.18µm technology with supply voltage of 3.3V 874

4 Figure 4(a) Figure 4(b) Figure 4: 8 T Full adder Waveform (a)using 0.35µm technology (b) using 0.18µm technology with supply voltage of 3.3 V Table 1 shows power consumption and output voltage levels for sum and carry of proposed 14 T Full Adder. It has been observed from table that power consumption reduces with reduction in supply voltage. S.V (V) Power Consumption (µw) TABLE I(A) for low SUM for high Cout

5 TABLE I(B) S.V (V) Power consumption (µw) for low SUM for high Cout Also from figure 5, power consumption decreases using 0.18 than in 0.35µm technology. Output voltage levels are improved with 0.18 than in 0.35µm technology. Power dissipation (uw) um 0.18 um 14 T full ad der Supply Voltage(V ) Figure 5: Power consumption of 14 T Full Adder gate with supply voltage of [ ] V using 0.35µm and 0.18µm technology Table 2 shows results of power consumption and output voltage levels for 8 T full adder with variations in supply voltage from [ ] V. TABLE II: POWER CONSUMPTION AND OUTPUT VOLTAGE LEVELS OF 8T FULL ADDER (A) USING 0.35µM (B) USING 0.35µM TECHNOLOGY WITH SUPPLY VOLTAGE OF [ ]V TABLE II (A) S.V(V) Power consumption(µw) for low SUM for high Cout S.V (V) Power consumption(µw) TABLE II (B) for low SUM output for high Cout It has been observed from table that power consumption reduces with reduction in supply voltage. Also from figure 6, power consumption decreases using 0.18 than in 0.35µm technology. Output voltage levels are improved with 0.18 than in 0.35µm technology. 876

6 Power Consumption(pW) um 0.18um 8 T Full Adder Supply Voltage(V) Figure 6: Power consumption of 8 T Full Adder with supply voltage of [ ] V using 0.35µm and 0.18µm technology Table 3 shows comparison of 14 T and 8 T full Adder. 8 T full Adder has less internal capacitance due to reduce number of transistors and shows reduced power consumption. TABLE 3: COMPARISONS OF POWER CONSUMPTION OF 14 T FULL ADDER AND 8 T FULL FULL ADDER Full Adder Configuration Technology Power Consumption (µw) 14T Full Adder 0.35µm T Full Adder 0.35µm T Full Adder 0.18µm T Full Adder 0.18µm IV. CONCLUSION A new low-power single bit full adder based on XNOR/XOR cell using 14 transistors has been designed. Proposed adder shows power consumption of µW using 0.35µm technology and µW using 0.18µm technology with supply voltage of 3.3V. Also single bit full adder with 8 transistors based on proposed XNOR gate has been presented which shows power consumption of µW using 0.35µm technology and µW using 0.18µm technology with supply voltage of 3.3V. 8 T Adder has been compared with 14 T adder and show less power consumption with reduced transistor count. The proposed adders has been designed and studied using 0.18µm and 0.35µm technologies, which shows better performance of circuits using 0.18µm technology. REFERENCES [1] Sujata Pandey, Sandeep K. Arya, Manoj Kumar, Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate, International Journal of VLSI design & Communication Systems (VLSICS),Vol.2, No.4, December [2] A.Banerjee, Saradindu Panda, Dr.A.K.Mukhopadhyay, B.Maji, Power and Delay Comparison in between Different types of Full-Adder Circuits, IJAREEIE, Vol. 1, Issue 3, September [3] Mayank Kumar Rai, Deepak Garg, CMOS Based 1-Bit Full Adder Cell for Low-Power Delay Product, IJECCT, Vol. 2, No.4, July2012. [4] V.Elakya, D.Priya, Design Of High Performance Low Power Full-Adder, IJATER, Vol. 2, Issue 2, September [5] Rohit Maurya, Vivek Kumar, Vrinda Gupta,, A Study and Analysis of High Speed Adders in Power-Constrained Environment, International Journal of Soft Computing and Engineering (IJSCE), Volume-2, Issue-3, July [6] Divya Gupta, Ravindra Prakash Gupta, B.S.N.Raju, Analysis of Different CMOS Adders for Power, Speed and Area, IJECT, Vol. 2, Issue 4, Oct - Dec 2011 [7] Yi WEI, Ji-zhong SHEN, Design of a novel low power 8-transistor 1-bit full adder cell Wei et al. / 604 J Zhejiang Univ-Sci (Comput & Electron), [8] R. N. Mandavgane, N. M. Chore, A survey of low power high speed one bit full adder, Recent advances in networking, VLSI and signal processing, vol.6, pp , Oct [9] Shikha, Seema, Comparative Performance Analysis of XOR/XNOR Topologies for Low-Power VLSI Design, IJERT, ISSN , Vol-6, No.-10, pp.25-31,