1. Random Access Memory An array of 64K by 4 SRAM ICs is used to construct a 256K by 8 memory system.

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1 1. Random Access Memory An array of 64K by 4 SRAM ICs is used to construct a 256K by 8 memory system. (a) How many RAM ICs are needed? (b) How many address lines and how many data lines are there for the memory system? Now consider a SRAM memory chip organized in a rectangular array using a coincident selection scheme (using a row select decoder and a column select decoder) instead of a single row select decoder. (c) Suppose that the memory chip is 128K by 4 and the number of select lines leaving the row decoder is twice the number of select lines leaving the column decoder. How many address lines are connected to each decoder? How many total address pins are there? (d) Suppose that this chip is a DRAM. How many address pins would be on this chip? (e) Suppose that the memory is 64K by 7 and the column select and row select decoders are the same size. How many address lines are connected to each decoder? (f) For a 32K by 1 memory, suppose the address lines of the most significant 10 bits of the address are connected to the row select decoder, and the remaining address bits are connected to the column select decoder. Find the row and column numbers of the RAM cell in the square array that corresponds to the Hexadecimal address 20A3.

2 2. Random Access Memory Timing Pick out the necessary steps and place in the proper order for each of the cases below. See pages 402, 404, 419 in Mano & Kime. a) SRAM A. Apply the binary address of the desired word to the address bus B. Apply the binary Row Address of the desired word to the address bus C. Apply the binary Column Address of the desired word to the address bus D. Apply the data bits that must be stored in memory to the data input bus E. Set Read/~Write equal to logic 1 F. Set Read/~Write equal to logic 0 G. Activate the memory enable H. Deactivate the memory enable I. Activate the output enable J. Deactivate the output enable K. Activate the RAS line L. Deactivate the RAS line M. Activate the CAS line N. Deactivate the CAS line Read Cycle 1) 1) Write Cycle 2) 2) 3) 3) 4) 4) 5) 5) b) DRAM Read Cycle 1) 1) Write Cycle 2) 2) 3) 3) 4) 4) 5) 5) 6) 6) 7) 7) 8) 8)

3 3. PROM Implementation Implement the following boolean functions using a PROM. Specify the size of the ROM. Fill in the truth table and connection map below. For the truth table, assume a 1 indicates a connection and a 0 indicates no connection. For the connection map, label the outputs of the OR gates and indicate a connection with an x. A(X,Y,Z) = m(3,6,7) B(X,Y,Z) = M(2,3,7) C(X,Y,Z) = m(2,3,4) _ D(X,Y,Z) = X Y Z + X Y + Y Z Address ROM Content X Y Z A B C D Check out the discussion folder on the course website for other programmable logic (PLA, PAL) problems.

4 4. ASM An algorithmic state machine (ASM) is to be formulated which has two inputs A and B and one output Z. The flip-flops used to implement the ASM are positive edge-triggered. The following describes the operation of the synchronous ASM. Power-up reset, which need not be shown in the diagram, places the control in initial state R. Beginning at power up or reset in state R, any time thereafter that the sequence A = 0, A = 0, B = 1 occurs on three successive clock cycles, output Z is to be 1 immediately upon application of B = 1. Otherwise, Z is to be 0. The ASM is to have Z a function of both state and input, i. e., to be a Mealy type. Complete the partial ASM diagram below. Do NOT add any state boxes! R

5 5. ASM Implementation: One Flip-Flop per State An ASM chart is given along with some components for implementing the flip-flop per state control unit it represents. The control unit has inputs A and B and outputs C1, C2 and C3. Interconnect the components to implement the control including outputs. There may be more components than needed and extra inputs on some components. Connect extra inputs to 0 or 1 as appropriate.

6 6. Binary Multiplier Manually simulate the process of multiplying the two unsigned binary numbers 1001 (multiplicand) and 1010 (multiplier). List the contents of the registers A, Q, P, and C and the control state, using the figures below. Assume G = 1 for the first IDLE state. State P C A Q IDLE

7 7. Binary Multiplier Manually simulate the process of multiplying the two unsigned binary numbers 1001 (multiplicand) and 1010 (multiplier). List the contents of the registers A, Q, and P and the control state, using the figures below. Assume G = 1 for the first IDLE state. State P A Q IDLE What is the major advantage of this multiplier? How was the datapath changed from the original one to implement this multiplier?

8 8. Synchronous Counter Design Construct a BCD down counter by connecting together the given components and labels:

9 9. Synchronous Counter Design Four positive edge-triggered flip- flops with asynchronous clear are shown. Connect the flip- flops and additional logic to form a synchronous binary up counter (counts 0, 1, 2,,15, 0,...). This counter has an ENABLE input. With ENABLE = 1, the counter counts up. With Enable = 0, the counter holds its current value. The additional logic is to consist ONLY of AND gates with as many inputs as needed and the type of gating is to be PARALLEL (not SERIAL) to permit a high clock frequency.

10 10. Asynchronous Counter Design Assuming the circuit below begins in state 0,0,0, write the sequence of states that occurs in the boxes given the interconnected T-flip-flops below

11 11. Busses and Register Transfers The following register transfer operations will be implemented where K1, K0 are two input Boolean variables: K1 K0 : R1 R2 K1 K0 : R2 R3 K1 K0 : R3 R2 K1 K0 : R1 R4 All four n-bit registers R1, R2, R3, and R4 have three-state bi-directional input/output lines connecting to a single shared bus as shown in the figure below. Fill-in the control signals (Load and En(able)) to each of these four registers so that the above conditional register transfer operations can be realized. R1 R2 R3 R4 Load EN

12 12. ALU Depicted above is an ALU bit slice which can perform both arithmetic and logic operations by choosing appropriate control signals C in, S 0 and S 1 where C 0 = C in. Let F = F n 1 F 1 F 0 to be the output, A = A n 1 A 1 A 0 and B = B n 1 B 1 B 0. Complete the function table below. S 1 S 0 C in = 0 C in = A B A A + B 1 1

13 13. Micro-operations The simple datapath studied in Chapter 7 is used for this question. The detailed description of the micro-operations and control bits is attached to the end of this exam. Use it to help answer the following questions. FILL IN the table below with the appropriate missing entry. If the field is unused, denote it by placing X s for each bit in the field. All microinstruction values are BINARY. Operation DA AA BA MB FS MD RW R0 R3 R2 R1 DataIn AddressOut R7 R 3 R

14 14. Single-Cycle Computer-Instruction Formats Find the binary representation for each instruction by filling in the table below. Instruction LD R1, R4 SUB R2, R2, R1 ADI R0, R1, 6 JMP R6 BRZ R7,

15 15. Single-Cycle Computer-Control Words Find the register transfer notation and control word for each instruction by filling in the table below. Instruction Register Transfer DA AA BA MB FS MD RW MW PL JB BC SUB R2, R2, R1 R[ 2] R[2] R[1] DEC R3, R4 ADI R0, R1, 6 JMP R6 BRZ R7, -23 LD R3, R6 R[ 3] M[ R[6]] ST R5, R7