706 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 8, AUGUST 1998

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1 706 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 8, AUGUST 1998 A Design-for-Testability Technique for Register-Transfer Level Circuits Using Control/Data Flow Extraction Indradeep Ghosh, Member, IEEE, Anand Raghunathan, and Niraj K. Jha, Fellow, IEEE Abstract In this paper, we present a technique for extracting functional (control/data flow) information from register-transfer level controller/data path circuits, and illustrate its use in design for hierarchical testability of these circuits. This scheme does not require any additional behavioral information. It identifies a suitable control and data flow from the register-transfer level circuit, and uses it to test each embedded element in the circuit by symbolically justifying its precomputed test set from the system primary inputs to the element inputs and symbolically propagating the output response to the system primary outputs. When symbolic justification and propagation become difficult, it inserts test multiplexers at suitable points to increase the symbolic controllability and observability of the circuit. These test multiplexers are mostly restricted to off-critical paths. Testability analysis and insertion are completely based on the registertransfer level circuit and the functional information automatically extracted from it, and are independent of the data path bit width owing to their symbolic nature. Furthermore, the data path test set is obtained as a byproduct of this analysis without any further search. Unlike many other design-for-testability techniques, this scheme makes the combined controller-data path very highly testable. It is general enough to handle control-flow-intensive register-transfer level circuits like protocol handlers as well as data-flow intensive circuits like digital filters. It results in low area/delay/power overheads, high fault coverage, and very low test generation times (because it is symbolic and independent of bit width). Also, a large part of our system-level test sets can be applied at speed. Experimental results on many benchmarks show the average area, delay, and power overheads for testability to be 3.1, 1.0, and 4.2%, respectively. Over 99% fault coverage is obtained in most cases with two four orders of magnitude test generation time advantage over an efficient gate-level sequential test pattern generator and one three orders of magnitude advantage over an efficient gate-level combinational test pattern generator (that assumes full scan). In addition, the test application times obtained for our method are comparable with those of gatelevel sequential test pattern generators, and up to two orders of magnitude smaller than designs using full scan. Index Terms Design for testability, functional information extraction, RTL circuit testing, symbolic testing. I. INTRODUCTION THE problem of sequential test pattern generation has remained a difficult one in spite of great advances in automatic test pattern generation (ATPG) techniques. The Manuscript received December 12, 1997; revised April 21, This work was supported by the NSF under Grant MIP This paper was recommended by Associate Editor S. Reddy. The authors are with the Department of Electrical Engineering, Princeton University, Princeton, NJ USA. Publisher Item Identifier S (98) classical testing methods [1] target the problem at the gate level, and might require huge amounts of computing time and resources to generate tests of even moderately sized sequential circuits. By modeling circuits at a higher level, the number of primitive elements in the circuit is reduced, thus making the problem size more tractable. This allows larger circuits to be handled in much less time. In order to reduce the complexity of test generation in larger circuits, various design-for-testability (DFT) schemes have been proposed. Among them, scan design (full or partial) [2] [4] has become one of the most widely used. However, the area and delay overheads as well as large test application times are a matter of concern in scan-based designs. Another major disadvantage of scan-based design is that the complete test set cannot be applied at speed. This becomes important in light of the work in [5] which shows that applying test vectors at the operational speed of the circuit detects more defective integrated circuits than a test set having the same fault coverage that is applied at a slower rate in a scan mode. In recent years, various behavioral and architectural schemes have been proposed to generate easily testable sequential circuits. These techniques may target built-in self test [6], [7] or sequential ATPG [8]. A lot of work has also been done in behavioral synthesis for testability [9] [15]. In [9] [12], behavioral synthesis was geared toward scan optimization. The behavioral description of a circuit was modified in [13] to improve testability. Hierarchical testability was targeted during behavioral synthesis in [14] and [15]. However, while targeting a circuit for testing, the behavioral description is not available in many cases. Solving the test generation problem at the gate level suffers from the problems of higher area/delay overheads. Hence, in order to get the testability advantages of a higher level of abstraction, the register-transfer level (RTL) is a good choice. Due to the popularity of macrocell-based designs, a circuit description at RTL is frequently available. Note that most of the above work has targeted data-flowintensive designs, and work on control-flow-intensive designs is limited. At the RTL, some DFT schemes have also been proposed. A full scan-based scheme has been proposed in [16]. Nonscan DFT techniques are employed in [17] to make RTL circuits better testable by ATPG. In [18], the controller is modified to achieve better testability of the circuit. HSCAN a hybrid between high-level testing and scan is proposed in [19]. All of these methods target gate-level ATPG. A partial scan /98$ IEEE

2 GHOSH et al.: DESIGN FOR TESTABILITY TECHNIQUE 707 method which employs symbolic test generation is presented in [20]. Precomputed test sets are used to test acyclic RTL circuits in [21]. There has also been some effort to justify and propagate test vectors at the RTL for data-flow-intensive circuits on a vector-by-vector basis [22], [23]. An RTL automatic test-scheduling technique has been proposed that can be used in lieu of or to complement sequential gate-level ATPG [24]. It provides a system with 11 signal types to perform test scheduling at the RTL which allows modulelevel precomputed test sets to be directly used for testing. The techniques have been further extended to do RTL fault simulation [25]. In [26], the testing of the controller/data path pair is done in an integrated way by adding a small finite-state machine, known as a piggyback FSM, to the system between the controller and data path. A high-level ATPG tool has also been developed that uses a functional equivalent model of sequential primitives, making it usable beyond the RTL [27]. A gate-level test generator is used to generate test vectors for the module under test. High-level knowledge is applied locally to speed up the data implication at each module. For each pattern to be justified at a module input, an instruction sequence is automatically assembled using a structural data-flow graph. In related previous work [28], RTL circuits obtained through behavioral synthesis were targeted for hierarchical testability. In this work, we propose a new methodology whereby RTL circuits are made hierarchically testable by using very little test hardware without assuming that they are obtained through behavioral synthesis. Thus, no prior behavioral information is assumed available. The only restriction imposed on the circuits is that they should have a separate data path and controller, and a reset state should be present in the controller. The only inputs required are a structural RTL description of the data path in some high-level descriptive language like VHDL and the logic-level netlist of the controller. This scheme works by extracting a test control-data flow (TCDF) from the data path and controller circuitry, and using it to symbolically justify precomputed test sets of RTL elements from the system inputs to element inputs and symbolically propagate error responses from element outputs to system outputs. When this is not possible, test multiplexers are added to the data path to increase its symbolic controllability and observability. These multiplexers can mostly be added to off-critical paths. TCDF may not exactly correspond to the full control-data flow graph (CDFG) that the RTL circuit emulates. However, the test set derived with its help is valid for the RTL circuit. The precomputed test set of an RTL element can be obtained using a suitable fault model at a lower level description of the element. All modules in the design library can be characterized in this fashion, and their precomputed test sets can be stored in the library along with the traditional information that is stored in the library, such as area, delay, and power models. Note that obtaining the precomputed test set is a one-time cost. Just like the area, delay, and power information on the module, its test information is useful for all of the hundreds or thousands of designs created with the help of the design library. For our experimental results, we obtained the precomputed test set of the modules in the library by targeting single stuck-at faults in their gate-level implementation. Many modules in the library were testable (i.e., testable with a constant number of vectors irrespective of bit width) [1]. For such modules, well-known tests were used from the literature. The advantages of this scheme are that it is applicable to all RTL circuits conforming to the above assumptions, whether it be data- or control-flow intensive. The incurred overheads are very low. The fault coverage is very high for all of the circuits, and the test generation time is two four orders of magnitude smaller than sequential ATPG and one three orders of magnitude smaller than combinational ATPG that assumes full scan. The reason is that, because of the use of symbolic test generation in our scheme, the test generation time is independent of bit width. In addition, after testability analysis and insertion, the test set is obtained as a byproduct without any further search. The test application times are very small too. This scheme does not assume any scan at the controller data path interface, and the testing is actually done by using the data flow dictated by the controller. Finally, this scheme is amenable to at-speed testing of the circuit. The paper is organized as follows. The TCDF extraction and subsequent testing procedures are explained in Section II with the help of a data-flow-intensive circuit and a controlflow-intensive circuit. In Section III, the procedures are formalized. Experimental results and conclusions are provided in Sections IV and V, respectively. II. EXTRACTING CONTROL-DATA FLOW INFORMATION FOR TEST In this section, we illustrate the extraction of functional information from RTL implementations and its application to test generation and DFT through several examples. We then discuss the DFT architecture. A. A Data-Flow Intensive Circuit Application Fig. 1 shows an RTL circuit obtained by synthesizing the data flow graph (DFG) of benchmark Paulin [7] which has been popularly used in the literature. This particular RTL implementation was synthesized from a behavioral description using the HYPER [29] high-level synthesis system. However, as mentioned earlier, we will not be making use of the behavioral information available in this case for testability purposes since, in general, such information may not be available. The inputs are applied at IN-PORT1 and IN-PORT2 and the outputs are obtained from OUT-PORT1 and OUT- PORT2. The data path consists of an adder, a subtracter, two multipliers, five registers, two latches, and some multiplexer trees. Note that, throughout this paper, an edge-triggered register without a load signal that loads in all clock cycles is referred to as a latch. 1) Extracting the TCDF: The first step in the process is to extract the controller behavior from the controller circuit. This can be done by a state machine extraction program starting from the reset state of the controller (note that a reset input is assumed to be present for the controller only, not for the data path registers). We used the state machine extraction program available in SIS [30]. As we are trying to extract the state machine of the controller part of the circuit only,

3 708 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 8, AUGUST 1998 Fig. 1. RTL circuit of Paulin. Fig. 2. State transition information of the controller of Paulin. this method is quite efficient and takes very little time. Fig. 2 shows the state table obtained from the controller circuit as well as the corresponding state transition graph. In the absence of conditionals, the state machine takes the form of a counter and, hence, the state transition graph becomes a chain of states. The basic idea behind TCDF extraction is to extract operations executed in each cycle, and keep track of variables that are present in each register or latch. We start with the input variables created in the first cycle. We identify all registers that load in the first cycle. This is done by analyzing the load signals of all of the registers in the data path from the outputs in the state transition table. If a load signal is 1 in any cycle, then the register loads in that cycle. For our example, in cycle 1, all registers load. Along with these registers, all of the latches load by default in all cycles. We next analyze the multiplexer tree that feeds each of these registers or latches, and check if any input port is connected to the register/latch input in the first cycle. The multiplexer tree configuration in any cycle can be obtained by looking at the values of the select signals of those multiplexers in the state table. We find that IN-PORT2 and IN-PORT1 are connected to REG4 and REG5, respectively, in the first cycle. Hence, two variables are born in these two registers. We call them and, respectively. A variable is live until its register loads again. The association of a variable with its register is recorded. Thus, this binding information is developed in each cycle, and the variables bound to a particular register as noted. We also find that in the first cycle, REG1, REG2, REG3 are connected to hardwired constants. We name these, and, respectively, and note their values. The latches do not have any input ports or constants at their inputs. Hence, they are ignored for now. In cycle 2, we would like to identify the operations that take place. So for each functional module in the circuit, we find the operand selected at each of its input ports by analyzing

4 GHOSH et al.: DESIGN FOR TESTABILITY TECHNIQUE 709 Fig. 3. Partial TCDF obtained after analyzing cycle 2. the multiplexer trees at its inputs. For example, in cycle 2, the left input of the adder is connected to REG1 and the right input to REG5. We check if both of these registers have some live variables or constants in them. In this case, they do, and they are and, respectively. In addition, we check if any of the registers (there may be many due to fan-out) at the output of the module load at the end of the second cycle, and if the multiplexer configuration at the input of these registers is such that the output of the module is selected. In case of the adder, REG1 indeed loads at the end of the second cycle. Moreover, the multiplexer at its input selects the adder s output. Hence, we create a new variable in REG1, and an operation in the TCDF,. We also label this operation 1. Similarly, we analyze all other modules to obtain the set of operations in the second cycle, as shown in Fig. 3. In the figure, the constants have their actual values given in brackets beside them. If there are no live variables or constants in some register which is an input to a module or if the output of the module is not loaded anywhere, then the operation is void and not added to the TCDF. Note that this means that the analysis assumes that the design is sensible, i.e., no primary outputs depend indirectly or directly on unknowns. For example, the subtracter does not have a valid operation associated with it in the second cycle as the input latch associated with its right input (LATCH ) does not yet have a live variable. The binding information of operations to modules is also maintained. This procedure is repeated for each cycle until we reach a predefined limit on the number of states visited in the controller state machine. This is explained in detail in Section III. There might still be operations in the generated TCDF which are not part of the original data flow. This is because latches will load by default in every cycle. So if there are live variables at the input of a module whose output goes to a latch, an operation will be created as well as a new variable in the latch. However, before this variable is ever used in the next cycle, it might be overwritten by another variable. For example, at the end of the fifth cycle, the latches LATCH and LATCH load, and this creates two multiplication operations in the fifth cycle. However, these values are never utilized, and the latches load new values at the beginning of the next iteration. Hence, these operations are spurious, and the TCDF graph needs to be pruned. The pruning is performed by starting at the output variables in the TCDF, and performing a backward traversal of the graph until all operations which are not in the support of these variables are deleted (an operation is in the support of a variable if it is in the transitive fan-in of that variable). The TCDF obtained for this circuit, after traversing ten cycles, is shown in Fig. 4. This figure comprises two iterations of the state transition graph. Note that since is an output variable of the first iteration, it has simply been renamed as. The operations and variables with at the end constitute the second iteration. In the figure, the reason that operations *6.1 and are not shown is that they do not contribute to the primary outputs after two iterations (only to a latch that drives the next iteration). 2) Hierarchical Testability Analysis on TCDF: Once this TCDF is obtained, symbolic justification and propagation of test vectors can be done using it, and a set of justification and propagation paths can be generated for the RTL element under test. These paths constitute a test environment [14], [15]. From the test environment, it is a straightforward task to generate a system-level test set for the element using its precomputed test set without any further search. This procedure is briefly described later. In this way, the whole circuit can be tested hierarchically. Before describing the test environment generation process, we need to introduce a few terms. General controllability of a variable, is a Boolean function that represents the ability to control to any desired value by appropriately controlling the primary input variables. Similarly, we can define (controllability to 0), (controllability to 1), (controllability to all-ones vector where is the bit width of the circuit), and (controllability to any fixed constant ). are special cases of. Observability of a variable, written as, is a Boolean function that represents the ability to observe variable at a primary output variable or at any other variable mapped to a primary output register. Verifiability is a Boolean function that represents the ability to verify the value of variable with certainty by either controlling or observing it. Testability of an operation op in a TCDF, written as (op), is a Boolean function which represents the ability to simultaneously control its input variables to any arbitrary values from the system inputs and observe its output variable at some system output. Testability of a variable is defined in a similar way. Note that the only values that controllability, observability, verifiability, or testability of a variable or operation can attain are 0 or 1, unlike the traditional definitions of controllability and observability. Since and allow us to justify and propagate logic values dictated by a precomputed test set defined at a lower level, we refer to them as hierarchical controllability and hierarchical observability, respectively, later. Similarly, if (op) is 1, we say that op (and the module to which it is mapped) is hierarchically testable. Suppose we want to test the ADDER module in the RTL circuit of Paulin. In order to do this, we can test either operation, or mapped to it (see the binding information in Fig. 4). For testing, we need, and (this is another way of saying that we want these three Boolean functions to evaluate to 1). Since is a constant, is impossible to achieve. Hence, we try operation. This time, the objectives are, and. is trivial to achieve since is a primary input variable. is transformed through operation to, and (the last objective

5 710 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 8, AUGUST 1998 Fig. 4. Final TCDF for Paulin. is necessary to ensure that fault masking does not happen during testing of module ADDER as operation is also mapped to it). is again trivial to achieve as is a primary input variable. is achievable as is a constant with value 1. is achieved by observing as is a primary output variable. is again trivial to achieve as is a primary output variable. Thus, a test environment is generated for ADDER with the help of these Boolean functions. Now, let us see how we can use the above test environment to obtain a system-level test set that tests ADDER. Suppose, from the precomputed test set of ADDER, that we see that for one particular test vector, it needs vector at its left (right) input. In cycle 1, we feed vector at IN-PORT1 and obtain the output variable in cycle 3. If the value of, observable at OUT-PORT1, is not, then the fault is immediately detected. Otherwise, we can assume that indeed has value y at this point. We feed vector at IN-PORT1 in cycle 6. Now, if we observe OUT-PORT1 in cycle 8 (variable ), ADDER is tested with the test vector. Thus, once the test environment is generated, the system-level test set is obtained without further search by just plugging in the values from the precomputed test set into the test environment. Note that since test generation is symbolic, it does not matter what exact vectors the precomputed test set contains. Registers can also be tested in a similar fashion. A register can be shown to have a precomputed test set of size 4 [15]. To test a register, it is enough to control and observe any one variable mapped to it. Consider REG5 to which variable is mapped. Since each bit of the register needs a 1 and a 0 to test, we generate two test environments for REG5. First, the objectives are and. is trivial to achieve since is a primary input variable. is transformed through operation to and.as explained earlier, these two objectives can be met. Hence, we have one test environment for REG5. Similarly, the other test environment can be found by starting from and. After this, the system-level test set can be obtained from the precomputed test set of the register as before. Many registers get tested while testing the modules. This is found out by doing RTL test simulation as explained in Section II-E later. Only the remaining untested registers are targeted in the above fashion. In addition, RTL test simulation is used to find multiplexers that get tested while testing the modules and registers. For the remaining untested multiplexers, additional test sequences are added to the system level test set. Deriving these test sequences is a bit tricky. The method is explained in Section II-D. Sometimes, a few -bit 2-to-1 test multiplexers have to be added in order to make symbolic justification and propagation

6 GHOSH et al.: DESIGN FOR TESTABILITY TECHNIQUE 711 Fig. 5. Test multiplexer needed to make the RTL circuit of Paulin testable. Fig. 6. RTL circuit for GCD. possible, where is the data path bit width. This testability insertion method is explained in detail in [28] and briefly described in Section III. For the example circuit Paulin, only one -bit test multiplexer was required in the data path, as shown in Fig. 5. Just the addition of this test multiplexer makes the data path of Paulin completely testable using our method. Although the test multiplexer is placed in front of multiplier MULT2, it does not affect the critical path delay as the delay through MULT1 and the multiplexer tree above it dominates. The select signal of the test multiplexer is taken from an added register called TCR, which is explained in Section II-F. Sometimes, it may not be desirable to feed the other input of the test multiplexer directly from a primary input port. In Paulin, the output of a register, which is fully controllable from a primary input port, can be used as the side input of the test multiplexer. In this case, the test multiplexer was needed to enhance the controllability of an internal wire. In general, however, test multiplexers are also used to enhance observability. In [28], test multiplexers were limited to the inputs/outputs of registers only. However, in this work, this method was extended to place them in front of module inputs/outputs as well. This resulted in bringing down the test multiplexer overhead even further. This can be illustrated through a simple example. Suppose that there is an adder in the RTL circuit that adds operands with different constants which are all bound to constant registers (i.e., registers which only store constants) feeding its left input port. Now, suppose that three of these constants are used in three different test environments used for testing three separate modules, and we need to put arbitrary values on the corresponding wires. If only register inputs are targeted for DFT, we would need three -bit test multiplexers to feed the three constant registers from some controllable variables. However, the problem can be solved using a single -bit test multiplexer at the left input port of the adder. B. A Control-Flow Intensive Circuit Application We next show how the procedure can be applied to a control-flow intensive circuit. Fig. 6 shows an example RTL circuit that we will use to explain the procedure. This circuit computes the greatest common divisor (GCD) of two numbers. The numbers are input at the ports XIN and YIN, and the GCD is written to register REGO which is connected to the output port. Since the number of cycles required to compute the GCD will vary according to the input values provided, the controller has an output signal RDY which specifies that the output is valid. The data path consists of four functional units: a subtracter, a less-than comparator, and two equalto comparators. There are three registers and a number of multiplexer trees. There are three status signals going out from the data path to the controller, namely,. The main problem in extending the approach of Section II-A to control-flow-intensive designs like GCD lies in the complex nature of the controller. Let us take a look at the state transition graph of the GCD controller shown in Fig. 7, which was extracted through SIS as before. There are only four states in the controller. However, the state sequence depends heavily on the status signals generated. A fixed data flow consisting of a fixed number of cycles per iteration (as in the case of Paulin) is impossible to achieve here. This is true because the data flow depends on the inputs specified. For example, for one set of inputs, the subtracter may execute several operations before the output is ready. In some other case, the subtracter may not be exercised at all. The first problem here is that the state machine is a Mealy machine. This means that, in a particular state, the output signals might vary depending on the input status signals. Consequently, the set of operations executed in a particular state of this machine is not unique. This makes it more difficult to generate the data-flow information, as outlined for the previous example. Hence, in order to get rid of this problem, we convert the Mealy machine into an equivalent Moore machine (this conversion is only done for analysis purposes). The above conversion can always be done, where in the Moore machine a state is associated with a fixed set of output values. Fig. 8 shows the corresponding Moore machine obtained for the GCD controller. Now, we can proceed with

7 712 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 8, AUGUST 1998 Fig. 7. State transition information for the GCD controller. Fig. 8. Equivalent Moore machine for the GCD controller. the generation of the TCDF by analyzing this Moore machine. Note that the data flow obtained from the Moore machine will also be valid for the Mealy machine as the behaviors of the two machines are equivalent. In the Moore machine, the output of a particular row in the state table of Fig. 7 is associated with the corresponding state. Row 1 in the state table of the Moore machine corresponds to state, rows 3 and 4 correspond to state, and row 9 corresponds to state. The other states are as before. As stated before, there is no fixed sequence of states in a particular iteration in this case. Hence, in order to test a module in the RTL circuit, we need to find a possible state sequence which will provide us with a TCDF to test that module. The first step in this procedure is to identify the input states in the state machine. These are states where the input registers get loaded from the primary input ports. In GCD, we conclude that is such a state. This is again done by analyzing the load signals of the registers whose input multiplexer tree has an input port, and also by checking the path through the multiplexer tree to see when the input port gets connected to the register input. Next, we proceed to find the set of output states, which are the set of states where an output register is loaded from the data path (i.e., it is loaded with a value, and not a constant). To clarify the previous statement, consider output register REGO in the GCD circuit. It is seen that it is loaded with a constant ZERO in states 1 and, but gets loaded with a data path value only in state (this is evident from the controller state table as loado is 1 only in states and ). Loading a constant into an output register is useless from the data flow point of view. Therefore, only is an output state by our definition. Finally, we define the set of operation states. An operation state is a state where the module under test is exercised. This can be found by checking where the output of the module gets loaded into a register. For example, for the subtracter in GCD, the output is loaded into REGX in state 2. Hence, 2 is the operation state for the subtracter. In order to get a TCDF for a module, we can obtain the sequence of states by going from an input state to an output state through an operation state, while traversing the state transition graph. For example, for the subtracter, we would like to go from to through. We also need to figure out a path from the reset state to the input state, i.e., in this case, from to. If we want to keep the test application time as small as possible, we should immediately choose the shortest path between any two states, and just concatenate them to get the complete path. For example, we find the shortest path between and, then and, and finally and. To do this, a breadth-first search on the state transition graph can be done. One can argue that the sequence of states that the state machine will take will depend on the input values provided, and it may not always be possible to traverse the shortest path. However, the test architecture that we present later gives us full controllability of the status signals during testing. Hence, we can actually dictate the path that the state machine will take during testing by controlling the external inputs. Just finding the state sequence mentioned above, however, may not be sufficient. There is an additional problem of data flow. For instance, in the above case, the shortest path sequence is. However, if we take the state machine through this path, we obtain the TCDF shown in Fig. 9. The register-to-register transfers are shown by the assignment operator, and the dashed lines and nodes

8 GHOSH et al.: DESIGN FOR TESTABILITY TECHNIQUE 713 Fig. 9. Unsuccessful TCDF for the subtracter. Fig. 10. Successful TCDF for the subtracter. are pruned from the TCDF as their outcome does not affect the final output. It can be seen clearly that the subtract operation is not a part of this TCDF if this state sequence is taken. Hence, this is not a valid sequence from the point of view of testing the subtracter. In order to get a valid sequence, we need to backtrack along the path, do some loop unrolling, and explore another path which may not be the shortest path. For example, consider the sequence. This is obtained by backtracking one state from the previous path and unrolling the self-loop on once. The TCDF that we obtain now is shown in Fig. 10. This TCDF is indeed valid for testing the subtracter. During the TCDF generation, the status inputs that we need to dictate the flow are recorded, as shown in the figure. These inputs as well as the test vectors are fed into the test architecture from the primary input port, as explained later. In this manner, a TCDF is generated for each module in the circuit. For example, the TCDF obtained for testing the comparators is shown in Fig. 11. During testing, the status outputs of the data path become observable at primary outputs because of the test architecture used. Hence, the comparison operations have outputs which become primary output variables. Test sequences are generated from each TCDF by using the method given in [14], [15], and [28]. For example, in Fig. 10, we can test the subtracter by testing the operation mapped to it. This can be done by controlling the inputs and from the primary input ports, and observing the variable out after it is loaded into register REGO. Such test sequences are concatenated together to generate the global system-level test set. In a TCDF obtained for a module, the registers and multiplexers that are exercised in its path are automatically targeted for testing. However, if untested registers or multiplexers remain, they can be separately targeted, as mentioned before. Sometimes, the RTL circuit might be such that, no matter which sequence of states is taken, the required data flow is never obtained. An example of test multiplexer insertion was given earlier for Paulin. Consider another example circuit Barcode which performs the task of reading bar codes printed on objects. A portion of the circuit is shown in Fig. 12. Here, the left input of the adder is never connected to a primary input. Hence, in order to get controllability over this input, we add a -bit test multiplexer as shown in the diagram. If the input to a module is a constant, as is the right input of the adder in this case, it is assumed to be swept away during logic synthesis. Hence, in this case, controlling one port of the adder and providing the test vectors corresponding to the swept adder are sufficient. Finally, we must point out that although we use a certain degree of backtracking here, the search never explodes. This is because each loop is allowed to be unrolled a limited number of times, and the number of states in the controller is typically not large. If we cannot find a valid data flow, then we always have the option of adding a -bit test

9 714 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 8, AUGUST 1998 Fig. 11. TCDF for testing the comparators. Fig. 12. Part of RTL circuit Barcode showing the necessity for a test multiplexer. multiplexer to create the required flow. During system-level test set generation, we also target the test multiplexers that we add for testability. The select input of the test multiplexer and one input (output) port is fully controllable (observable), as explained later. We just need a set of four vectors to test a multiplexer. Hence, the test multiplexers are inherently quite testable. C. Tackling Chained, Multicycled, and Pipelined Modules TCDF extraction in the case of chained, multicycled, and pipelined modules is tackled in a special way. These techniques are depicted in Fig. 13. If two modules are chained, an intermediate variable is created at the junction of the two modules, as shown in Fig. 13(a). This variable is not bound to any register. However, it may be used for setting objectives for test environment generation and targeted for test multiplexer insertion. Whether a module is multicycled (i.e., takes more than one cycle to execute) can be determined easily, given the delay of the module from the module library and the clock cycle time of the RTL circuit. If a module is multicycled, its inputs stay unchanged for more than one clock cycle. Its output registers load only after the appropriate number of cycles. This leads to data flow extraction in the manner shown in Fig. 13(b). A multiplier, which executes over four cycles, is modeled as if its inputs are kept unchanged for four cycles, and it is executed in the fourth cycle. This is only done to ease test environment generation. It does not imply slowing down the clock while testing. This modeling is valid for testing purposes as long as we do not make use of any test multiplexer at the input of the multiplier in the intermediate cycles. This can be ensured by noting that the module is multicycled before any test multiplexer insertion starts. In case of pipelined modules, the information that the module is pipelined should be available in the module library. A variable queue is required for such a module. The size of the queue depends on the number of pipeline stages in the module. In Fig. 13(c), we show a queue with three pairs of variables for a pipelined multiplier with three stages. Whenever there are live variables at the inputs of the multiplier, its input variable pair is inserted into the first slot of the queue in the next cycle. The variable pair in the queue is pushed forward one step in each cycle. If any register at the output of the module loads when a variable pair exits the queue, a multicycled operation is born in the TCDF. The multicycled operation is treated in the manner mentioned above. In the example in Fig. 13(c), we have assumed that the output of the pipelined multiplier is not loaded in any register after the second multiplication is executed on it. Thus, the pipelined multiplier is modeled as two multicycled operations for testing purposes. D. Testing Untested Multiplexers Many multiplexers get tested while testing the modules and registers. We next explain how the remaining untested multiplexers are tested. It is easy to determine that the following test set, if fed to each bit slice of a 2-to-1 multiplexer (assuming an AND OR two-level implementation), will detect all single stuck-at faults in it: (corresponding to the 0-input, 1-input, select). This means that a multibit 2-to- 1 multiplexer should propagate the all-ones vector through both of its input ports, and its output should be observed (this corresponds to the first two vectors). For the next two vectors, the multiplexer should propagate the zero vector while its idle input port is supplied with the all-ones vector. This requirement at the idle port poses a problem in the sense that

10 GHOSH et al.: DESIGN FOR TESTABILITY TECHNIQUE 715 (a) (b) Fig. 13. Tackling chaining, multicycling, and pipelining. (c) the value at the idle port does not directly correspond to any value in the TCDF. However, this problem can be solved by careful analysis of the TCDF and the RTL circuit. This is explained through an example next. Consider multiplexer in Fig. 1. The 0-input of the multiplexer is connected to LATCH while the 1-input is connected to LATCH. The output of feeds the right input of subtracter SUB. From the TCDF shown in Fig. 4, we find when a variable mapped to LATCH is the right input to an operation mapped to SUB. We find that variable and operation 2 constitute such a pair. Hence, the objectives for deriving the test environment of corresponding to the first test vector are and. There is no requirement at the left input port of the subtracter. It can be verified by traversing the TCDF back from to the primary inputs that can be satisfied with all-ones. is trivially achieved since is a primary output. For the second test vector, we look for an operation mapped to SUB which has a variable mapped to LATCH as its right input. Operation 1 and variable constitute such a pair. Thus, the objectives for the test environment corresponding to the second test vector are and. These are also satisfiable with all-ones and. For the third test vector, we have to do an idle-port analysis, i.e., when operation is executed by SUB and it uses the contents of LATCH, we need to know the live variable residing in LATCH at that point. This live variable is (although variable is not bound to LATCH, it loads this value, as a latch loads by default in all cycles). Therefore, the objectives for deriving the test environment of this vector are and. These objectives are satisfied by all-ones. For the last test vector, we see that the idle port of is connected to variable which gets loaded into LATCH by default. Thus, the test objectives are, and. These objectives are satisfied by all-ones and. Thus, using these four test environments, the multiplexer can be completely tested. E. Reducing the Global Test Application Time If test environments are sequentially generated for each module or register and used to obtain the corresponding system-level test set, there may be an unnecessary penalty paid in the test application time. We use two basic techniques to reduce the global test application time: parallel test environment generation and test simulation. To understand the concept of parallel test environment generation, consider Fig. 14. This figure shows the generation of three test environments to test three different modules using a single TCDF. It can be seen that the test environment for multiplier MULT1 and that of subtracter SUB1 do not overlap, i.e., the two sets of inputs required to be justified in the two cases are disjoint. Hence, these two modules can be tested in parallel. Thus, a postprocess phase is added to the testability analysis procedure that tries to merge test environments of two or more modules and registers. This is done by simply checking whether or not two test environments share any primary input/output variables. Even if primary input variables are shared, test environments can still be merged if the objective required in the two test environments for that variable do not conflict (i.e., both test environments require the same value to be justified at that variable). This reduces the final system-level test set size. This merging process has a greater chance of success as the number of inputs and outputs of the TCDF increases.

11 716 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 8, AUGUST 1998 Fig. 14. Parallel test environment generation. The system-level test set is also compacted using test simulation. In this technique, while testing a module with its test environment, we do an RTL simulation to see if some other modules, registers, or multiplexers in the test path get a test vector from their precomputed test set coincidentally. These vectors are deleted from the corresponding precomputed test set. When these other modules, registers, or multiplexers are targeted later, their corresponding system-level test set is smaller since fewer vectors from their precomputed test set need to be considered. Even smaller test set sizes can be obtained by using -testable modules in the data path. Note that registers, multiplexers, adders, and subtracters are inherently testable. A multiplier can be made testable with a small area and delay overhead (typically less than 2%). Thus, if such modules are available in the design library, they can sometimes result in a significant further reduction in test application time at a marginal increase in area and delay. However, in the experimental results section, we do not exploit this feature in order to establish the efficacy of our scheme, even when such modules are not available in the library. F. The Test Architecture The method of testing an RTL circuit discussed so far would be incomplete without specifying the test architecture, which we explain next. If -bit test multiplexers are placed in the RTL circuit, there are multiplexer select inputs which have to be controlled. A low-overhead solution to this problem is shown in Fig. 15. In this figure, the added DFT hardware is shaded grey. (We assume one extra pin to provide the Test mode signal.) The controller outputs are multiplexed with a data path primary output port to facilitate testing of the controller [15]. This multiplexer does not result in a delay overhead, as the delay of a multiplexer or even a multiplexer tree at the output of a primary output register is usually much less than the clock period. Even without this added test multiplexer, normally, the last clock cycle is devoted to transferring the values from the primary output register to the primary output port. In case of circuits with conditionals, the status signals are made directly observable by multiplexing the status signal lines from the data path with an output port, and are made directly controllable by feeding the status register input from a primary input port. A register, called the test configuration register (TCR), is added to the RTL circuit. The input of this register is connected to the low-order bits of an input port. The load signal of TCR is connected to the Test pin. Its reset signal is connected to the controller reset (recall that only TCR and the controller state register are assumed to be resettable in our scheme; none of the data path registers is assumed to be resettable). TCR feeds: 1) the select signals of the test multiplexers that are added to the circuit, and 2) two bits and that control the loading of the controller state register and selecting of the output multiplexer. The load enables of the data path and controller registers are qualified with the inverted Test signal to ensure that the data path and controller registers freeze their state while TCR and the status register are being loaded. If there are latches in the data path, they need to be replaced with registers with their load signals fed by the inverted Test signal. Writing into TCR results in the circuit being reconfigured to provide controllability and/or observability as required. When we reset TCR, all of the testmultiplexer select lines are 0. Hence, the normal data-path configuration exists. The Test signal and signals and should also be 0 for normal operation. In the test architecture in Fig. 15, it is assumed that control chaining is used in the original circuit to reduce the number of cycles needed in an iteration. In such designs, care is taken to prevent asynchronous feedback loops between the data path and the controller. In this case, we have to place the status register before multiplexer in the test architecture as shown in the figure. Therefore, the status register becomes a test overhead. In other designs, however, the status register may already be present between the data path and the controller. In that case, we place the multiplexer before the status register, and the status register is not an overhead. However, for experimental results given later, we treat the status register as an overhead. Let us now see how the above configuration can be used to test the whole circuit. The data path and the controller are tested separately. While testing the data path, the TCDF gives a suitable control flow which is achieved by controlling the status register from a primary input port at appropriate cycles. Signals and are set to 1 and 0, respectively, for testing the data path modules other than the comparators. Only at specified cycles, when we need to reconfigure the data path using the test multiplexers, do we assert the Test pin. This

12 GHOSH et al.: DESIGN FOR TESTABILITY TECHNIQUE 717 Fig. 15. Test architecture used in the scheme. freezes the whole circuit for a cycle while loading TCR with the correct test-multiplexer select pattern and simultaneously loading the status register with the required status signals from the primary input port. In certain cycles, however, we might need to load only the status register or TCR, i.e., we either need to get a new conditional input vector to the controller or reconfigure the test multiplexers, but not both. Since we know the value that should be present in each cycle at either of the registers, we can feed the correct default value that should exist in the register that we do not need to load from the primary input port. While testing the data path comparators, we need to observe the status signals coming out of the data path to get full observability of the comparator outputs. In this case, we need to keep signals and at 0 and 1, respectively. While testing the controller, we make the Test signal high to load the status register. Thus, we can directly control the controller inputs using the primary input port. The controller outputs are directly observable at the primary output port. We assert signals and to force the state register to load in all cycles while the controller is being tested. In some rare cases, it might so happen that the sum of the number of controller output bits and the status output bits exceeds the number of output bits of the data path. In that case, instead of a 2-to-1 multiplexer at the output port, we will have to use a -to- multiplexer and increase the number of control signals (like and ) in TCR. Hence, the observation will have to proceed through multiple cycles while the circuit remains frozen. Similarly, if the size of TCR is larger than the total number of primary input port bits, then TCR will have to be loaded through multiple cycles. However, as the number of test multiplexers required is typically quite small (between zero and six for the benchmarks considered), this kind of a situation will arise rarely. Although the above discussion assumed edge-triggered flipflops and a single-phase clock, similar arguments can be shown to hold for multiphase and level-triggered clocking schemes as well. III. THE DFT PROCEDURE Fig. 16 shows the top-level pseudocode that we use to generate the system-level test set of an RTL circuit. The procedure takes as input an RTL circuit, design library, and an integer limit which is used to specify that, while searching for a TCDF with a state machine, the number of states in the search tree is not to exceed limit. How to find a suitable number for limit is discussed later. We first extract the state transition information from the RTL circuit controller. If it is a circuit without conditionals, the state machine is already in the form of a Moore machine. Else, we convert the state machine to an equivalent Moore machine. Well-known algorithms exist for this purpose that split a state with different

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