Classification of Digital Circuits
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1 lassification of igital ircuits ombinational. Output depends only on current input values. Sequential. Output depends on current input values and present state of the circuit, where the present state of the circuit is the current value of the devices memory. Also called finite state machines.
2 State of a ircuit The contents of storage elements. A collection of know internal signal values that contain information about the past necessary to account the future behavior of the circuit.
3 lock Signal that determines the change of state in most sequential circuits. (a) state changes occur here t H t L period = t per t per frequency = / t per duty cycle = t H / t per (b) state changes occur here _L t L t H t per duty cycle = t L / t per igital esign Principles and Practices, 3/e
4 Bi-stable Elements The simplest sequential circuit. It consist of a pair of inverters connected as shown below. Notice the feedback loop. V in V in2 V out V out2 _L igital esign Principles and Practices, 3/e
5 igital Analysis Two stable states. If is HIGH then the lower inverter has a HIGH at its input and a LOW at its output. This in turn forces the upper inverter s input to be LOW and its output to be HIGH. If is LOW then the lower inverter has a LOW at its input and a HIGH at its output. This in turn forces the upper inverter s input to be HIGH and its output to be LOW.
6 Analog Analysis onsidering the steady state behavior of the bistable element. V stable out = V in2 metastable stable Transfer function: V out = T(V in ) V out2 = T(V in2 ) V in = V out2 V in = T(V in2 ) V in = T(V out ) V in = T(T(V in )) V in = V out2 igital esign Principles and Practices, 3/e
7 Analog Analysis Metastable behavior: onsider the middle intersecting point in the diagram shown below. V stable out = V in2 metastable What would happen if a small amount of noise varies either input voltage. V in = V out2 stable igital esign Principles and Practices, 3/e
8 Analog Analysis The drawing on this slide shows a very good analogy to the stable and metastable behavior of a bistable element. stable metastable stable
9 Latches and Flip-Flops Binary cells capable of storing bit of information. Generates one of two possible stable states. Two outputs labeled and. One or more inputs.
10 Latches and Flip-Flops These sequential devices differ in the way their outputs are changed: The output of a latch changes independent of a clocking signal. The output of a flip flop changes at specific times determined by a clocking signal.
11 S-R Latch R S R last N last N (a) S N (b) igital esign Principles and Practices, 3/e SR latch based on NOR gates. The S input sets the output to while R reset it to.
12 S-R Latch R S R last N last N (a) S N (b) igital esign Principles and Practices, 3/e When R=S= then the output keeps the previous value. When R=S= then = =, and the latch may go to an unpredictable next state.
13 S-R Latch S S S R N R R N (a) (b) (c) igital esign Principles and Practices, 3/e ouble negation is not a good idea. It is confusing and it creates problems.
14 S-R Latch S R () (2) t plh(s) t phl(r) t pw(min) igital esign Principles and Practices, 3/e S R (a) N (b) igital esign Principles and Practices, 3/e
15 S -R Latch igital esign Principles and Practices, 3/e (a) S_L (b) (c) S_L R_L N or S R_L N last last N or R S R S R latch based on NAN gates. The S input sets the output to while R reset it to.
16 S -R Latch igital esign Principles and Practices, 3/e (a) S_L (b) (c) S_L R_L N or S R_L N last last N or R S R When R =S = then the output keeps the previous value. When R =S = then = =, and the latch may go to an unpredictable next state.
17 S-R Latch With Enable The outputs change only when the enable input is asserted. igital esign Principles and Practices, 3/e (a) S (b) S R last N last N (c) S R R N x x last last N
18 S-R Latch With Enable S Ignored since is. Ignored until is. R N igital esign Principles and Practices, 3/e Notice that the outputs only change when the input is asserted.
19 Latch This latch eliminates the problem that occurs in the S R latch when R=S=. is an enable input: When = then the output follows the input and the latch is said to be open. ue to this fact this latch is also called transparent latch. When = then the output retains its last value and the latch is said to be closed. N N x last last N (a) (b) (c) igital esign Principles and Practices, 3/e
20 Latch N N x last last N (a) (b) (c) igital esign Principles and Practices, 3/e igital esign Principles and Practices, 3/e
21 Latch () (2) (3) (4) (5) t phl() t phl() t hold t plh() t plh() t plh() t setup For proper operation the input must not change during a time interval around the falling edge of. This time interval is defined by the setup time t setup and the hold time t hold.
22 Edge Triggered Flip-Flop This flip-flop is made out of two latches. The first latch is the master, and the second the slave. When _L = the master is open (on) and the slave is closed (off). m and s follow m. N _L N _L (a) (b) x x last last last N last N (c) igital esign Principles and Practices, 3/e
23 Edge Triggered Flip-Flop When _L = the master is closed, the slave is open and m is transferred to s. Note that s does not change if m changes because the master latch is closed leaving m fixed. N _L N _L (a) (b) x x last last last N last N (c) igital esign Principles and Practices, 3/e
24 Edge Triggered Flip-Flop Positive edge-triggered flip-flop. * = igital esign Principles and Practices, 3/e (a) M N (b) N (c) x x last last last N last N M N igital esign Principles and Practices, 3/e
25 Edge Triggered Flip-Flop t hold t plh() t phl() t setup If the set-up and hold times are not met the flip-flop s output will go to a stable, though unpredictable, state.
26 Edge Triggered Flip-Flop (a) (b) PR_L PR LR N LR_L igital esign Principles and Practices, 3/e Asynchronous inputs are used to force the output of the flip-flop to a particular state. PR (preset) =. LR (clear) =.
27 Edge Triggered Flip-Flop (a) (b) PR_L PR LR N LR_L igital esign Principles and Practices, 3/e PR_L LR_L N igital esign Principles and Practices, 3/e
28 Edge Triggered Flip-Flop Edge triggered flip-flop with enable. (a) (b) (c) EN N EN N x last last N EN x x last last N x x last last N
29 Scan Flip-Flop This flip-flop allows its inputs to be driven from alternate sources, which can be very useful during device testing. TE TI TE x x N x TI x x x x last N last N TE TI (a) (b) x x x last last N (c) external pins ASI TE TE TE TE TI TI TI TI TI TO TE igital esign Principles and Practices, 3/e
30 Master/Slave S-R Flip-Flop The postponed output indicator shows that the output signal does not change until the enable input is negated. Flip-flops with this kind of behavior are called pulse-triggered flip-flops. * = S+R SR = igital esign Principles and Practices, 3/e (a) S R S R M M_L S R N (b) S x R N x last last N last last N (c) S R undef. undef.
31 Master/Slave S-R Flip-Flop S Ignored since is. Ignored until is. Ignored until is. R M M_L N igital esign Principles and Practices, 3/e
32 Master/Slave J-K Flip-Flop The J and the K inputs of the J-K flipflop are analogous to the S and R inputs of the S-R flip-flop, except in the case where J=K=. In this case the outputs of the J-K flip-flop will toggle to the opposite state. igital esign Principles and Practices, 3/e (a) (b) (c) J K S R M M_L S R N J x K N x last last N last last N J K last N last
33 Master/Slave J-K Flip-Flop * = J +K igital esign Principles and Practices, 3/e (a) (b) (c) J K S R M M_L S R N J x K N x last last N last last N J K last N last Ignored since is. Ignored since N is. Ignored since is now. Ignored since is. Ignored since N is. J K M M_L N igital esign Principles and Practices, 3/e
34 Edge Triggered J-K Flip-Flop * = J +K igital esign Principles and Practices, 3/e (a) J K N (b) J x x K N x last last N x last last N last last N (c) J K last N last J K igital esign Principles and Practices, 3/e
35 Edge Triggered J-K Flip-Flop 74LS9 PR_L LR_L N J K_L igital esign Principles and Practices, 3/e
36 T Flip-Flop Flip-flop changes state every tick of the clock. * = (a) (b) T N T J K N igital esign Principles and Practices, 3/e (a) T (b) T igital esign Principles and Practices, 3/e
37 T Flip-Flop With Enable Flip-flop changes state every tick of the clock when enable is asserted. * = EN +EN (a) EN T N (b) EN T J K N igital esign Principles and Practices, 3/e (a) (b) EN EN T T igital esign Principles and Practices, 3/e
38 locked Synchronous State-Machine Analysis State machine Another term for a sequential circuit. locked Refers to the fact that their flip-flops employ a clock input. Synchronous Same clock signal is used by all flip-flops. A state machine with n flip-flops can have up to 2 n distinct states.
39 State Machine Structure State memory a set of n flip-flops. Next-state logic combinational logic circuit which determines the next state. Next-state = F(current state,input) Output logic combinational logic circuit which determines the output. There are two models for the output logic: Mealy Model. Moore Model.
40 Mealy Model The output is based on both current state and input. Output = G(current state,input) inputs Next-state Logic F excitation State Memory current state Output Logic G outputs clock input clock signal igital esign Principles and Practices, 3/e
41 Moore Model The output is based on current state only. Output = G(current state) In high speed circuits the output circuit may be absent and the output is generated directly from the flip-flop s outputs. This is called output coded state assignment. inputs Next-state Logic F excitation State Memory current state Output Logic G outputs clock input clock signal igital esign Principles and Practices, 3/e
42 Mealy Model Pipelined outputs a design approach that ensures the output of a Mealy model circuit only changes with the clock. inputs Next-state Logic F excitation State Memory current state Output Logic G Output Pipeline Memory pipelined outputs clock input clock input clock signal igital esign Principles and Practices, 3/e
43 Analysis etermine the next-state and output functions F and G. Use F and G to construct a state/output table that completely specifies the next state and output of the circuit for every possible combination of current state and input. raw a state diagram.
44 State Machines With Flip-Flops = EN + EN = EN + EN + EN Next-state Logic F State Memory Output Logic G output EN input EN EN excitation MAX clock signal current state igital esign Principles and Practices, 3/e
45 State Machines With Flip-Flops * = * = * = EN + EN * = EN + EN + EN Next-state Logic F State Memory Output Logic G output EN input EN EN excitation MAX clock signal current state igital esign Principles and Practices, 3/e
46 State Machines With Flip-Flops MAX = EN Next-state Logic F State Memory Output Logic G output EN input EN EN excitation MAX clock signal current state igital esign Principles and Practices, 3/e
47 State Machines With Flip-Flops * = EN + EN * = EN + EN + EN MAX = EN Present State Input Next State Output EN * * MAX Present State Input Next State Output S EN S* MAX A A A B B B B A
48 State Machines With Flip-Flops (a) EN (b) EN (c) EN S S A A B A A, B, B B B B,,,, A, A, S S, MAX Table 7-2 Transition, state, and state/output tables for the state machine in Figure 7-38.
49 State Machines With Flip-Flops (a) EN (b) EN (c) EN S S A A B A A, B, B B B B,,,, A, A, S S, MAX Table 7-2 Transition, state, and state/output tables for the state machine in Figure EN = EN = (MAX = ) A EN = (MAX = ) B (MAX = ) EN = (MAX = ) EN = (MAX = ) EN = EN = (MAX = ) EN = (MAX = ) (MAX = ) igital esign Principles and Practices, 3/e
50 State Machines With Flip-Flops EN = EN = (MAX = ) A EN = (MAX = ) B (MAX = ) EN = (MAX = ) EN = (MAX = ) EN = EN = (MAX = ) EN = (MAX = ) (MAX = ) igital esign Principles and Practices, 3/e LOK EN MAX MAXS STATE A A B A A igital esign Principles and Practices, 3/e
51 State Machines With J-K Flip- Flops
52 locked Synchronous State Machine esign erive a state/output table from the problem specification. Minimize the number of states in the state/output table by eliminating equivalent states. hoose a set of state variables. Assign to each state a unique combination from the set derived above. reate a transition/output table. hoose a flip-flop type and derive its excitation table. Using the excitation table fill the values for the input excitation function columns on the transition/output table. erive the excitation and output equations. raw logic diagram.
53 locked Synchronous State Machine esign esign a sequential circuit with one input ( I ) and one output ( Z )The output is asserted when the input sequence -- is received. See state/output table below. Present State Init S S S Input I Next state Output Z S Init S S S S S S
54 locked Synchronous State Machine esign Set of state variables and their unique assignment to the different states. State Init S S S
55 locked Synchronous State Machine esign Transition/output table Present State Input Next state Output I * * Z
56 locked Synchronous State Machine esign Excitation table. Present State Next State Required inputs J K T X X X X
57 locked Synchronous State Machine esign Present State Input Next state Output Input Excitation I * * Z J K J K X X X X X X X X X X X X X X X X Equations derived from the table above: J = I K = I J = I K = I Z =
58 locked Synchronous State Machine esign Logic diagram. J = I K = I J = I K = I Z =
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