Design and Evaluation of Pulse Triggered Flip-Flop Based on Split Output TSPC Latch for Low Power High Performance Digital Circuit

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1 Design and Evaluation of Pulse Triggered Based on Split Output TSPC Latch for Low Power High Performance Digital Sandeep Singh Gill 1 and Gurinderjit Kaur 2 1, 2 Guru Nanak Dev Engineering College, Ludhiana, India 1 ABSTRACT In this paper a Pulse Triggered based on Split Output TSPC Latch suitable for low power high performance application is proposed. The Pulse Triggered is constructed using a split output TSPC latch. flip-flop has the advantages of simple structure, less number of transistors, low dissipation power and lower transistor area. circuit is simulated in cadence analog design environment 0.25µm CMOS technology. Simulation results show that by using the proposed circuit, dissipation power can be reduced by 40%, number of transistors by 40%, current drawn by 48% and transistor area can be reduced by 68%. KEYWORDS: Pulse triggered flip-flops (PTFF), Split Output TSPC latch, Semi dynamic flip-flop (SDFF), Hybrid latch flip-flop (HLFF), Embedding, Low power. 1. INTRODUCTION Most digital circuits today are constructed using static CMOS and edge- triggered flip-flops. Although such techniques have been adequate in the past and will remain adequate in the future for low performance design, they will become inefficient for highperformance components as the number of transistors are increasing resulting in increase of area. Some conventional high performance flip-flops like Hybrid Latch (HDFF) and Semi Dynamic (SDFF) have the disadvantage that they have large amount of power dissipation due to redundant transistors at internal nodes, including the issue of increase in the number of transistors. Designers will therefore need to adopt new techniques and circuits that can improve the performance by lowering power dissipation and area of the design for low power digital circuits less number of transistors. 2. REVIEW OF EXISTING FLIP-FLOPS A design was developed by Sun Microsystems Inc. used in UltraSPARC-III micro-processors using a Semi Dynamic Flip- Flop, proposed by Fabian Klass 0.25 µm CMOS technology. This design had short latency, Small clock load low power consumption. This design was bulky having large number of transistors and required larger area on die. This design was improved by Arnab Ghosh from university of Idaho same Semi Dynamic (SDFF) by scaling and [1], [2]. The flip-flop on a 1 bit adder consisting carry and sum functions was implemented and by the use of scaling and timing parameters and area were improved. These improvements were achieved the penalty of bulk in circuit, large delay, large setup and hold time. This design is considered as a benchmark for this paper [1]. This section will discuss the used structure of Flip-flop i.e. Semi-Dynamic (SDFF) and the conventional high speed i.e. Hybrid-Latch (HLFF). The circuit diagram of a Semi-Dynamic (SDFF) is shown in Fig. 1. The circuit is ISBN: SDIWC 137

2 faster than TSPC but still has some shortcomings. First, internal node X is truly dynamic, i.e. it is not actively driven by any device during most of the evaluation phase. Second, output Q is high impedance when the clock signal is low. The circuit is composed of a dynamic front-end and a static back-end. The flop samples input D and produces output QB, which is the complement of D. The circuit operates as follows. On the falling edge of clock CLK, the flop enters the precharge phase. Fig.1. Semi Dynamic (SDFF) Node X is precharged high, cutting off node Q from the input stage. The evaluation phase begins the rising edge of clock CLK. If input D is low, node X would remain high. Node Q would either remain low or will be discharged through transistors. The circuit diagram of Hybrid Latch is shown in Fig.2. having negative setup time in generating pulse which gives small D-Q delay. It also has small -embedding small penalty. As mentioned earlier this Flip-flop has the disadvantage of large amount of power dissipation [3-13]. 3. PROPOSED FLIP-FLOP To overcome the disadvantages of Design using Semi Dynamic and Conventional high speed flip flops we proposed a Pulse Triggered Flip- Flop based on split output TSPC latch. It has a simpler structure composed of five transistors and back to back inverters. It is a positive latch if it is triggered by the rising edge of the clock. Back to back inverters enhance the robustness of its output operation. flip-flop can reduce the power dissipation, current drawn, transistor count, total transistor width and estimated transistor area. Fig.3 Shows the diagram of Pulse Triggered based on split output TSPC latch. In proposed circuit clock is applied to pull up circuit to fulfill the need to have a mirror circuit of pull down to implement the. Clock is also applied to NMOS at the middle to trigger the circuit, data is applied to pull down circuit. Fig.2. Hybrid Latch (HLFF) The circuit of Hybrid Latch consists of two stages: the front end function as pulse generator and the back end is to capture the pulse as a latch. It has the advantage of Fig.3. PTFF based on Split output TSPC latch This circuit will also avoid bulk in the design as compared to Semi Dynamic s (SDFF) as it do not consists of any redundant ISBN: SDIWC 138

3 transistors at internal node. An inverted clock is applied to PMOS connected at X and Y node to remove the potential difference between both the nodes. This gate here behaves like a pass gate. At the back end we have cross coupled inverters which is a basic storing element also, it increases the robustness of the circuit. In this cross coupled inverters, width of feedback inverter should be greater than the width of feed through inverter. 4. EMBEDDING LOGIC FUNCTION Fig.4. PTFF based on split output TSPC latch Embedding function is an important technique using which we can easily incorporate most functions into flop, such as wide OR functions, multiplexers and complex gates. Fig.4. shows the Pulse Triggered based on split output TSPC latch Sum and Carry functions. It will reduce the number of combinational stages and clock cycles, which will provide high throughput of the design. 5. SIMULATION RESULTS In this experiment we implemented the design of 1-bit registered adder having sum and carry function using Semi Dynamic Flip-flop [1] discussed in this paper and the proposed Pulse Triggered Flip-flop based on split output TSPC latch. We also simulated and analyzed both the designs using Cadence analog design environment. We compare the transistor count, total transistor width, estimated transistor area, current drawn, power dissipation, C-Q, C-Q, D-Q. D-Q, Set up and hold times and transparency pulse width of circuit. The experiment conditions are shown in Table.1. Simulation results are shown in Table.2 to Table.10. In this experiment all the flip-flops have the same data rate and all transistor sizes are optimized to achieve the desired results. The rise time and fall time of the input signal are 100ps. We can see that Transistor count of the proposed flip-flop is 15, it consists of 19 transistors and for 1 bit registered transistor count is 90 in Table.2. In Table.3, we compare the Total Transistor Width which is µm for 1-bit registered. We also compare Estimated Transistor Area which is µm 2 for proposed circuit and µm 2 for benchmark [1] in Table.4. In Table.5 transparency pulse width is given, which is 205ps and 180ps for Semi Dynamic Flip-Flip (SDFF) and Pulse Triggered Flip- Flop Based on split output TSPC latch respectively. In Table.6 we compare the Set up and Hold time of the proposed and benchmark [1]. We can see at the fall edge the C-Q for benchmark circuit is 120.3ps and for the proposed circuit it is 189.3ps, at the rise edge the C-Q for benchmark circuit is 276.5ps and for the proposed circuit it is 215ps given in Table.7. In Table.8 we can see at fall edge the D-Q for benchmark circuit is146ps and for the proposed circuit it is 207.9ps, at the rise edge the D-Q for benchmark circuit is 293.1ps and for the proposed circuit it is 228.3ps. Table.9 shows the comparison between Current drawn of both the designs which is 0.7nA and 0.23nA for benchmark and the proposed circuit respectively. Power dissipation is also compared in Table.10 ISBN: SDIWC 139

4 which is 1.4nW for benchmark circuit and 0.445nW for the proposed circuit. Table 4. Estimated Transistor Area Table 1. Experiment Conditions Design Specification Work Technology 0.25um 0.25um TSMC deep TSMC deep MOSFET submicron submicron Model 0.25um 0.25um Conditions Nominal Nominal Supply Voltage 2V 2V Temperature 25 degree C 25 degree C Rise time of input signal 100ps 100ps Fall time of input signal 100ps 100ps Clock frequency 100 MHz 100 MHz Clock duty cycle 50% 50% Delay calculations Between 50% points Between 50% points design (µm 2 ) bit registered design (µm 2 ) Table 5. Transparency Pulse Width of the design (ps) design (ps) Table 2. Transistor Count Transistor count bit registered Table 3. Total Transistor Width design (µm) design (µm) bit registered full adder Table 6. Set up and Hold times design Virtual Real (ps) (ps) design Virtual (ps) Real (ps) Setup time Hold time ISBN: SDIWC 140

5 Table 7. Comparison of C-Q Clk Q (ps) Clk (ps) (LH) (HL) (LH) (HL) design design Table 8. Comparison of D-Q D Q (ps) (ps) (LH) (HL) (LH) (HL) design design Table 10. Power Dissipation design (nw) design (nw) bit registered CONCLUSION A Design using Pulse triggered based on split output TSPC latch is proposed and simulated in a 0.25µm process. Our simulation results justify our analysis that we reduced power dissipation by 40%, transistor area by 68%, transistor count by 40% and current drawn by 48% out affecting the high performance of the circuit. ACKNOWLEDGEMENT The authors thank Guru Nanak Dev Engineering College, Gill Road, Ludhiana, for technical support for implementation and simulation. Table 9. Current Drawn design (na) design (na) bit registered REFERENCES [1]. A. Ghosh, Evaluation of semi dynamic flip-flops for low power, High performance s, University of Idaho: MS Dissertation, [2]. F. Klass, Semi-Dynamic and dynamic s Logic, Digest of Technical Papers, IEEE Symposium on VLSI s, Honolulu, HI, USA, pp , June [3]. F. Klass, C. Amir, A. Das, K. Aingaran, C. Truong, R. Wang, A. Mehta, R. Heald, and G. Yee, A new family of semi-dynamic and Dynamic flip flops ISBN: SDIWC 141

6 for high performance processors, IEEE Journal of Solid State s, vol.34, no.5, pp , May [4]. G. Yee, Dynamic design and synthesis using clock-delayed domino, University of Washington: Ph.D. Dissertation [5]. H. Partovi, H. Partovi, R. Burd, U. Salim, F. Weber, L. DiGregorio, D. Draper, Flow through latch and edge triggered flip-flop hybrid elements, ISSCC, Digest of Technical Papers, pp , Feb [6]. J.M Rabaey, Digital Integrated circuit: A design prospective, Prentice Hall, [7]. J.F Lin, Low-power pulse triggered flip flop design using gated pull-up control scheme, Department of information and communication Engineering, Chaoyang University of Technology, Taiwan, [8]. J. Kennedy, R. Eberhart, Particle Swarm Optimization, Proceedings of IEEE international Conference on Neural Network, vol. 4, pp , Nov/Dec [9]. J.Yuan and C. Svensson, High-speed CMOS circuit techniques, IEEE Journal of Solid-State s, vol. 24, pp , Feb [10]. K.Roy and S. Prasad, Low- power CMOS VLSI Design. New York: John Wiley and Sons, Inc., [11]. U. Ko, A. Hill, and P.Balsara, Design techniques for high-performance, energy-efficient control, IEEE International Symposium on Low Power Electronics and Design, pp , Aug [12]. V. Stojanovic, V. Oklobdzija, and R. Bajwa, A unified approach in the analysis of latches and flipflops for low power systems Proceedings of IEEE International Symposium on Low Power Electronics and Design, Monterery, CA, pp , Aug [13]. Y. Hu and R. Zhou, Low clock swing TSPC flip flops for low power applications, J Syst Comp., vol. 18, Issue 01, February ISBN: SDIWC 142

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