FACULTY OF ENGINEERING LAB SHEET EEE1036 DIGITAL LOGIC DESIGN TRIMESTER 3, 2015_2016
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1 EEE06: Digital Logic Design, Lab Exp. DL FACULTY OF ENGINEERING LAB SHEET EEE06 DIGITAL LOGIC DESIGN TRIMESTER, 05_06 DL - Flip-Flops and Their Applications *Note: On-the-spot evaluation may be carried out during or at the end of the experiment. Students are advised to read through this lab sheet before doing experiment. Your performance, teamwork effort, and learning attitude will count towards the marks. Page of 0
2 EEE06: Digital Logic Design, Lab Exp. DL Objective EEE06: DIGITAL LOGIC DESIGN EXPERIMENT : Flip-flops and Their Applications The objective of this experiment is to introduce students to flip-flops and their applications. Note: There are three parts in this experiment. They are:. flip-flop. Ripple binary counter using Flip-flop. Synchronous binary counter using Flip-flop You are required to complete all of them. Preparation Before starting the experiment, make sure that you have the following equipment and components. Equipment. DC power supply -. Function Generator -. Oscilloscope - Components. Breadboard -. IC 7408 (quad AND gate) -. IC 747 (dual - flip-flop) - 4. Resistor.Ω - 5. Resistor 4.7Ω - 6. LED - 7. Function generator probe - Experiment A: Design of Flip-flop (0 minutes) The next outputs of a sequential circuit depend on its inputs as well as its present state. It has a storage capacity. Flip-flops are the basic building blocks of sequential circuits. Common flip-flop types are S-R, D, and T. The flip-flop is regarded as the most versatile one. Normally, it functions as S-R flip-flop ( refers to set, refers to reset). It can be used to design both D and T flip-flops. The characteristic table of the flip-flop is given in Table.. Table. flip-flop characteristic table Clock Present state Next state Mode of operation 0 x x 0 0 hold hold reset 0 0 set 0 0 toggle Page of 0
3 EEE06: Digital Logic Design, Lab Exp. DL SET Experimental Procedures Fig. flip-flop This part of the experiment will examine the functional behavior of flip-flop. The experiment setup is shown in Fig V + 5 V Oscilloscope CH 4.7 S S Oscilloscope CH 4 Hz 747 SET. Reset Squared pulses from SYNC OUT output at the rear panel of function generator Fig. flip-flop test setup By now you should be familiar with digital logic experiment procedures. The following description will be brief. Getting ready the power supply: Set the output voltage to +5V. Set the ammeter scale switch to LO (if any). Set the current adjustment knob to about ¼ turn from the min position. Connect the - output terminal to the GND terminal. Ask your supervisor if you have any query.. Make sure that the power supply is turned off. Connect two jumper wires from the DC power supply's +5V and GND (ground) points to two horizontally connected lines on your breadboard, respectively.. Insert one 747 IC on the breadboard. Note that you will use up to ICs in exp. B.. Distribute your ICs on your breadboard.. Please make sure that the IC and other components are placed firmly on the breadboard, otherwise, get a new breadboard from the lab. 4. Connect pin 4 of 747 IC to +5V. Page of 0
4 EEE06: Digital Logic Design, Lab Exp. DL 5. Connect pin of 747 IC to GND. 6. Complete the circuit connections as shown in Fig.. Use jumper wires as switches, including the reset switch. 7. Getting ready the function generator: Set the function generator to squared pulse generation mode. Select the 0 Hz frequency range button ( second counter gate time). Set the function generator's frequency to about Hz. 8. Make sure that the function generator is turned off. Connect the function generator probe to the function generator s SYNC OUT located at the rear panel (this output is TTL compatible). 9. Connect the positive line of the probe to pin of IC Connect the ground lead (long end) of the probe to the common ground point.. Getting ready the oscilloscope: Set time base scale to 0.5 ms/div and vertical scales to 5 V/div. Make sure that the VARIABLE of the TIME DIV is at the CAL position. Do not turn off the oscilloscope (warming up is required).. Connect the clock input and the flip-flop output to oscilloscope channel (CH) and channel (CH) respectively, as indicated in Fig... Verify your connections again. 4. Now you are ready for the experiment. Turn on the DC power supply. 5. Turn on the function generator. Observation. Complete Table R. in that sequence. Repeat this experiment to confirm your results.. eep S and S in the OPEN () state. Increase the clock frequency to Hz. Record the waveform of the flip-flop output (CH) with respect to the clock waveform in Fig R... Hold the reset button in closed (0) position. Observe the change of the waveform of the flip-flop output (CH). Record your observation in experimental result section. This is the end of this part of the experiment. Switch off the power supply, the function generator and the oscilloscope. Note that the circuit in Fig. will be used in the next experiment with some modifications. [ mark] Page 4 of 0
5 EEE06: Digital Logic Design, Lab Exp. DL Experiment B: Application of Flip-Flop Design of Binary Counter A binary counter is a kind of sequential circuit. It counts the input pulses appearing at its input. Counters can be designed in many different ways. Two basic types that will be covered in this experiment are:. Ripple binary counter and. Synchronous binary counter B.: Design of Ripple Binary Counter using Flip-flop (45 minutes) In a ripple or asynchronous counter, the change of state of each stage occurs after the state change in its previous stage. Such counters are easy to design. Its main disadvantage is that it is a slow counter. Toggle (T) flip-flops are used to design the counter circuit. T flip-flops can be easily designed using flip-flops by tying its inputs together to VCC. Fig. shows a T flip-flop constructed from a flip-flop. Clock SET Clock (a) Fig. (a) Toggle flip-flop and (b) output waveform (b) Page 5 of 0
6 EEE06: Digital Logic Design, Lab Exp. DL Your experiment will be to construct a -bit ripple binary counter. -bit counter requires T flip-flops. IC 747 contains flip-flops. Therefore, you need two 747 ICs. The circuit for the experiment is shown in Fig.4. ICA +5 V ICB Reset SET SET SET... Hz (SYNC OUT) 0 LSB MSB Fig.4 -bit ripple binary counter Experimental Procedures Note that ONLY TWO 747 ICs are used in this experiment.. Make sure that the power supply and the function generator are turned off.. Insert another 747 ICs on the breadboard. Note that you will use up to ICs ONLY in exp. B.. Distribute your ICs on your breadboard.. Please make sure that the IC and other components are placed firmly on the breadboard, otherwise, get a new breadboard from the lab. 4. Connect pin 4 and pin of this IC to +5V and GND, respectively. 5. Complete the circuit connections as shown in Fig Set the function generator's frequency to Hz (refer to procedure 6 and 7 in exp. A if necessary). You may need to reduce the frequency to Hz if you cannot record your results in the observation part. 7. Verify your connections again. 8. Now you are ready for the experiment. Turn on the DC power supply. 9. Push the reset button to reset all the flip-flops. It will turn off all the LEDs. 0. Turn on the function generator. Observation Complete Table R. in that sequence. Repeat this experiment to confirm your results. [ marks] This is the end of this part of the experiment. Switch off the power supply and the function generator. Note that the circuit in Fig.4 will be used in the next experiment with some modifications. Page 6 of 0
7 EEE06: Digital Logic Design, Lab Exp. DL B.: Design of Synchronous Binary Counter using Flip-flop ( hour) A synchronous binary counter's states change synchronously with the clock edge. This counter is faster than ripple binary counters. All the flip-flops in a synchronous binary counter share a common clock. A -bit synchronous binary counter circuit is shown in Fig ICA +5 V ICB Reset SET SET SET Hz (SYNC OUT).. 0. LSB MSB Experimental Procedures Fig.5 -bit synchronous binary counter. Make sure that the power supply and the function generator are turned off.. Insert one 7408 IC on the breadboard and connect pin 4 to +5V and pin 7 to GND.. Complete the circuit connections as shown in Fig Verify your connections again. 5. Now you are ready for the experiment. Turn on the DC power supply unit. 6. Push the reset button to reset all the flip-flops. It will turn off all the LEDs. 7. Turn on the function generator. Observation Complete Table R. in that sequence. Repeat this experiment to confirm your results. [ marks] At the end of this experiment: switch off all the equipment, open all the connections and return all the components used. Summary In this experiment, you have learned how to design, analyze and evaluate a binary counter. Page 7 of 0
8 EEE06: Digital Logic Design, Lab Exp. DL Pin Layout for 747 Dual - Flip-Flop APPENDIX Testing - flip-flop: Use Fig. and operate the flip-flop in toggle mode.. Connect input, input and CLR to +5V.. Test the flip-flop using clock and.ω + LED. The LED will be ON and OFF alternately.. Disconnect CLR from +5V and connect it to GND. The LED will be OFF regardless the clock trigger. Pin layout for 7408 quad -input AND gates Testing AND gate: Each AND gate is tested according to the truth table. Input Output Input connected to ground is logic 0. Input not connected to ground is logic. Use.Ω+LED or multimeter (V mode) to indicate output state. Page 8 of 0
9 EEE06: Digital Logic Design, Lab Exp. DL result and mark sheets Student ID Name.. Major. EXPERIMENTAL RESULTS AND DISCUSSIONS Exp. A: flip-flop Analysis. Table R.: Observation results of - flip-flop Operational sequence S S LED (ON/OFF) Mode of operation 0 (Push the reset button) CLS (0) CLS (0) OFF (Release the reset button) CLS (0) CLS (0) OPEN () CLS (0) CLS (0) CLS (0) 4 CLS (0) OPEN () 5 CLS (0) CLS (0) 6 OPEN () OPEN (). Fig R.: Measured waveforms of clock and - flip-flop output Clock - flip-flop output f = Hz f = Hz. When the reset button is held in closed position, what is the output of the - flip-flop? 4. From the measured waveforms in Fig R. i) When the flip-flop output starts to change state? The positive or negative edge of the clock? ii) What is the frequency of the flip-flop output? Exp. B.: Ripple binary counter Analysis and Evaluation. Table R.: Observation results of the ripple binary counter (Use binary 0 to represent LED OFF and binary to represent LED ON) Sequence No./ Clock Pulse No. MSB LSB 0 Decimal 0 (Push the reset button) (Release the reset button) Page 9 of 0
10 EEE06: Digital Logic Design, Lab Exp. DL result and mark sheets Student ID Name.. Major.. From the experimental results in Table R., draw the waveforms at 0, and in Fig R.. Fig R.: Waveforms of clock, 0, and of the ripple binary counter Pulse No Clock 0 Exp. B.: Synchronous Binary Counter Analysis and Evaluation. Table R.: Observation results of the synchronous binary counter Sequence No./ Clock Pulse No. MSB LSB 0 Decimal 0 (Push the reset button) (Release the reset button) From the results in Table R. and circuit diagram in Fig.5, draw the waveforms at 0,, Pin (7408) and in Fig R.. Fig R.: Waveforms of clock, 0,, Pin (7408) and of the synchronous binary counter Pulse No Clock 0 Pin (7408). From Fig R. and Fig.5, describe the function of the AND gate. 4. If a clock frequency f clk is applied to an n-bit binary counter, what is the frequency of the final stage flip-flop output ( n- )? Show your derivation. Fig R. or R. can help you in this derivation. Page 0 of 0
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