PAPER A New Dynamic D-Flip-Flop Aiming at Glitch and Charge Sharing Free

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1 496 IEICE TRANS. ELECTRON., VOL.E86 C, NO.3 MARCH 2003 PAPER A New Dynamic D-Flip-Flop Aiming at Glitch and Charge Sharing Free Sung-Hyun YANG a), Younggap YOU, Nonmembers, and Kyoung-Rok CHO, Regular Member SUMMARY A dual-modulus (divide-by-128/129) prescaler has been designed based on 0.25-µm CMOS technology employing new D-flip-flops. The new D-flip-flops are free from glitch problems due to internal charge sharing. Transistor merging technique has been employed to reduce the number of transistors and to secure reliable high-speed operation. At the 2.5-V supply voltage, the prescaler using the proposed dynamic D-flipflops can operate up to the frequency of 2.95-GHz, and consumes about 10% and about 27% less power than Yuan/Svensson s and Huang s circuits, respectively. key words: dynamic D-flip-flops, prescalers, low-power circuits, glitch free 1. Introduction Frequency synthesizers have been basic building blocks in modern communication systems. One of the key elements of the frequency synthesizer is a dual-modulus prescaler used in a fast phase-locked-loop (PLL). High performance prescalers and voltage controlledoscillators are frequently used in high-speed applications. Costly bipolar or GaAs technologies have been the basis of these high-speed parts, which are being replaced with rapidly improving low-cost CMOS technology. CMOS implementations become very attractive due to their characteristics of high frequency operation, low-power consumption yielding long battery life. Dynamic D-flip-flops for high-speed operation and low-power consumption are essential to high performance frequency synthesizers. Various flip-flops have been proposed to improve the operating speed of dualmodulus prescalers [1] [10]. The dynamic D-flip-flop designs in previous studies found suffer from glitch and charge-sharing problems [2], [3], which may result in incorrect operations. To alleviate these problems, additional transistors are introduced to some critical nodes to make these nodes stable [4] [6]. However, the newly added transistors limit operating speed and increase power consumption. In high-frequency operations, ratioed logic can replace ratioless logic without significant penalty on power consumption [8] [10]. Ratioed logic, however, consumes high power in low-frequency opera- Manuscript received December 28, Manuscript revised July 9, The authors are with the Department of Computer and Communication Engineering, Chungbuk National University, San 48, Gaesin-dong, Cheongju Chungbuk, Korea. a) shyang@hbt.chungbuk.ac.kr tion, and their operating frequency range is limited. In this paper, a new dynamic D-flip-flop without glitch problems resulting from charge sharing is proposed, which is a basic building block of a high-speed and low-power CMOS dual-modulus prescaler. The proposed dynamic flip-flop is to ensure edge-triggering operation independent of operating frequency. By reducing the charge sharing effect, more reliable operation can be achieved. This paper is organized as follows. In Sect. 2, serious problems of conventional dynamic flip-flops, such as glitch and charge sharing, are reviewed. Section 3 describes the structure and operation of the proposed D-flip-flops. Simulation and experimental results are summarized in Sect. 4. Finally, the conclusions are presented in Sect Conventional Dynamic D-Flip-Flops Dynamic or clocked logic gates are used to decrease circuit complexity, increase operating speed, and lower power dissipation [12]. Of various dynamic CMOS circuit techniques, a true single-phase-clock (TSPC) dynamic CMOS circuit is operated with one clock signal that is never inverted. Therefore, no clock skew exists except for the clock delay problems, and even higher clock frequency can be achieved [2], [11]. Figure 1 shows a TSPC D-flip-flop for high-speed operation introduced in [1], [4] [6]. The flip-flop consists of nine transistors, where the clocked switching transistors are placed closer to power/ground for higher speed [6]. The state transition of the flip-flop occurs at the rising edge of the clock signal, clk. Figure 2(a) shows the operation: Qb becomes high Fig. 1 A TSPC D-flip-flop for high-speed operation [1].

2 YANG et al.: A NEW DYNAMIC D-FLIP-FLOP AIMING AT GLITCH AND CHARGE SHARING FREE 497 (a) D =0,clk =0 1: Qb 1 Fig. 3 Simulation results of the D-flip-flop in Fig. 2. (b) D =1,clk =0 1: Qb 0 Fig. 2 Operation of a conventional dynamic D-flip-flop [1]. along clk changing low to high with D =0. InFig.2, the dotted lines are the conducting paths when clk = 0, and the solid lines when clk =1. IfD =0andclk = 0, MPS1, MP1, and MPS2 are turned on and n 1, y 1, and y 2 become high. If the signal clk changes low to high, the node y 2 is discharged to low through MN2 and MNS1, making MP2 be on and Qb high. Figure 2(b) shows the case with clk changes low to high and D = 1makingQb be low. The analysis is extended to other input combinations in the same manner. 2.1 Glitch and Charge Sharing Problems Edge-triggered flip-flops take incoming data at the edge of a clock signal. Glitch problems may occur making the flip-flops fall into wrong states. Consider the circuit in Fig. 2(a) with clk =0andD =0,wherey 1 and y 2 are precharged to high voltage. If clk changes low to high, the node y 2 is discharged to low after some delay. In other words, y 2 remains high for a short time, in which MN3 and MNS2 are turned on and Qb may change to low. By discharging of y 2, then, Qb returns to the correct state of high. A glitch may appear at Qb as indicated (a) in Fig. 3. Consider the circuit in Fig. 2 to discuss charge sharing effects. When clk is low, the node y 2 is always precharged high making MN3 on. The nodes, then, Qb and n 3 may share their charges. The high level of Qb is somewhat lowered by sharing charges with the low level of n 3 as indicated (b) in Fig. 3. Glitches induced by charge sharing among internal nodes are illustrated in Fig. 3. With clk low and D Fig. 4 Toggle configuration using D-flip-flop. high, both n 1 and y 2 are precharged to the VDD level and y 1 is discharged to ground. Then clk changes to high making MNS2 turn on and Qb low. Here, clk is assumed high for a while and D changes high to low instantly, then MN1 becomes off and MP1 turned on. Nodes n 1 and y 1 share their charges through MP1 making y 1 rise above the threshold voltage of MN2. With clk high and MNS1 on, the node y 2 discharges slowly, which leads MP2 to be turned on and Qb to rise to high. This is shown as (c) and (d) in Fig. 3. At the point (c), if clk changes to low right after D changes to low, there is no critical operation due to the small amount of discharge at y 2 and MP2 cannot be turned on. However, the edge-triggering operation of the flipflop is prevented in the case that the discharging time of y 2 is long as shown at (d) in Fig. 3. Charge sharing raises more serious problems when the D-flip-flop is used as a toggle-flip-flop operating in a lower frequency range. For toggle operations, Qb is tied to D as shown in Fig. 4. By changing clk low to high with Qb in a high state, Qb toggles to low. Since Qb and D are tied together, D is forced to change high to low right after clk changes low to high. The time that D stays low is almost half the period of clk. In a lower operating frequency, y 2 would have enough time to discharge making MP2 turn on strongly and Qb high. The flip-flop, therefore, loses its edge-triggering characteristics and fails to perform proper operations.

3 498 IEICE TRANS. ELECTRON., VOL.E86 C, NO.3 MARCH 2003 Fig. 6 A D-flip-flop design proposed by Huang [6]. (a) Simulation waves at clk = 2 GHz (b) Simulation waves at clk = 3 GHz Fig. 5 Simulation waveforms of toggle-flip-flop of Fig. 4. Fig. 7 Simulation waveforms of Huang s D-flip-flop. Figure 5 shows the simulation result of the toggleflip-flop. As shown in Fig. 5(a), when the frequency of 2-GHz is applied to clk, the toggle operation is not performed because of the long discharging time of the node y 2. In Fig. 5(b), however, the flip-flop shows the proper toggle operation under the sufficiently high frequency of 3-GHz because the discharging time of y 2 is small. As a result, in the low frequency the edge-triggering characteristic of the flip-flop gets worse and the reliability degrades. The toggle-flip-flop in Fig. 4 operates properly above 2.5-GHz when it is designed using 0.25-µm CMOS technology. Though the flip-flop violating the edge-triggering feature can be used as a component of a divide-by-4/5 synchronous counter in a high-frequency dual-modulus prescaler, it cannot be used as a flip-flop alone [7] [10]. The edge-triggering characteristics are very important for reliable operation. 2.2 Huang s D-Flip-Flop Huang proposed a D-flip-flop circuit shown in Fig. 6 aiming at the elimination of glitches as shown in Fig. 3 [4] [6]. To alleviate the charge sharing, the small size transistor MN5 prevents y 1 from rising when D changes high to low during clk high. MN5 and the inverter INV1 make a pull-down path of y 1 as follows. If D changes high to low during clk =1,n 1 and y 1 share their charges. That is, y 1 would rise up, but the output of INV1 still has a high value turning on MN5. This makes y 1 low and stable resolving the charge sharing problem. The same analogy applies Qb having MP3 and INV2. A transistor MN4 is introduced between MN3 andmns2toremoveglitches. Thatis,MN4driven by INV1 breaks the pull-down path of Qb. When D =0andclk =0,nodesy 1 and y 2 are precharged to high. If clk changes low to high, y 2 discharges to low. This operation cannot be completed instantaneously: MN4 prevents Qb from pulling down to ground. Figure 7 shows the simulation waveforms with the clock frequency of 100 MHz. Introduction of MN4 in Fig. 6 brings a new problem as the point (a) of Fig. 7. For clk =0andD = 0, y 1 and y 2 are precharged to high. If clk changes low to high, y 2 discharges to low and Qb becomes high. Though D changes low to high when clk =1,Qb remains high. At this time, y 1 =0andclk =1,n 3 and n 4 are low because both MN4 and MNS2 are turned on. If clk changes to low, y 2 is precharged to high. Then Qb shares charges with n 3 and n 4 through MN3 and MN4. This makes the voltage of Qb fall down. Even though MP3 can stabilize Qb, the time for returning to a correct logic value is somewhat long. 3. Proposed Dynamic D-Flip-Flop We now introduce a new dynamic D-flip-flop eliminat-

4 YANG et al.: A NEW DYNAMIC D-FLIP-FLOP AIMING AT GLITCH AND CHARGE SHARING FREE 499 ing glitches and reducing the number of transistors. It is based on a ratioed logic design technique and transistor merging. 3.1 Transistor Merging Transistor merging is to reduce the number of transistors and thereby save both power and silicon area while suppressing glitch occurrences. Pull-up and pull-down transistors are combined together yielding a circuit having fewer pull-up and pull-down transistors. Consider the circuit shown in Fig. 1, where the nodes n 1 and y 2 have the same potential of VDD during clk =0. When clk = 1, its operation is independent of the n 1 level and y 2 may stay high or discharge to low. This observation leads to merge two pull-up transistors of the conventional design. MPS1 and MPS2 in Fig. 1 are merged to MPS1 as shown in Fig. 8(a). With the same analysis, MNS1 in Fig. 8(a) replaces MNS1 and MNS2 in Fig Charge Sharing Problems In Fig. 8(a), with clk =0,y 2 is always high turning on MN3 and causing charge sharing between n 1 and Qb and resulting in an incorrect value at Qb. It is effective to introduce a transistor MNS2 driven by clk between MP2 and MN3 [2]. Figure 8(b) shows the proposed circuit, where MNS2 blocks charge sharing between Qb and n 2. The simulation result for the circuit of Fig. 8(b) is shown in Fig. 9. The 2-GHz sinusoidal wave is applied as the clock. An inverter is connected to the Qb node to generate the Q signal. Under 1.8-GHz, the toggle connection flip-flop in Fig. 8(b) ends up wrong operations due to long discharging time of y 2, and yields an unpredictable state of y 2. While the structure in Fig. 4 fails to operate at 2-GHz, the structure in Fig. 8(b) can operate at the frequency of 2-GHz. The reason is that y 2 in Fig. 8(b) starts discharging later than y 2 in Fig. 4 since inserting MNS2 makes Qb discharge slowly. Figure 10 shows the proposed D-flip-flop comprising nine transistors, which is free from glitches induced by charge sharing. The MPS2 transistor driven by clk as shown in Fig. 10 can effectively reduce charge sharing experienced in the circuit of Fig. 1. MPS2 disturbs charge distribution path between y 1 and y 2 preventing MN2 from turning on. This guarantees the correct edge-triggering operation of the flip-flop and enhances its reliability. Unfortunately, the critical path to pull up y 1 node is longer and thereby some speed degradation is expected. The operation of the proposed D-flip-flop shown in Fig. 10 is as follows. Consider the circuit of Fig. 11(a), where nodes y 1, n 1,andy 2 are precharged high with clk = 0andD = 0. During this phase, MNS1 and MP2 are off, and Qb holds the previous value. Note that both n 2 and n 3 are weak high because of y 1 and (a) Toggle-flip-flop using the transistor merging technique Fig. 9 Simulation results for the proposed circuit of Fig. 8(b). (b) Charge sharing protection between Qb and n 1 using MNS2 Fig. 8 The proposed toggle-flip-flop designed with transistor merging technique. Fig. 10 The proposed D-flip-flop for glitch elimination.

5 500 IEICE TRANS. ELECTRON., VOL.E86 C, NO.3 MARCH 2003 (a) D =0,clk =0 1: Qb 1 Fig. 12 Fig. 10. Simulation results of the proposed D-flip-flop in (b) D =1,clk =0 1: Qb 0 Fig. 11 Operations and signal paths of the proposed D-flip-flop. y 2 being high. Assuming that clk changes low to high, MPS1 and MPS2 are turned off and MNS1 and MNS2 are on. Since y 2 cannot discharge instantly, a pull-down path is formed consisting of MNS2, MN3, and MNS1. But n 2 and n 3 keep weak high from the previous phase resulting in a small glitch due to the voltage drop of Qb. Asy 2 becomeslowthroughmn2andmns1path, Qb rises high. Considering that clk =0andD =1asshownin Fig. 11(b), y 2 is precharged to high but y 1 is low. This makes MN2 be turned off. If clk changes low to high, Qb discharges low through the path consisting of MNS2, MN3, and MNS1. If we change D to low when clk = 1, MP1 is turned on, but the charge sharing between y 1 and y 2 never occurs due to the blocking transistor MPS2. This implies that MN2 remains off and the pulldown path of node y 2 does not exist. Though there exists the charge sharing effect between y 2 and n 1, it is different from (c) and (d) of Fig. 3. As shown in Fig. 12(b), after charge sharing y 2 has a stable final value, since clk = 1 and MN2 is off. On the other hand, the charge sharing in Fig. 3 turns on MN2, and y 2 continues to discharge. The voltage drop of y 2 resulting from charge sharing between n 1 and y 2 is determined by the ratio of the total capacitance of n 1 and y 2 as follows. We assume that y 2 and n 1 nodes are initially VDD and ground, respectively. This is the worst case condition. Then the initial charge of y 2 node, Q initial,is Q initial = C y2 VDD (1) The total charge after charge sharing, Q final,is Q final =(C y2 + C n1 ) V final (2) According to the charge conservation law, Q final = Q initial must be satisfied. (C y2 + V final )=C y2 VDD (3) Thus the final voltage of y 2, V final,is V final = C y 2 VDD VDD = (4) C y2 + C n1 1+C n1 /C y2 The parameters of the employed process are as follows: the junction capacitance C j at zero bias is 1 ff/µm 2, the junction capacitance of the sidewall C jsw,p (C jsw,n ) is (0.083) ff/µm, C jgate,p (C jgate,n ) is (0.82) ff/µm, and the gate-oxide capacitance is 6.64 ff/µm 2. From the layout, the parasitic capacitances for interconnection lines are extracted to the order of ff, which have a little effect on the calculation of the parasitic capacitance. With the source/drain area and their perimeters, C n1 is calculated to 8.4 ff and C y2 is calculated to 30.5 ff. Since (C n1 /C y2 ) = 3.63, V final is 1.96 V at VDD = 2.5 V, which is lower than the threshold voltage of a PMOS transistor of 0.6 V. If we lower the logic threshold voltage of the inverter consisting of MP2, MNS2, MN3, and MNS1, this effect can be further alleviated. Note that the final voltage of y 2 after charge sharing, V final,does not change any more, which is the difference from (c) and (d) of Fig. 3. Simulation results in Fig. 12 show successful operations of the proposed design. Nine transistors and one inverter (i.e., 11 transistors) are used to build the same logic operation of Qb and Q of Fig. 7 with reliable edge-triggering operations. Figure 13 shows the structure and the simulation result of Yuan/Svensson D-flip-flop [2], [11], which has no charge sharing problem but has glitch problems [6].

6 YANG et al.: A NEW DYNAMIC D-FLIP-FLOP AIMING AT GLITCH AND CHARGE SHARING FREE 501 (a) Yuan/Svensson s D-flip-flop (a) Yuan/Svensson s D-flip-flop Fig. 13 (b) Simulation result Yuan/Svensson s D-flip-flop and the simulation result. (b) Huang s D-flip-flop 4. Simulation and Experimental Results To evaluate the performance of the proposed D-flipflop, a divide-by-16 asynchronous counter and a dualmodulus divide-by-128/129 prescaler have been designed. Huang s general purpose D-flip-flops [6] of Fig. 6 and Yuan/ Svensson D-flip-flops [2], [11] of Fig. 13 are used to build an asynchronous counter and a prescaler for the performance comparison. The circuits have been resized in 0.25-µm technology. Figure 14 and Fig. 15 show the transistor sizing and the layout for the three D-flip-flops, respectively. The proposed flipflop occupies almost the same area as Yuan/Svensson s flip-flop and about 23% less area than Huang s flipflop. Yuan/Svensson flip-flop operates at the highest frequency among the three flip-flops. The proposed flipflop shows the lowest power consumption, the medium speed, and the medium power-delay product (PDP). The maximum operating frequency and the PDP of the proposed circuit is slightly degraded from stacking three PMOS transistors, MPS1, MP1, and MPS2 as shown in Fig. 10. The lowest power consumption is achieved by merging of the pull-up and pull-down transistors. The proposed flip-flop in Fig. 10 can be also obtained by connecting the sources of MP1 and MN3 to the nodes y 2 and n 2 in Fig. 13(a), respectively. Table 1 summarizes the comparison of the number of transistors and the layout area for three D-flip-flops. (c) The proposed D-flip-flop Fig. 14 Transistor sizing for (a) Yuan/Svensson s D-flip-flop, (b) Huang s D-flip-flop, and (c) the proposed D-flip-flop. For all transistors, the channel length L is 0.25-µm. 4.1 Asynchronous Counter Figure 16 shows the schematic diagram of a divide-by- 16 asynchronous counter. In each flip-flop, node Qb is fed back to the node D to get a toggle operation at the rising edge of the clock signal. The divide-by- 16 counter consists of four cascaded toggle flip-flops, in which clk drives the first flip-flop and its output Q drives the next flip-flop in turn. The output signal, the divide-by-16 signal of the main clock, is acquired at the node Q of the last flip-flop stage. The configuration provides with a practical load conditions for high speed operation: it employs the next stage flip-flops as its load instead of the artificial load capacitance. The maximum operating frequency and the power-

7 502 IEICE TRANS. ELECTRON., VOL.E86 C, NO.3 MARCH 2003 (a) Layout of Yuan/Svensson s D-flip-flop ( µm 2 ) Fig. 17 counters. Performance comparison of divide-by-16 asynchronous Table 2 Transistor dimensions of the proposed D-flip-flop related to the scale factor, S f. λ =2.25 µm S f, and the channel length is 0.25-µm for all transistors. (b) Layout of Huang s D-flip-flop ( µm 2 ) (c) Layout of the proposed D-flip-flop ( µm 2 ) Fig. 15 Layout of three dynamic D-flip-flops. Fig. 16 counter. Table 1 Comparison for three D-flip-flops. Schematic diagram of a divide-by-16 asynchronous delay product versus the supply voltage are evaluated through the SPICE simulation. Figure 17 summarizes the simulation results, where the power-delay products are measured at the maximum frequency of Huang s circuit for an apparent comparison. At the supply voltage of 2.5-V, the maximum operating frequencies of the proposed circuit, Huang s circuit, and Yuan/Svensson s circuit are 4.06-GHz, 3.07-GHz, and 4.85-GHz, respectively. The power-delay products of them at the maximum frequency of Huang s counter (i.e., at the frequency of 3.07-GHz) are pJ, pJ, and pj, respectively. The performance of the proposed circuits is better than that of Huang s circuits in the operating frequency and the power-delay product. At the frequency of higher than 3-GHz, Huang s flip-flop in Fig. 6 suffers from the speed degradation since the added inverter, INV1, fails to follow the input frequency. To find out the effect of the supply voltage and the device size on the divide-by-16 counter, simulations have been performed scanning the supply voltage and the device size. Table 2 shows the working transistor dimensions of the proposed D-flip-flop, where the scale factor S f is used to change the transistor width. For convenience, the parasitic capacitances of each transistor s source/drain are calculated with the transistor width and the source/drain length without sharing source/drain areas with the adjacent transistors. As shown in Fig. 18, the supply voltage has been considered from 1.0 to 3.5-V and S f from 0.2 to 2.0. The counter operates up to 4.06-GHz with S f of 1.0. As the supply voltage and S f are increased, the maximum operating frequency is gradually increased and finally saturated as shown in Fig. 18(a). The operating frequency saturation at high S f is due to the increase of the parasitic capacitances. The power consumption illustrated in Fig. 18(b) shows that the power consumption plane becomes steeper along the supply voltage and the scale factor increase. The optimum values of

8 YANG et al.: A NEW DYNAMIC D-FLIP-FLOP AIMING AT GLITCH AND CHARGE SHARING FREE 503 (a) Maximum operating frequency versus VDD and scale factor Fig. 20 Dual-modulus divide-by-128/129 prescaler. (b) Power consumption versus VDD and scale factor Fig. 18 Maximum operating frequency and power consumption features. Fig. 21 Performance comparison of divide-by-128 prescalers. factor is 1.0, the rising time of the clock must be faster than 0.9-ns. However, if we select the scale factor of 0.2, the rising time requirement becomes a slower value of 2.1-ns. Figure 19 can be used to estimate the driving capability of clock drivers for the proper operation of flip-flops. 4.2 Dual-Modulus Prescaler Fig. 19 Maximum allowable rising time of the clock according to the scale factors. the supply voltage and S f can be deduced from (a) and (b) of Fig. 18 with a specification on the maximum operating frequency and the power consumption. It is important to control the rise/fall rate at the clock edge in dynamic flip-flops [2], [6], [11]. The proposed flip-flop requires the clock rising time below about 1 ns for the correct operation. For the rising time slower than 1-ns, the precharge and the evaluation may occur in the middle of a rising edge leading the flip-flop to the wrong operation [6]. A smaller device size allows a slower edge rate of the clock signal. As shown in Fig. 19, the maximum allowable rising time is decreased as the device size increase. For example, when the scale The block diagram of the dual-modulus divide-by- 128/129 (64/65) prescaler is shown in Fig. 20. The dual-modulus prescaler has two counters: a divideby-4/5 synchronous counter and a divide-by-32 asynchronous counter. As the output signal of the divideby-4/5 counter, fso in Fig. 20, is connected to the clock input of the divide-by-32 counter, the prescaler can divide the main clock signal by 128 or 129. The divideby-4/5 counter is the only part operating at the maximum frequency determining the overall speed of the prescaler [5]. As several logic gates are inserted between the flip-flops to get a proper operation of the prescaler, the speed degradation is unavoidable due to the propagation delay. The select signal chooses the division ratio of the prescaler between 64/65 and 128/129. When the select is low, the last toggle flip-flop in the asynchronous counter is bypassed and the prescaler operates as a

9 504 IEICE TRANS. ELECTRON., VOL.E86 C, NO.3 MARCH 2003 Fig. 22 The chip photograph of the dual-modulus prescaler. The chip area including oscillator was measured to 85 µm 54µm. (a) Measured output waveform for the divide-by-128 prescaler erate at about 4-GHz with the supply voltage of 3.5 V. A dual-modulus divide-by-128/129 prescaler has been fabricated employing 0.25-µm CMOS technology. The chip photograph is shown in Fig. 22. The area of the chip including oscillator was 85-µm by 54-µm. Figure 23 shows the measured output from the fabricated chip at the supply voltage of 2.5-V. In Fig. 22(a), the measured output frequency of the prescaler was MHz (T =44.2 ns), and the input clock frequency is estimated to GHz. The result is very close to the simulation result. The output waveforms according to the division ratios are also shown in Fig. 23(b). 5. Conclusions A new dynamic D-flip-flop for high-speed operation and low-power consumption is presented aiming at glitch free operation. The flip-flop consists of only nine transistors based on the transistor merging technique, which is smaller than other alternatives. The fewer transistors in the flip-flop can achieve faster operation and lower power consumption. To evaluate the proposed flip-flop circuit, a dual-modulus divideby-128/129 prescaler has been designed and fabricated using 0.25-µm CMOS technology. At the 2.5-V supply voltage, the prescaler using the proposed dynamic D- flip-flops can operate up to the frequency of 2.95-GHz consuming mW, and shows half the power-delay product of Huang s circuits. Acknowledgement (b) Output waveform according to the division ratios Fig. 23 Measured waveforms of the prescaler. divide-by-64/65 counter. When the select is high, the prescaler operates as a divide-by-128/129 counter. When the mode signal is low (high), a divide-by-64 (65) or 128 (129) prescaler is obtained. The maximum operating frequency and the powerdelay product versus the supply voltage of the prescalers are also measured. As shown in Fig. 21, at 2.5-V supply voltage, the maximum operating frequencies in the proposed circuit, Huang s circuit, and Yuan/Svensson s circuit are 2.95-GHz, 2.77-GHz, and 3.12-GHz, showing the power-delay products of pj, pJ, and pJ, respectively. For comparison, the power-delay products are measured at the maximum frequency of Huang s circuit (i.e., at the frequency of 2.77-GHz). Each circuit operates at almost the same frequency, since the speed of prescaler is limited by the propagation delay of the logic gates. Note that the prescaler using the proposed flip-flops can op- The authors would like to thank Hynix Semiconductor and Integrated Circuit Design Education Center (IDEC) for the significant support to fabricate the test chip as well as the reviewers for their valuable comments. References [1] H. Oguey and E. Vittoz, CODYMOS frequency dividers achieve low power consumption and high frequency, Electron Lett., pp , Aug [2] J. Yuan and C. Svensson, High-speed CMOS circuit technique, IEEE J. Solid-State Circuits, vol.24, no.1, pp.62 70, Feb [3] R. Rogenmoser, N. Felber, Q. Huang, and W. Fichtner, 1.16 GHz dual-modulus 1.2-µm CMOS prescaler, Proc. IEEE 1993 CICC, pp , San Diego, CA, May [4] Q. Huang and R. Rogenmoser, A glitch-free single-phase DFF for gigahertz applications, Proc. IEEE 1994 ISCAS, vol.4, pp.11 13, London, May [5] R. Rogenmoser, Q. Huang, and F. Piaza, 1.57 GHz asynchronous and 1.4 GHz dual-modulus 1.2-µm CMOS prescaler, Proc. IEEE 1994 CICC, pp , San Diego, CA, May [6] Q. Huang and R. Rogenmoser, Speed optimization of edgetriggered CMOS circuits for gigahertz single-phase clocks, IEEE J. Solid-State Circuits, vol.31, pp , March 1996.

10 YANG et al.: A NEW DYNAMIC D-FLIP-FLOP AIMING AT GLITCH AND CHARGE SHARING FREE 505 [7] N. Foroudi and T.A. Kwasniewski, CMOS high-speed dual-modulus frequency divider for RF frequency synthesis, IEEE J. Solid-State Circuits, vol.30, pp , Feb [8] B. Chang, J. Park, and W. Kim, A 1.2 GHz CMOS dualmodulus prescaler using new dynamic D-type flip-flops, IEEE J. Solid-State Circuits, vol.31, pp , May [9] C.-Y. Yang, G-.-K. Dehng, J.-M. Hsu, and S.-I. Liu, New dynamic flip-flops for high-speed dual-modulus prescaler, IEEE J. Solid-State Circuits, vol.33, pp , Oct [10] K.-H. Sung and L.-S. Kim, Comments on new dynamic flip-flops for high-speed dual-modulus prescaler, IEEE J. Solid-State Circuits, vol.35, pp , June [11] M. Afghahi and C. Svensson, A unified single-phase clocking scheme for VLSI systems, IEEE J. Solid-State Circuits, vol.25, pp , Feb [12] R.J. Baker, H.W. Li, and D.E. Boyce, CMOS Circuit Design, Layout, and Simulation, Ch.14, IEEE Press, New York, Kyoung-Rok Cho received the B.S. degree in Electronic Engineering from Kyoungpook National University, Taegu, Korea in 1977, and M.S. and Ph.D. degrees in Electrical Engineering from the University of Tokyo, Tokyo, Japan, in 1989 and 1992, respectively. From 1979 to 1986, he was with TV research center of Gold Star Company in Korea. He is currently a Professor in Dept. of Computer and Communication Eng. of Chungbuk National University, Korea, since August His research interests are in the field of high-speed and low-power circuit design, and ASIC design for communication system. From 1999 to 2000, he was a visiting scholar at Oregon State University, OR. He is a member of Institute of Electrical and Electronics Engineer (IEEE), and Korea Institute Tele-communication Electronics (KITE). Sung-Hyun Yang received the B.S. and M.S. degrees in Computer and Communication Engineering from Chungbuk National University, Cheongju, Korea in 1999 and 2001, respectively. He is currently pursuing the Ph.D. degree in Computer and Communication Engineering at the Chungbuk National University, Korea. His research interests are highspeed and low-power circuit, CMOS active pixel image sensor, analog-to-digital conversion, and continuous-time filter designs. Younggap You received the B.S. degree in Electronic Engineering from the Sogang Jesuit University, Seoul, Korea and the M.S. and Ph.D. degrees in Electrical Engineering from the University of Michigan, Ann Arbor, U.S.A., in 1981 and 1986, respectively. From 1975to 1979, he was with the Agency for Defense Development, Korea, where he was involved in high speed digital design. He worked as a principal engineer at LG Semiconductor, inc., Seoul, Korea, form 1986 to He is currently a Professor in Dept. of Computer and Communication Engineering at Chungbuk National University, Cheongju, Korea. His research interests are fault tolerant computing, computer architecture, cryptography, cellular system design, and frequency synthesis technology.