Verilog Lecture 1-1. Verilog Lecture 1. Introduction to Verilog. Logic Design. Youpyo Hong, Dongguk University

Transcription

1 Verilog Lecture 1-1 Verilog Lecture 1 Introduction to Verilog

2 Verilog Lecture 1-2 Hardware Description Languages Introduction We would like to design our circus at a relatively high level, to be more productive. Like many software projects, we start with an imprecise description of what we want to build, and need to work on it to make it more precise. In old days, many people start the process by writing a C model first, just to get a better idea of the functionality of the part. Languages have been created to help describe hardware. We will look at an HDL called Verilog, and describe some of its uses.

3 Verilog Lecture 1-3 Hardware Description Languages (HDLs) There are many different systems for modeling and simulating hardware. Verilog (Cadence) VHDL (many) L-language, M-language (Mentor) CSIM / THOR (U of Colo / Stanford) DECSIM (DEC) Aida (IBM / HaL) and many others The two most standard languages are Verilog and VHDL. For this class we will be using Verilog.

4 Verilog Lecture 1-4 Verilog (or any HDL) View of the World A design consists of a set of modules plus their connections. A b c B a bus d C

5 Verilog Lecture 1-5 An Example: A 4-Bit Register module example(a, b, c, f, e); a b d f input a, b, c; output f, e; wire d; c e and g1(d, a, b); not g2(e, c); or g3(f, d, e); endmodule

6 Verilog Lecture 1-6 Before We Start In Verilog, there are some keywords that we must momorize and use them as promised. Verilog provides some basic logic gates like nand, not, etc. They are a kind of keywords too. Verilog is a quite natural language. We can insert empty space or lines as we feel convenient. We will learn how to specify the circuits in this lecture and learn how to simulate in the next class. There are many Verilog simulators in addition to Cadence. We will be using the SynptiCAD VeriLogger tool.

7 Verilog Lecture 1-7 Module Description Format Module header module Module identifier module example Port connection list module example (a, b, c, f, e) a b c d f e a b c example e f Period to complete a statement. module example (a, b, c, e, f) ;

8 Verilog Lecture 1-8 Port Declarations module example (a, b, c, e, f); input a, b, c; output e, f; a b c d f e a b c example e f Now we must describe the internal structure of the flip-flop. We must label all the nodes.

9 Verilog Lecture 1-9 Component and Node Labeling a b g1 d g3 f c g2 e

10 Verilog Lecture 1-10 Internal Structure Declarations module example (a, b, c, e, f); input a, b, c; output e, f; and g1 (d, a, b); a b g1 d g3 f c g2 e

11 Verilog Lecture 1-11 Internal Structure Declarations module example (a, b, c, e, f); input a, b, c; output e, f; and g1 (d, a, b); not g2 (e, c); or g3 (f, d, e); a b g1 d g3 f c g2 e endmodule

12 Verilog Lecture 1-12 Another Example: A 4-Bit Register clear clock d 3 d 2 d 1 d 0 q 3 q 2 q 1 q 0 clock clear 0 1 d 3 d 2 d 1 d0 q 3 q 2 q 1 q d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 otherwise last q

13 Verilog Lecture 1-13 The Structure of a 4-Bit Register q 3 q 2 q1 q 0 d q d q d q d q clk clk clk clk clr clr clr clr d 3 d 2 d 1 d 0

14 Verilog Lecture 1-14 D-Type Flip-Flop with Clear clear clock data q qb clock clear data q qb otherwise last q last qb

15 Verilog Lecture 1-15 D-Type Flip-Flop with Clear clear q clock data qb

16 Verilog Lecture 1-16 The Flip-Flop Model Module header module Module identifier module flop Port connection list module flop (data, clock, clear, q, qb) clear clock data flop q qb Period to complete a statement. module flop (data, clock, clear, q, qb) ;

17 Verilog Lecture 1-17 Port Declarations module flop (data, clock, clear, q, qb); input data, clock, clear; output q, qb; clear clock data flop q qb

18 Verilog Lecture 1-18 So Far clear q clock data qb Now we must describe the internal structure of the flip-flop. We must label all the nodes.

19 Verilog Lecture 1-19 Component and Node Labeling clear nd1 a nd3 c nd5 e nd7 q clock data iv1 nd2 ndata b nd4 d nd6 f nd8 qb iv2

20 Verilog Lecture 1-20 Internal Structure Declarations module flop (data, clock, clear, q, qb); input data, clock, clear; output q, qb; nand nd1 (a, data, clock, clear); clear nd1 a q clock data qb

21 Verilog Lecture 1-21 Internal Structure Declarations... nand nd1 (a, data, clock, clear); nand nd2 (b, ndata, clock); clear nd1 a q clock data ndata nd2 b qb

22 Verilog Lecture 1-22 Repeatitive Component If the gate types are the same for more than one component, we can skip repeating the component name and ; as follows.... nand nd1 (a, data, clock, clear), nd2 (b, ndata, clock),...

23 Verilog Lecture 1-23 Flip-Flop Declaration Completed module flop (data, clock, clear, q, qb); input data, clock, clear; output q, qb; nand nd1 (a, data, clock, clear), nd2 (b, ndata, clock), nd3 (c, a, d), nd4 (d, c, b, clear), nd5 (e, c, nclock), nd6 (f, d, nclock), nd7 (q, e, qb), nd8 (qb, q, f, clear); not iv1 (ndata, data), iv2 (nclock, clock); endmodule

24 Verilog Lecture 1-24 Hierarchical Design The previous flip-flop is designed using flat style. However, we need to call modules (or subcircuits as in Spice) to describe larger design. nand nand flop flop flop flop 4-bit register

25 Verilog Lecture Bit Register Model module my_reg (d3, d2, d1, d0, clk, clrb, q3, q2, q1, q0); input clk, clrb; input d3, d2, d1, d0; output q3, q2, q1, q0; q 3 q 2 q 1 q 0 flop flop flop flop clrb clk d 3 d 2 d 1 d 0

26 Verilog Lecture 1-26 Compact Representation Using Bus module my_reg (d, clk, clrb, q); input clk, clrb; input [3:0] d; output [3:0] q; q[3] q[2] q[1] q[0] flop flop flop flop clrb clk d[3] d[2] d[1] d[0]

27 Verilog Lecture 1-27 Port Matching Recall that module flop (data, clock, clear, q, qb) q[3] q[2] q[1] q[0] data q clock qb clear clrb clk d[3] d[2] d[1] d[0] When we call a module, the port order must match. For example, the first instantiation of flop must follow (d[3], clk, clrb, q[3], ) order. Any unused port must be specified empty.

28 Verilog Lecture 1-28 So module my_reg (d, clk, clrb, q); input clk, clrb; input [3:0] d; output [3:0] q; flop f1 (d[0], clk, clrb, q[0],), f2 (d[1], clk, clrb, q[1],), f3 (d[2], clk, clrb, q[2],), f4 (d[3], clk, clrb, q[3],); endmodule

29 Verilog Lecture 1-29 Simulation of Verilog Simulation method depends on which simulator you use. Altera MaxPlusII : You typically use waveform editor to draw input waveform. Cadence, SynaptiCAD : You use another module as a testbench. There can be other methods but they must be similar to one of the two approaches above.