VLSI Design I; A. Milenkovic 1
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1 Review: Pass Transistor Circuits CPE/EE 427, CPE 527 VLI esign I 0: equential Circuits epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( Use pass transistors like switches to do logic Inputs drive diffusion terminals as well as gates CMO Transmission Gates: 2-input multiplexer Gates should be restoring 11/1/2005 VLI esign I;. Milenkovic 2 TG Multiplexer Transmission Gate OR V In 2 In 1 =!(In 1 In 2 GN In 1 In 2 11/1/2005 VLI esign I;. Milenkovic 3 11/1/2005 VLI esign I;. Milenkovic 4 Transmission Gate OR TG ull dder weak 0 if! off on off on!! um 0 1 weak 1 if an inverter C out 11/1/2005 VLI esign I;. Milenkovic 5 11/1/2005 VLI esign I;. Milenkovic 6 VLI esign I;. Milenkovic 1
2 ifferential TG (PL CPL GN GN V V N/NN = = OR/NOR = = Complementary Pass-transistor ual-rail form of pass transistor logic voids need for ratioed feedback Optional cross-coupling for rail-to-rail swing L L 11/1/2005 VLI esign I;. Milenkovic 7 11/1/2005 VLI esign I;. Milenkovic 8 ifferential PT (CPL CPL Properties N/NN = = PT Network Inverse PT Network OR/NOR = = = = OR/NOR ifferential so complementary data inputs and outputs are always available (so don t need extra inverters till static, since the output defining nodes are always tied to V or GN through a low resistance path esign is modular; all gates use the same topology, only the inputs are permuted. imple OR makes it attractive for structures like adders ast (assuming number of transistors in series is small dditional routing overhead for complementary signals till have static power dissipation problems 11/1/2005 VLI esign I;. Milenkovic 9 11/1/2005 VLI esign I;. Milenkovic 10 CPL ull dder CPL ull dder!um!um um um!c out!c out C out C out 11/1/2005 VLI esign I;. Milenkovic 11 11/1/2005 VLI esign I;. Milenkovic 12 VLI esign I;. Milenkovic 2
3 tate Registers equencing equential Circuits logic output depends on current inputs equential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: M, pipeline in out inite tate Machine Pipeline 11/1/2005 VLI esign I;. Milenkovic 14 equencing Cont. If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiber-optic cable Light pulses (tokens are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses ut dispersion sets min time between pulses This is called wave pipelining in circuits In most circuits, dispersion is high elay fast tokens so they don t catch slow ones. 11/1/2005 VLI esign I;. Milenkovic 15 equencing Overhead Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay Called ome people call this clocking overhead ut it applies to asynchronous circuits too Inevitable side effect of maintaining sequence 11/1/2005 VLI esign I;. Milenkovic 16 equential Timing Metrics In Out Inputs Outputs clock t su clock time Current tate Next tate In data stable t c-q time clock Out output stable output stable time 11/1/2005 VLI esign I;. Milenkovic 17 11/1/2005 VLI esign I;. Milenkovic 18 VLI esign I;. Milenkovic 3
4 tate Registers ystem Timing Constraints equencing Elements Inputs Current tate clock Outputs Next tate T (clock period : Level sensitive a.k.a. transparent latch, latch lip-flop: edge triggered.k.a. master-slave flip-flop, flip-flop, register Timing iagrams Transparent Opaque Edge-trigger reg logic T t c-q t plogic t su (latch (flop 11/1/2005 VLI esign I;. Milenkovic 19 11/1/2005 VLI esign I;. Milenkovic 20 equencing Elements esign : Level sensitive a.k.a. transparent latch, latch lip-flop: edge triggered.k.a. master-slave flip-flop, flip-flop, register Timing iagrams Transparent Opaque Edge-trigger (latch (flop Pass Transistor Pros Cons 11/1/2005 VLI esign I;. Milenkovic 21 11/1/2005 VLI esign I;. Milenkovic 22 esign esign Pass Transistor Pros Tiny Low clock load Cons V t drop nonrestoring backdriving output noise sensitivity dynamic diffusion input Used in 1970 s Transmission gate - 11/1/2005 VLI esign I;. Milenkovic 23 11/1/2005 VLI esign I;. Milenkovic 24 VLI esign I;. Milenkovic 4
5 esign esign Transmission gate No V t drop - Requires inverted clock Inverting buffer ixes either 11/1/2005 VLI esign I;. Milenkovic 25 11/1/2005 VLI esign I;. Milenkovic 26 esign esign Inverting buffer Restoring No backdriving ixes either Output noise sensitivity Or diffusion input Inverted output Tristate feedback 11/1/2005 VLI esign I;. Milenkovic 27 11/1/2005 VLI esign I;. Milenkovic 28 esign esign Tristate feedback tatic ackdriving risk tatic latches are now essential uffered input 11/1/2005 VLI esign I;. Milenkovic 29 11/1/2005 VLI esign I;. Milenkovic 30 VLI esign I;. Milenkovic 5
6 esign esign uffered input ixes diffusion input Noninverting uffered output 11/1/2005 VLI esign I;. Milenkovic 31 11/1/2005 VLI esign I;. Milenkovic 32 esign esign uffered output No backdriving Widely used in standard cells Very robust (most important - Rather large - Rather slow (1.5 2 O4 delays - High clock loading atapath latch - 11/1/2005 VLI esign I;. Milenkovic 33 11/1/2005 VLI esign I;. Milenkovic 34 esign lip- esign atapath latch maller, faster - unbuffered input lip-flop is built as pair of back-to-back latches 11/1/2005 VLI esign I;. Milenkovic 35 11/1/2005 VLI esign I;. Milenkovic 36 VLI esign I;. Milenkovic 6
7 Enable Enable: ignore clock when en = 0 Mux: increase latch - delay Clock Gating: increase en setup time, skew Reset orce output low when asserted ynchronous vs. asynchronous ymbol ymbol Multiplexer esign Clock Gating esign en en 1 0 en 1 0 en en en ynchronous Reset synchronous Reset 11/1/2005 VLI esign I;. Milenkovic 37 11/1/2005 VLI esign I;. Milenkovic 38 et / Reset equencing Methods et forces output high when enabled lip-flop with asynchronous set and lip-flops 2-Phase es Pulsed es lip-s set set 2-Phase Transparent es Pulsed es 1 2 p t pw p /2 t nonoverlap Half-Cycle 1 Half-Cycle 1 t nonoverlap p 11/1/2005 VLI esign I;. Milenkovic 39 11/1/2005 VLI esign I;. Milenkovic 40 Timing iagrams Max-elay: lip-s Contamination and Propagation elays tpd Tc ( Prop. elay Cont. elay / Clk- Prop elay thold q / Clk- Cont. elay - Prop elay - Cont. elay / etup Time / Hold Time q q /1/2005 VLI esign I;. Milenkovic 41 11/1/2005 VLI esign I;. Milenkovic 42 VLI esign I;. Milenkovic 7
8 Max-elay: lip-s Max elay: 2-Phase es ( setup tpd Tc t tpcq t = t t Tc ( pd pd pd L q q /1/2005 VLI esign I;. Milenkovic 43 11/1/2005 VLI esign I;. Milenkovic 44 Max elay: 2-Phase es Max elay: Pulsed es ( 2 t = t t Tc tpdq pd pd pd L3 3 tpd Tc max 144 ( p 1 1 p q 2 (a t pw > q1 p t pw tpd tsetup 2 q2 (b t pw < /1/2005 VLI esign I;. Milenkovic 45 11/1/2005 VLI esign I;. Milenkovic 46 Max elay: Pulsed es Min-elay: lip-s ( setup tpd Tc max tpdq, tpcq t tpw p 1 1 p t cd 1 1 q (a t pw > p 1 t pw tpd tsetup 1 (b t pw < /1/2005 VLI esign I;. Milenkovic 47 11/1/2005 VLI esign I;. Milenkovic 48 VLI esign I;. Milenkovic 8
9 Min-elay: lip-s Min-elay: 2-Phase es 1 t t t cd hold ccq 1 t t cd1, cd Hold time reduced by nonoverlap Paradox: hold applies twice each cycle, vs. only once for flops. ut a flop is made of two latches! 1 2 t nonoverlap /1/2005 VLI esign I;. Milenkovic 49 11/1/2005 VLI esign I;. Milenkovic 50 Min-elay: 2-Phase es Min-elay: Pulsed es t t t t t cd cd ccq 1, 2 hold nonoverlap 1 1 p tcd 1 Hold time reduced by nonoverlap 2 2 Hold time increased by pulse width 2 p Paradox: hold applies twice each cycle, vs. only once for flops. ut a flop is made of two latches! 1 2 t nonoverlap 1 2 p tpw /1/2005 VLI esign I;. Milenkovic 51 11/1/2005 VLI esign I;. Milenkovic 52 Min-elay: Pulsed es Time orrowing t t t t cd hold ccq pw Hold time increased by pulse width 2 p 1 2 p 1 p tpw In a flop-based system: ata launches on one rising edge Mus before next rising edge If it arrives late, system fails If it arrives early, time is wasted s have hard edges In a latch-based system ata can pass through latch while transparent Long cycle of logic can borrow time into next s long as each loop completes in one cycle 11/1/2005 VLI esign I;. Milenkovic 53 11/1/2005 VLI esign I;. Milenkovic 54 VLI esign I;. Milenkovic 9
10 t skew Time orrowing Example How Much orrowing? Phase es t T c ( tsetup t borrow nonoverlap (a Pulsed es 1 2 t nonoverlap orrowing time across half-cycle boundary orrowing time across pipeline stage boundary t t t borrow pw setup /2 Nominal Half-Cycle 1 elay 2 t borrow 1 2 (b Loops may borrow time internally but must complete within the cycle 11/1/2005 VLI esign I;. Milenkovic 55 11/1/2005 VLI esign I;. Milenkovic 56 Clock kew kew: lip-s We have assumed zero clock skew Clocks really have uncertainty in arrival time ecreases maximum propagation delay Increases minimum contamination delay ecreases time borrowing cd hold ( setup skew tpd Tc tpcq t t t t t t ccq skew q 2 2 t skew /1/2005 VLI esign I;. Milenkovic 57 11/1/2005 VLI esign I;. Milenkovic 58 kew: es Two-Phase Clocking 2-Phase es t Tc ( 2t pd pdq 123 t, t t t t t cd cd ccq 1 2 hold nonoverlap skew t Tc ( tsetup 2 t tskew borrow nonoverlap Pulsed es t Tc max ( tpdq, tpcq tsetup tpw tskew pd t t t t t cd hold pw ccq ( t t t t skew borrow pw setup skew L3 3 If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speed In this class, working chips are most important No tools to analyze clock skew n easy way to guarantee hold times is to use 2- phase latches with big nonoverlap times Call these clocks 1, 2 (ph1, ph2 11/1/2005 VLI esign I;. Milenkovic 59 11/1/2005 VLI esign I;. Milenkovic 60 VLI esign I;. Milenkovic 10
11 afe lip- In class, use flip-flop with nonoverlapping clocks Very slow nonoverlap adds to setup time ut no hold times In industry, use a better timing analyzer dd buffers to slow signals if hold time is at risk 2 1 ummary lip-s: Very easy to use, supported by all tools 2-Phase Transparent es: Lots of skew tolerance and time borrowing Pulsed es: ast, some skew tol & borrow, hold time risk /1/2005 VLI esign I;. Milenkovic 61 11/1/2005 VLI esign I;. Milenkovic 62 VLI esign I;. Milenkovic 11
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