EECE 481. Static MOS Gate and Flip-Flop Circuits Lecture 8

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1 EECE 48 Sttic MOS Gte nd Flip-Flop Circuits Lecture 8 Rez Molvi Dept. of ECE University of British Columi rez@ece.uc.c Slides Courtesy : Dr. Res Sleh (UBC), Dr. D. Sengupt (AMD), Dr. B. Rzvi (UCLA) EECE 48 Lecture 8

2 Comintionl MOS Logic Now tht we understnd the logic strction nd the properties of vlid logic gtes, we cn consider the issues of design sic uilding locks of digitl systems Typicl comintionl gte is multiple input single output system Performs Boolen opertions on multiple input vriles, drives one or more gtes Design prmeters nd considertions: Propgtion dely Sttic nd dynmic power Are Noise mrgins (VTC) Fnins = no. of inputs V V 2 V 3 Comintionl Logic Circuit Fnouts = no. of gtes driven V out = f (V, V 2, V 3,... V n ) V n 2

3 Pull-up nd Pull-down Networks V DD Bsic Structure Of ll CMOS logic gtes A B C : A B C : p-complex F n-complex PMOS pull-up nd NMOS pull-down networks re duls of ech other Configurtion of pull-up nd pull-down networks crete current connection from the output to either Vdd or Gnd, sed on the inputs PMOS devices hve lower drive cpility nd thus require wider devices to chieve the sme on-resistnce s its pull-down counterprt 3

4 Sttic CMOS Logic Gtes A B F A F B These re the most common type of sttic gtes Cn implement ny Boolen expression with these two gtes Why is sttic CMOS so populr? It s very roust! it will eventully produce the right nswer Power, shrinking V DD, more circuit noise, process vritions, etc. limit use of other design styles 4

5 More Properties of Sttic CMOS Logic Fully complementry Low sttic power dissiption! Outputs swing full ril Vdd (V OH ) to Gnd (V OL ) Works fine t low Vdd voltges But lower Vdd = less current = slower speed Comintionl opertion Feed it some inputs, wit some dely, result comes out No clocks required for norml opertion Modertely good performnce Drive strength is proportionl to trnsistor size Lrge lods require lrge W Dul logic networks for N- nd P-Chnnel devices 5

6 Bet Rtio for Sttic Gtes The rtio etween the NMOS nd PMOS device is clled the et rtio We need to size CMOS sttic gtes to deliver trget speed. But how? Strt y sizing the inverter to deliver the trget speed, then mp size to gte Suppose: R eqp (PMOS) 2.5 R eqn (NMOS) under identicl conditions (ctully R eqp =3kW nd R eqn =2.5kW) Then rtio etween PMOS:NMOS should e 2.5: Bet rtio sets: Switching point of the gte output drive Input cpcitnce L-to-H vs. H-to-L trnsition times Usully find 2: rtio in CMOS inverter 2W Is 2: the right rtio? For equl rise nd fll times. 2.5: W How out for minimum dely?.7: 6

7 NAND nd NOR Sizing First Design Inverter Then Mp Results to Gtes 2W 2W 2W 4W 4W W C L 2W 2W C L W W C L () Inverter () NAND (c) NOR Drive strength determined y device widths - W (ssume L is minimum size) For the moment, consider only C L (we re ignoring the device self-cpcitnce) Pick the right sizes for the sic inverter nd then ssign vlues to gtes Wht does tht men for prllel nd series comintions? For prllel trnsistors, direct mpping from inverter For series trnsistors, need to compute equivlent sizes 7

8 Equivlent Sizes Consider three-input NAND gte (NMOS portion only): Actul Lyout Equivlent Device A 3W F L 3W F B L 3L C L poly diffusion poly 8

9 VTC nd Noise Mrgins V OUT V OUT Both inputs tied inverter One input only One input only inverter Both inputs tied NOR gte A B V I N F NAND gte A F V I N B 9

10 Complex Logic Circuits The ility to esily uild complex logic gtes is one of the most ttrctive fetures of MOS logic circuits Design principle of the pull-down network: OR opertions re performed y prllel connected drivers AND opertions re performed y series connected drivers Inversion is provided y the nture of MOS circuit opertion Don t get too crried wy Use this knowledge wisely Rememer tht complex functions don t hve to e implemented with single gte Cn rek up very complicted Boolen expressions into cscde of gte stges Limit series stcks to 3~4 We will use De Morgn s Lw to uild the dul networks

11 Review of DeMorgn s Lw = = De Morgn s theorem: The complement of ny logic function is found y complementing ll input vriles nd replcing ll AND opertions with OR nd ll OR opertions with AND Use De Morgn s lw to find the complement of function for the pulldown network (if needed) Use Dulity to find the pull-up network

12 Complex CMOS Gte Design Exmple Implement n AND-OR-INVERT (AOI) function Z = (A B + C) Get the expression into forms tht enle esy implementtion of pullup nd pull-down networks Z = (A B +C) Z = (A + B) C pull-up A B A B A B Z = A B + C C C pull-down Z = (A + B) C A B C Z C Complement of Z Dul of Complement of Z Comine Results 2

13 XOR nd XNOR Gtes V DD V DD f = + f = + f f 3

14 CMOS Multiplexer V DD s f s s s s f = s+s 4

15 The Bd News Slows down drmticlly for lrge fnins due to long series stck of trnsistors fnin = numer of inputs PMOS series stcks worse thn nmos series stcks Lrge numer of trnsistors 2n devices for n-input NAND At lest 2 devices per input Bigger lyout n+ to p+ spcing rule nd well spcing rule Lrge device sizes required to counterct series stck Limit the fnin to 3 or 4 or dely nd re will e too lrge 5

16 Eight-Input AND gte 2W 8W 8W 8W 8W This is not cceptle 8W 8W 8W 8W 6

17 Multi-level Logic Implementtions NAND2-INV-NAND2-INV NAND2-NOR2-NAND2-INV There re mny more options to try Which is the est? We need quick wy of nswering this question 7

18 Pseudo-NMOS Logic NOR gte W Lod A B Z = A+B Z A W A B W B A B Z Design issues: Sizing Rtio Rtio pull-up to pull-down (V OL & V OH ) Propgtion dely Suthreshold current cn degrde V OH slightly V OL decreses s more devices turning on 8

19 Pseudo-nMOS Logic NAND Gte A B Z = A B A B W A W B Z A B Z Issues Sizing Rtio Need to mke pull-down devices wider Prsitic cp goes up with igger devices Lower devices in stck slower compred to upper ones ecuse they see more cpcitnce 9

20 AND8 Option - Use Pseudo-NMOS W p W n 2

21 Properties of Sttic Pseudo-NMOS Gtes DC power lwys conducting current when output is low V OL nd V OH depend on sizing rtio nd input sttes Poor low-to-high trnsition Lrge fnin NAND gtes tend to get ig due to rtioing As trnsistor count increses, power consumption is too high Cnnot use this pproch for ll gtes on the chip But wht re its dvntges? Good for wide NOR structures Memory decoder Smller numer of trnsistors (re) / logic function 2

22 Flip-Flops nd Ltches Flip-flops nd ltches re importnt logic elements used for storge We typiclly uild finite stte mchines from comintionl logic (next stte logic) nd ltches or flip-flops (storge elements) to store the stte informtion. D Clk Logic D Clk N We then control ltches nd flip-flops with clock to crete synchronous logic circuits. The clock ensures tht we cn tell the difference etween previous, current nd future sttes of the logic circuit Clock prev this next 22

23 Ltch vs. Flip-flop Ltch (level-sensitive, trnsprent) When the clock is high it psses In vlue to Out When the clock is low, it holds vlue tht In hd when the clock fell Flip-Flop (edge-triggered, non trnsprent) On the rising edge of clock (pos-edge trig), it trnsfers the vlue of In to Out It holds the vlue t ll other times. In Clk Out In Out CLK In Clk In Out Out CLK Ltch Flip-Flop 23

24 FF Clocking Overhed FF hve setup nd hold times tht must e stisfied: Flip Flop D in will work my work won t work Clk T hold out T setup + T clk-q If Din rrives efore setup time nd is stle fter the hold time, FF will work; if Din rrives fter hold time, it will fil; in etween, it my or my not work; FF delys the slowest signl y the setup + clk-q dely in the worst cse 24

25 Ltch Clocking Overhed Ltches lso hve setup nd hold times tht must e stisfied: Ltch D in Clk out T setup T hold T d-q But ltch hs smll setup nd hold times; however, it delys the lte rriving signls y T d-q nd this is more importnt thn the setup nd hold times. 25

26 SR Ltch with NOR Gtes Simplest FF is cross-coupled pir of NOR gtes When S=, = When R=, = By setting oth S= nd R=, the previous stte is held Illegl stte occurs when R= nd S= (ctully, the finl stte is determined y which signl goes low lst) S R S R S R 26

27 27 SR Ltch with NAND Gtes Similr to NOR ltch except tht the signls re ctive low Illegl stte is now S= nd R= Hold stte is S= nd R= S R S R S R

28 JK Flip-flop J CK K To void illegl stte, use JK flip-flop In NAND implementtion, J=K= flips the stte of the output Clock is used to enle the output Will oscillte if clock is high too long when J=K= S R NAND Ltch J CK K J n K n n+ n n 28

29 Mster-Slve JK Flip-flop Cscde of two JK Flip-flops Mster ctivted y CK, Slve ctivted y CK Mster ltches new dt, slve lunches old dt J S S CK NAND Ltch NAND Ltch K R R 29

30 Clocked D Flip-flop Very useful FF Widely used in IC design for temporry storge of dt My e edge-triggered (Flip-flop) or level-sensitive (trnsprent D- ltch) D n+ D D-FF CK D CK Cn implement As AOI function 3

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