Lecture 10: Sequential Circuits

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1 Introduction ti to CMOS VLSI esign Lecture 10: Sequential Circuits avid Harris Harvey Mudd College Spring 2004

2 Outline Sequencing Sequencing Element esign Max and Min-elay Clock Skew Time Borrowing Two-Phase Clocking Slide 2

3 Sequencing Combinational logic output depends on current inputs Sequential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline in CL out CL CL Finite State Machine Pipeline Slide 3

4 Sequencing Cont. If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiber-optic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses This is called wave pipelining pp in circuits In most circuits, dispersion is high elay fast tokens so they don t catch slow ones. Slide 4

5 Sequencing Overhead Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit it slower than just the logic delay Called sequencing overhead Some people call this clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence Slide 5

6 Sequencing Elements Latch: Level sensitive a.k.a. transparent latch, latch Flip-flop: edge triggered A.k.a. master-slave flip-flop, flip-flop, register Timing iagrams Transparent Opaque Edge-trigger (latch) La atch Flop (flop) Slide 6

7 Sequencing Elements Latch: Level sensitive a.k.a. transparent latch, latch Flip-flop: edge triggered A.k.a. master-slave flip-flop, flip-flop, register Timing iagrams Transparent Opaque Edge-trigger (latch) La atch Flop (flop) Slide 7

8 Latch esign Pass Transistor Latch Pros + + Cons Slide 8

9 Latch esign Pass Transistor Latch Pros +Tiny + Low clock load Cons V t drop Used in 1970 s nonrestoring backdriving output noise sensitivity dynamic diffusion input Slide 9

10 Latch esign Transmission gate + - Slide 10

11 Latch esign Transmission gate +No V t drop - Requires inverted clock Slide 11

12 Latch esign Inverting buffer Fixes either X Slide 12

13 Latch esign Inverting buffer + Restoring + No backdriving + Fixes either X Output noise sensitivity Or diffusion input Inverted output Slide 13

14 Latch esign Tristate feedback + X Slide 14

15 Latch esign Tristate feedback + Static Backdriving risk X Static latches are now essential Slide 15

16 Latch esign Buffered input + + X Slide 16

17 Latch esign Buffered input + Fixes diffusion input + Noninverting X Slide 17

18 Latch esign Buffered output + X Slide 18

19 Latch esign Buffered output + No backdriving X Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1.5 2 FO4 delays) - High clock loading Slide 19

20 Latch esign atapath latch + - X Slide 20

21 Latch esign atapath latch + Smaller, faster - unbuffered input X Slide 21

22 Flip-Flop Flop esign Flip-flop is built as pair of back-to-back latches X X Slide 22

23 Enable Enable: ignore clock when en = 0 Mux: increase latch - delay Clock Gating: increase en setup time, skew Symbol Multiplexer esign Clock Gating esign en Latch 1 0 Latch Latch en en en Flop 1 0 en Flop Flop en Slide 23

24 l Reset Force output low when reset asserted Synchronous vs. asynchronous Symbol Latch Flop reset reset Synchronous Reset reset reset Asynchronous Reset reset reset reset reset Slide 24

25 Set / Reset Set forces output high when enabled Flip-flop with asynchronous set and reset reset set reset set Slide 25

26 Sequencing Methods Flip-flops T c 2-Phase Latches Flip-Flops Pulsed Latches Flop Combinational Logic Flop 2-Phase Transpar ent Latches Pul lsed Latches 1 2 p Latch T c /2 t nonoverlap Latch t nonoverlap t pw p Latch Combinational Logic Combinational Logic Half-Cycle 1 Half-Cycle 1 Combinational Logic Latch p Latch Slide 26

27 Timing iagrams Contamination ti and Propagation elays t pd t cd t pcq t ccq t pdq t pcq t setup t hold Logic Prop. elay Logic Cont. elay Latch/Flop Clk- Prop elay Latch/Flop Clk- Cont. elay Latch - Prop elay Latch - Cont. elay Latch/Flop Setup Time Latch/Flop Hold Time A Combinational Logic Flop Y A Y Latch t setup t cd t hold t ccq t pcq t pd t setup t hold t t ccq pcq t cdq t pdq Slide 27

28 Max-elay: Flip-Flops Flops t pd ( ) Tc sequencing overhead F1 1 Combinational Logic 2 F2 T c t pcq t setup 1 t pd 2 Slide 28

29 Max-elay: Flip-Flops Flops ( setup ) tpd Tc t + tpcq sequencing overhead F1 1 Combinational Logic 2 F2 T c t pcq t setup 1 t pd 2 Slide 29

30 Max elay: 2-Phase Latches ( ) tpd = tpd1+ tpd 2 Tc sequencing overhead Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L T c 1 t pdq1 1 t pd1 2 t pdq2 2 t pd2 3 Slide 30

31 Copyright 2011 Pearson Education, CMOS Inc. Publishing VLSI esign as Pearson Addison-Wesley

32 Max elay: 2-Phase Latches ( ) tpd = tpd1+ tpd 2 Tc 2 tpdq 123 sequencing overhead Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L T c 1 t pdq1 1 t pd1 2 t pdq2 2 t pd2 3 Slide 32

33 Max elay: Pulsed Latches t pd max ( ) Tc sequencing overhead 1 p L1 1 Combinational Logic 2 p L2 2 T c 1 t pdq (a) t pw > t setup 1 tpd 2 p (b) t pw < t setup 1 2 t pcq T c t pw tpd tsetup Slide 33

34 Min-elay: Flip-Flops Flops 1 t CL cd F1 2 F2 1 t ccq t cd 2 t hold Slide 34

35 Min-elay: Flip-Flops Flops 1 t t t CL cd hold ccq F1 2 F2 1 t ccq t cd 2 t hold Slide 35

36 Copyright 2011 Pearson Education, CMOS Inc. Publishing VLSI esign as Pearson Addison-Wesley

37 Min-elay: 2-Phase Latches t t cd1, cd 2 1 L1 1 CL Hold time reduced by nonoverlap 2 2 L2 Paradox: hold applies twice each cycle, vs. only once for flops. 1 2 t nonoverlap 1 t ccq t cd But a flop is made of two latches! 2 t hold Slide 37

38 Min-elay: 2-Phase Latches t t t t t cd1, cd 2 hold ccq nonoverlap 1 L1 1 CL Hold time reduced by nonoverlap 2 2 L2 Paradox: hold applies twice each cycle, vs. only once for flops. 1 2 t nonoverlap 1 t ccq t cd But a flop is made of two latches! 2 t hold Slide 38

39 Time Borrowing In a flop-based system: ata launches on one rising edge Must setup before next rising edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edges In a latch-based system ata can pass through latch while transparent Long cycle of logic can borrow time into next As long as each loop completes in one cycle Slide 39

40 Time Borrowing Example (a) Latch Combinational Logic Latch Combinational Logic Latch Borrowing time across half-cycle boundary Borrowing time across pipeline stage boundary 1 2 (b) Latch Combinational Logic Latch Combinational Logic Loops may borrow time internally but must complete within the cycle Slide 40

41 How Much Borrowing? 2-Phase Latches T borrow c setup + nonoverlap ( ) t t t L1 1 2 Combinational Logic 1 L T c t nonoverlap T /2 c Nominal Half-Cycle 1 elay t borrow t setup 2 Slide 41

42 Clock Skew We have assumed zero clock skew Clocks really have uncertainty in arrival time ecreases maximum propagation delay Increases minimum contamination delay ecreases time borrowing Slide 42

43 Skew: Flip-Flops Flops ( ) t pd Tc tpcq + tsetup + tskew t t t + t cd hold sequencing overhead ccq skew F1 1 1 t pcq Combinational Logic T c t pdq 2 t setup F2 t skew 2 F1 1 CL 2 F2 t skew t hold 1 t ccq 2 t cd Slide 43

44 Skew: Latches 2-Phase Latches ( 2 ) tpd Tc tpdq 123 sequencing overhead Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L3 3 t, t t t t + t cd1 cd 2 hold ccq nonoverlap skew 2 T t t + t + t 2 ( ) c borrow setup nonoverlap skew Slide 44

45 Two-Phase Clocking If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speed In this class, working chips are most important No tools to analyze clock skew An easy way to guarantee hold times is to use 2- phase latches with big nonoverlap times Call these clocks 1, 2 (ph1, ph2) Slide 45

46 Safe Flip-Flop Flop In class, use flip-flop with nonoverlapping clocks Very slow nonoverlap adds to setup time But no hold times In industry, use a better timing analyzer Add buffers to slow signals if hold time is at risk 2 1 X Slide 46

47 Summary Flip-Flops: Very easy to use, supported by all tools 2-Phase Transparent Latches: Lots of skew tolerance and time borrowing Pulsed Latches: Fast, some skew tol & borrow, hold time risk Slide 47

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