A NOVEL APPROACH FOR DESIGNING A D-FLIP FLOP USING MTCMOS TECHNIQUE FOR REDUCING POWER CONSUMPTION

Size: px
Start display at page:

Download "A NOVEL APPROACH FOR DESIGNING A D-FLIP FLOP USING MTCMOS TECHNIQUE FOR REDUCING POWER CONSUMPTION"

Transcription

1 A NOVEL APPROACH FOR DESIGNING A D-FLIP FLOP USING MTCMOS TECHNIQUE FOR REDUCING POWER CONSUMPTION Megala. C. D PG Scholar, Department of VLSI Design, Sri Shakthi Institute Of Engineering and Technology, Venkatesan.K Asst.Professor,Department of VLSI Design, Sri Shakthi Institute Of Engineering and Technology, Abstract Power consumption is a major bottleneck of system performance. A large portion of the on chip power is consumed by the clock system. It is made of the any integrated circuit, clock distribution network and flop-flops. A new system will considerably reduce the number of transistor it will lead to the reduction in clocking power and also improve the overall power consumption. Various design techniques used for a low power clocking system. Among those techniques Clocked Pair Shared Flip Flop(CPSFF) consume least power than Conditional Data Mapping Flip- Flop(CDMFF), Conditional Discharge Flip Flop(CDFF) and Conventional double Edge Triggered Flip-Flop (DEFF). A proposed novel Clocked Pair Shared Flip- Flop(CPSFF) using Multi-Threshold voltage CMOS(MTCMOS) technique which reduces the power consumption approximately by 20% to 90% than the original CPSFF. Simulation using Tanner Tool version with 250 nanometer technology. The power consumption is calculated by T Spice. The proposed work clock pair shared flip flop using MTCMOS technique is more efficient than all other designs. Key words- MTCMOS technique, integrated circuit, CPSFF, CDMFF,CDFF, DEFF, power delay. I. INTRODUCTION To optimize the power consumption, many low-power design techniques have been introduced, such as clock gating, power gating, creating multisupply-voltage designs, dynamic voltage frequency scaling, and minimizing clock network. Among these techniques, minimizing clock network is very important in reducing power consumption of a SoC. Power has become a big issue in modern VLSI design. Flip-Flop is an electronic circuit that is used to store a logical state of any data input signals with the response to a clock pulse. Flip-flops are widely used to receive and maintain data in selected sequences during recurring clock intervals for a limited time period sufficient for other circuits within a system. A huge portion of the on-chip power is consumed by clock systems, which consists of timing elements such as flipflops, latches and clock distribution network. These clock systems have redundant transition and the transition probability of the clock is 100% while an ordinary logic has onethird on average so clock systems are one of the most power consuming components in a VLSI system.these components consume 30% to 60% of the total power dissipation in 2.1a system Consequently, reduction in the power consumed by flip-flops will show a deep impact on the total power consumed. Several techniques as well as various flip-flops have been proposed recently to reduce redundancy in clock system. There are many flip-flops given in the literature. II. RELATED WORKS 301

2 A. Double edge triggered flip flop(deff) Figure 1.2 Conditional discharge flip-flop Figure 1.1 Double edge triggered flip flop Figure 1.1 shows that double edge triggered flip flop. Data sampling is done on both the rising and the falling edge of the clock signals by Double Edge triggered Flip Flop (DEFF)[1]. It has the same number of transistors as that of the conventional Single Edge triggered Flip-Flop (SEFF). Reduction of the frequency to half in case of DEFF results in abatement of the power dissipation to approximately half of the value of SEFF. B. Conditional discharge flip-flop(cdff) Figure 1.2 shows that the conditional discharge flip flop. CDFF operates in two stages. The first stage is mainly for the LOW to HIGH transition, and the second stage for HIGH to LOW transition. CDFF uses a pulse generator which eventually generates the pulses for implementing the circuit in double edge triggered technology. The discharge path of the first stage helps in preventing evaluation in the coming clock cycles as long as input remain stable level 1 C. Conditional Data Mapping Flip Flop(CDMFF) Figure 1.3 shows that the conditional data mapping flip flop. CDMFF uses only 7 clocked transistors.when compare with CDFF which uses 13clocked transistors [2] resulting in reduction of the power consumption. The conditional data mapping (CDM) methodology exploits the property of the flipflop, by providing the flip-flop with a stage to map its inputs to (0, 0) if a redundant event is predicted, such that the outputs will be unchanged when clock signal is triggered. The CDMFF has the floating node problem. The input for conditional data mapping flip flop is D and clock, and the output is Q. 302

3 7 clocked transistors shown in Figure (1.3). Hence reducing the clock load. In CPSFF the clocked pair is shared by the first and second stage. The always on pmos in CPSFF allows the internal node to be always connected to Vdd thus prevents the floating problem. Thus in terms of power consumption of clock circuit CPSFF is high efficient than CDMFF. Figure 1.3 Conditional Data Mapping Flip-Flop III.PROPOSED SYSTEM The main focus of this work is on minimizing the power consumption in any internal circuit. So that multi threshold CMOS (MTCMOS) technique is used with the clocked pair shared flip flop for reducing the power consumption. D. Clocked Pair Shared Flip Flop(CPSFF) Figure 1.5 Power gating technique using MTCMOS. Figure 1.4 Clocked Pair Shared Flip-Flop Figure 1.4 shows that the clocked pair shared flip flop. The CPSFF overcomes the problem of floating node in CDMFF by reducing the number of clocked transistors. CPSFF uses 4 clocked transistors while comparing with CDMFF which uses The figure 1,5 shows that the power gating technique using MTCMOS. The diagram consists of two sleep transistors S1 and S2 with higher V. The logic circuit between the S1 and S2 is not directly connected to real supply lines V dd and G nd. but in turn it is connected to virtual power supply lines Vdd v and Gnd v and has low V. Both the sleep transistors are given complementary inputs S and SBAR. The circuit operates in two modes active mode and standby mode. In active mode, S=0 and SBAR=1 such that S1 and S2 are ON and virtual supply lines Vdd and Gnd work as real supply lines therefore the logic circuit operates normally and at t higher speed. 303

4 In sleep mode, S=1 and SBAR=0 such that S1 And S2 are OFF and this will cause virtual power supply lines to float and large leakage current present in circuit is suppressed by sleep transistors S1 and S2 resulting in lower leakage current and thus reducing power consumption. The figure 1.6 shows that the schematic diagram of CPSFF using MTCMOS technique[3]. The flip flop works, when both clk and clkdb are at logic 1. Pseudo nmos and conditional mapping technique both are combined using the above scheme. The nmos M3 is controlled by a feedback signal. For input D=1and S=1,Q will be high, switching ON the transistor M8, and turning OFF M3 thus parrying redundant switching activity and flow of short- circuit current at the node X. the flip flop depends upon the state previously acquired by Q and QB along with the clock and the data signal inputs provided. IV. RESULT ANALYSIS The below table is shows the power analysis for various flip flop. The inputs are 1.5v, 3.3v and 5v.which is calculated in watts. The power analysis is calculated in different temperature. While comparing the various flip flop like, DEFF, CDFF, CMFF,CPSFF,MTCPSFF. The MTCPSFF consume least power then the other flip flop. Table 1 Comparison of power analysis for D-flip-flops. The MTCPSFF waveform is shown below, D is the input and Q is the output, clock is also the input. Figure1.6 Schematic of Proposed CPSFF using MTCMOS. When D transits to 1 the output Q is pulled up by pmos M2 whereas M4 is used to pull down Q when D=0 and Y=1 at the arrival of clock pulse. When the input D transits from 0-1 the short-circuit occurs for once even though M1 is always ON, thus disconnecting the discharge path and turning off M3 after two gates delay by feedback signal. There will be no short-circuiting even if the input D stays high as M3 disconnects the discharge path. The output of Figure 5.5 Output waveform of MTCPSFF 304

5 Table 1.1 Power analysis Design name Temperature = 25 C Power consumption (in watts) 27 C 1.5v 3.3v 5v 1.5v 3.3v 5v CDFF 3.309x x x x x x10 - DEFF x x x x x x10 - CDMFF x x x x x x10 - CPSFF x x x x x x10 - MTCMOS x x x x x x10 - V.CONCLUSION The existing clocked pair shared flip flop using MTCMOS reduces local clock transistor number and power consumption as well. The proposed MT- CPSFF has given better result than the previously existing DEFF, CDFF, CDMFF and CPSFF in terms of power and good output response by approximately 20% to 90%. Furthermore, several low power techniques, including Forced stack technique, can be explored to incorporate into the new flip-flop to build system. VII. FUTURE ENHANCEMENT The work will be extended by using Forced stack technique for reducing power consumption in D flip-flop and can be implemented in any one of the applications. Further the work can be extended in reducing the number of transistors in MTCMOS Clock Pair Shared Flip-flop. VI. ACKNOWLEDGMENT I thank my teachers for their continuous support and encouragement in this work, for cultivating new and aspiring ideas in my mind. I would especially thank to my friends and Mr. K.Venkatesan, Assistant Professor, for guiding through the process. VIII.REFERENCES [1] Pedram.M, Wu.Q, and Wu.X,(Jan.2002) A new Design for Double Edge Triggered Flip-flops. [2] The.C.K, Hamada.M, Fujita.T,Hara.H, Ikumi.N, 305

6 and Oowaki.Y,(December 2006) Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems.IEEE Transactions on very largescale integration (VLSI) systems, vol. 14, no. 12. [3] Zhou.Q, Zhao.X, Cai.Y, Hong.X(2), An MTCMOS technology for low-power physical design, Integration VLSI J. [4] Kavitha.T, Dr.Sumalatha.V, (2012. ) A New Reduced Clock Power Flip flop for Future SOC Applications.International Journal of Computer Trends and Technology,volume3 Issue4. [5] Weste.N and Harris.D (2), CMOS VLSI Design. Reading, MA: Addison Wesley. [6] F. Mohammad, L. A. Abhilasand P.Srinivas A new parallel counter architecture with reduced transistor count for power and area optimization, international conferenceon Electrical and Electronics Engineering, Sept., [7] HemanthaS, Dhawan A and Kar H, Multithreshold CMOS design for low power digital circuits, TENCON 2-2 IEEE Region 10 Conference, pp.1-5,

II. PROPOSED FLIP FLOP DESIGN

II. PROPOSED FLIP FLOP DESIGN A Review on High Performance Low Power Conditional Discharge Flip Flop Sonam Parihar 1, Rachana Arya 2 1 P.G student, Bipin Tripathi Kumaon Institute of Technology, Dwarahat, Almora, Uttarakhand 2 Assistant

More information

Design and analysis of flip flops for low power clocking system

Design and analysis of flip flops for low power clocking system Design and analysis of flip flops for low power clocking system Gabariyala sabadini.c PG Scholar, VLSI design, Department of ECE,PSNA college of Engg and Tech, Dindigul,India. Jeya priyanka.p PG Scholar,

More information

TRUE SINGLE PHASE CLOCKING BASED FLIP-FLOP DESIGN

TRUE SINGLE PHASE CLOCKING BASED FLIP-FLOP DESIGN TRUE SINGLE PHASE CLOCKING BASED FLIP-FLOP DESIGN USING DIFFERENT FOUNDRIES Priyanka Sharma 1 and Rajesh Mehra 2 1 ME student, Department of E.C.E, NITTTR, Chandigarh, India 2 Associate Professor, Department

More information

True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique

True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique Priyanka Sharma ME (ECE) Student NITTTR Chandigarh Rajesh Mehra Associate Professor Department of ECE NITTTR Chandigarh

More information

Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications

Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications TRIPTI SHARMA, K. G. SHARMA, B. P. SINGH, NEHA ARORA Electronics & Communication Department MITS Deemed University,

More information

CHAPTER 11: Flip Flops

CHAPTER 11: Flip Flops CHAPTER 11: Flip Flops In this chapter, you will be building the part of the circuit that controls the command sequencing. The required circuit must operate the counter and the memory chip. When the teach

More information

S. Venkatesh, Mrs. T. Gowri, Department of ECE, GIT, GITAM University, Vishakhapatnam, India

S. Venkatesh, Mrs. T. Gowri, Department of ECE, GIT, GITAM University, Vishakhapatnam, India Power reduction on clock-tree using Energy recovery and clock gating technique S. Venkatesh, Mrs. T. Gowri, Department of ECE, GIT, GITAM University, Vishakhapatnam, India Abstract Power consumption of

More information

CHAPTER 16 Memory Circuits

CHAPTER 16 Memory Circuits CHAPTER 16 Memory Circuits Introduction! The 2 major logic classifications are! Combinational circuits: Their output depends only on the present value of the input. These circuits do not have memory.!

More information

Design and Analysis of D Flip Flop Using Different Technologies

Design and Analysis of D Flip Flop Using Different Technologies Design and Analysis of D Flip Flop Using Different Technologies Hardeep Kaur, Er.Swarnjeet Singh, Sukhdeep Kaur M.Tech Student, Dept. of ECE, Baba Farid College of Engineering &Technology, Bathinda, Punjab,

More information

Design of Energy Efficient Low Power Full Adder using Supply Voltage Gating

Design of Energy Efficient Low Power Full Adder using Supply Voltage Gating Design of Energy Efficient Low Power Full Adder using Supply Voltage Gating S.Nandhini 1, T.G.Dhaarani 2, P.Kokila 3, P.Premkumar 4 Assistant Professor, Dept. of ECE, Nandha Engineering College, Erode,

More information

So far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs.

So far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs. equential Logic o far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs. In sequential logic the output of the

More information

ECE124 Digital Circuits and Systems Page 1

ECE124 Digital Circuits and Systems Page 1 ECE124 Digital Circuits and Systems Page 1 Chip level timing Have discussed some issues related to timing analysis. Talked briefly about longest combinational path for a combinational circuit. Talked briefly

More information

Design of Digital Systems II Sequential Logic Design Principles (1)

Design of Digital Systems II Sequential Logic Design Principles (1) Design of Digital Systems II Sequential Logic Design Principles (1) Moslem Amiri, Václav Přenosil Masaryk University Resource: Digital Design: Principles & Practices by John F. Wakerly Introduction Logic

More information

Design and Implementation of T-Flip Flop using GDI Techniques

Design and Implementation of T-Flip Flop using GDI Techniques Design and Implementation of T-Flip Flop using GDI Techniques Ritesh Kumar Yadav M.E. Scholar Department of Electronics & Communication NITTTR, Chandigarh, UT, INDIA Abstract: Gate diffusion input is a

More information

A Survey on Sequential Elements for Low Power Clocking System

A Survey on Sequential Elements for Low Power Clocking System Journal of Computer Applications ISSN: 0974 1925, Volume-5, Issue EICA2012-3, February 10, 2012 A Survey on Sequential Elements for Low Power Clocking System Bhuvana S ECE Department, Avinashilingam University

More information

International Journal of Electronics and Computer Science Engineering 1482

International Journal of Electronics and Computer Science Engineering 1482 International Journal of Electronics and Computer Science Engineering 1482 Available Online at www.ijecse.org ISSN- 2277-1956 Behavioral Analysis of Different ALU Architectures G.V.V.S.R.Krishna Assistant

More information

Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.

Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage

More information

Sequential Logic. References:

Sequential Logic. References: Sequential Logic References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey, Prentice Hall UCB Principles of CMOS VLSI Design: A Systems Perspective, N. H. E. Weste, K. Eshraghian,

More information

LOW POWER DESIGN OF DIGITAL SYSTEMS USING ENERGY RECOVERY CLOCKING AND CLOCK GATING

LOW POWER DESIGN OF DIGITAL SYSTEMS USING ENERGY RECOVERY CLOCKING AND CLOCK GATING LOW POWER DESIGN OF DIGITAL SYSTEMS USING ENERGY RECOVERY CLOCKING AND CLOCK GATING A thesis work submitted to the faculty of San Francisco State University In partial fulfillment of the requirements for

More information

DIGITAL SYSTEM DESIGN LAB

DIGITAL SYSTEM DESIGN LAB EXPERIMENT NO: 7 STUDY OF FLIP FLOPS USING GATES AND IC S AIM: To verify various flip-flops like D, T, and JK. APPARATUS REQUIRED: Power supply, Digital Trainer kit, Connecting wires, Patch Chords, IC

More information

NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter

NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential

More information

Low Power and Low Frequency CMOS Ring Oscillator Design

Low Power and Low Frequency CMOS Ring Oscillator Design Available online www.ejaet.com European Journal of Advances in Engineering and Technology, 2015, 2(7): 82-87 Research Article ISSN: 2394-658X Low Power and Low Frequency CMOS Ring Oscillator Design Venigalla

More information

Published by: PIONEER RESEARCH & DEVELOPMENT GROUP (www.prdg.org) 1

Published by: PIONEER RESEARCH & DEVELOPMENT GROUP (www.prdg.org) 1 Digital design of Low power CMOS D-Latch basic K.Prasad Babu 1, S.Ahmed Basha 2, H.Devanna 3, K.Suvarna 4 1,2,3,4 Assistant Professor, St.Jonhs College of Engineering & Technology, Yemmiganur Abstract:

More information

Chapter 9 Latches, Flip-Flops, and Timers

Chapter 9 Latches, Flip-Flops, and Timers ETEC 23 Programmable Logic Devices Chapter 9 Latches, Flip-Flops, and Timers Shawnee State University Department of Industrial and Engineering Technologies Copyright 27 by Janna B. Gallaher Latches A temporary

More information

Latches and Flip-Flops characterestics & Clock generator circuits

Latches and Flip-Flops characterestics & Clock generator circuits Experiment # 7 Latches and Flip-Flops characterestics & Clock generator circuits OBJECTIVES 1. To be familiarized with D and JK flip-flop ICs and their characteristic tables. 2. Understanding the principles

More information

Power Optimized Memory Organization Using Clock Gating

Power Optimized Memory Organization Using Clock Gating International Journal of Engineering and Technical Research (IJETR) ISSN: 2321-0869, Volume-2, Issue-6, June 2014 Power Optimized Memory Organization Using Clock Gating Lucky Khandelwal, Arpan Shah, Ramesh

More information

5. Sequential CMOS Logic Circuits

5. Sequential CMOS Logic Circuits 5. Sequential CMOS Logic Circuits In sequential logic circuits the output signals is determined by the current inputs as well as the previously applied input variables. Fig. 5.1a shows a sequential circuit

More information

Sequential Circuits. Prof. MacDonald

Sequential Circuits. Prof. MacDonald Sequential Circuits Prof. MacDonald Sequential Element Review l Sequential elements provide memory for circuits heart of a state machine saving current state used to hold or pipe data data registers, shift

More information

Lesson 12 Sequential Circuits: Flip-Flops

Lesson 12 Sequential Circuits: Flip-Flops Lesson 12 Sequential Circuits: Flip-Flops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability

More information

Sequential Logic: Clocks, Registers, etc.

Sequential Logic: Clocks, Registers, etc. ENEE 245: igital Circuits & Systems Lab Lab 2 : Clocks, Registers, etc. ENEE 245: igital Circuits and Systems Laboratory Lab 2 Objectives The objectives of this laboratory are the following: To design

More information

SCAN CHAINS TESTING FOR LATCHES TO REDUCE AREA AND THE POWER CONSUMPTION

SCAN CHAINS TESTING FOR LATCHES TO REDUCE AREA AND THE POWER CONSUMPTION SCAN CHAINS TESTING FOR LATCHES TO REDUCE AREA AND THE POWER CONSUMPTION Anusuya Yuvaraj 1, R. C. Biradar 2 1,2 Department of Electronics and Communication Engineering, Reva Institute of Technology and

More information

Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa

Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation

More information

CMOS Digital Circuits

CMOS Digital Circuits CMOS Digital Circuits Types of Digital Circuits Combinational The value of the outputs at any time t depends only on the combination of the values applied at the inputs at time t (the system has no memory)

More information

Chapter 14 Sequential logic, Latches and Flip-Flops

Chapter 14 Sequential logic, Latches and Flip-Flops Chapter 14 Sequential logic, Latches and Flip-Flops Flops Lesson 2 Sequential logic circuit, Flip Flop and Latch Introduction Ch14L2--"Digital Principles and Design", Raj Kamal, Pearson Education, 2006

More information

DIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse.

DIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse. DIGITAL COUNTERS http://www.tutorialspoint.com/computer_logical_organization/digital_counters.htm Copyright tutorialspoint.com Counter is a sequential circuit. A digital circuit which is used for a counting

More information

LOW POWER DUAL EDGE - TRIGGERED STATIC D FLIP-FLOP

LOW POWER DUAL EDGE - TRIGGERED STATIC D FLIP-FLOP LOW POWER DUAL EDGE - TRIGGERED STATIC D FLIP-FLOP Anurag #1, Gurmohan Singh #2, V. Sulochana #3 # Centre for Development of Advanced Computing, Mohali, India 1 anuragece09@gmail.com 2 gurmohan@cdac.in

More information

Lecture 8: Synchronous Digital Systems

Lecture 8: Synchronous Digital Systems Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered

More information

Counters and Decoders

Counters and Decoders Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4-bit ripple-through decade counter with a decimal read-out display. Such a counter

More information

To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC.

To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC. 8.1 Objectives To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC. 8.2 Introduction Circuits for counting events are frequently used in computers and other digital

More information

Lecture 10: Latch and Flip-Flop Design. Outline

Lecture 10: Latch and Flip-Flop Design. Outline Lecture 1: Latch and Flip-Flop esign Slides orginally from: Vladimir Stojanovic Computer Systems Laboratory Stanford University horowitz@stanford.edu 1 Outline Recent interest in latches and flip-flops

More information

Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill

Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.

More information

Design of OSC and Ramp Generator block for Boost Switching Regulator

Design of OSC and Ramp Generator block for Boost Switching Regulator Analog IC Design Contest 2011 Navis Team Hanoi University of Science and Technology Design of OSC and Ramp Generator block for Boost Switching Regulator Final Report Students: Advisors: Pham Van Danh (senior

More information

Sequential 4-bit Adder Design Report

Sequential 4-bit Adder Design Report UNIVERSITY OF WATERLOO Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4-bit Adder Design Report Prepared by: Ian Hung (ixxxxxx), 99XXXXXX Annette Lo (axxxxxx), 99XXXXXX Pamela

More information

Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology

Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology Nahid Rahman Department of electronics and communication FET-MITS (Deemed university), Lakshmangarh, India B. P. Singh Department

More information

EEC 116 Lecture #6: Sequential Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #6: Sequential Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 116 Lecture #6: Sequential Logic Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 3 extended, same due date as Lab 4 HW4 issued today Amirtharajah/Parkhurst,

More information

Performance of Flip-Flop Using 22nm CMOS Technology

Performance of Flip-Flop Using 22nm CMOS Technology Performance of Flip-Flop Using 22nm CMOS Technology K.Rajasri 1, A.Bharathi 2, M.Manikandan 3 M.E, Applied Electronics, IFET College of Engineering, Villupuram, India 1, 2 Assistant Professor, Department

More information

Power Reduction Techniques in the SoC Clock Network. Clock Power

Power Reduction Techniques in the SoC Clock Network. Clock Power Power Reduction Techniques in the SoC Network Low Power Design for SoCs ASIC Tutorial SoC.1 Power Why clock power is important/large» Generally the signal with the highest frequency» Typically drives a

More information

Basics of Energy & Power Dissipation

Basics of Energy & Power Dissipation Basics of Energy & Power Dissipation ecture notes S. Yalamanchili, S. Mukhopadhyay. A. Chowdhary Basic Concepts Dynamic power Static power Time, Energy, Power Tradeoffs Activity model for power estimation

More information

ASYNCHRONOUS COUNTERS

ASYNCHRONOUS COUNTERS LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding

More information

Lecture 10. Latches and Flip-Flops

Lecture 10. Latches and Flip-Flops Logic Design Lecture. Latches and Flip-Flops Prof. Hyung Chul Park & Seung Eun Lee Sequential Logic Outputs of sequential logic depend on current inputs and prior input values Sequential logic might explicitly

More information

Design of Low Power One-Bit Hybrid-CMOS Full Adder Cells

Design of Low Power One-Bit Hybrid-CMOS Full Adder Cells Design of Low Power One-Bit Hybrid-CMOS Full Adder Cells Sushil B. Bhaisare 1, Sonalee P. Suryawanshi 2, Sagar P. Soitkar 3 1 Lecturer in Electronics Department, Nagpur University, G.H.R.I.E.T.W. Nagpur,

More information

Figure 2.1(a) Bistable element circuit.

Figure 2.1(a) Bistable element circuit. 3.1 Bistable Element Let us look at the inverter. If you provide the inverter input with a 1, the inverter will output a 0. If you do not provide the inverter with an input (that is neither a 0 nor a 1),

More information

Module-3 SEQUENTIAL LOGIC CIRCUITS

Module-3 SEQUENTIAL LOGIC CIRCUITS Module-3 SEQUENTIAL LOGIC CIRCUITS Till now we studied the logic circuits whose outputs at any instant of time depend only on the input signals present at that time are known as combinational circuits.

More information

NEW adder cells are useful for designing larger circuits despite increase in transistor count by four per cell.

NEW adder cells are useful for designing larger circuits despite increase in transistor count by four per cell. CHAPTER 4 THE ADDER The adder is one of the most critical components of a processor, as it is used in the Arithmetic Logic Unit (ALU), in the floating-point unit and for address generation in case of cache

More information

9. Memory Elements and Dynamic Logic

9. Memory Elements and Dynamic Logic 9. Memory Elements and RS Flipflop The RS-flipflop is a bistable element with two inputs: Reset (R), resets the output Q to 0 Set (S), sets the output Q to 1 2 RS-Flipflops There are two ways to implement

More information

A Novel Low Power, High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold Loss Problem

A Novel Low Power, High Speed 14 Transistor CMOS Full Adder Cell with 50% Improvement in Threshold Loss Problem A Novel Low Power, High Speed 4 Transistor CMOS Full Adder Cell with 5% Improvement in Threshold Loss Problem T. Vigneswaran, B. Mukundhan, and P. Subbarami Reddy Abstract Full adders are important components

More information

The OpEL will close at 4:30PM on Thursday Nov 8. Week 9 is due next Wed (Nov 7) as usual. The make-up lab (photoflash) is due Wed Nov 14.

The OpEL will close at 4:30PM on Thursday Nov 8. Week 9 is due next Wed (Nov 7) as usual. The make-up lab (photoflash) is due Wed Nov 14. The OpEL will close at 4:30PM on Thursday Nov 8. Week 9 is due next Wed (Nov 7) as usual. The make-up lab (photoflash) is due Wed Nov 14. 1 As an Astable Multivibrator 2 3 An integrated chip that is used

More information

SEQUENTIAL CIRCUITS. Block diagram. Flip Flop. S-R Flip Flop. Block Diagram. Circuit Diagram

SEQUENTIAL CIRCUITS. Block diagram. Flip Flop. S-R Flip Flop. Block Diagram. Circuit Diagram SEQUENTIAL CIRCUITS http://www.tutorialspoint.com/computer_logical_organization/sequential_circuits.htm Copyright tutorialspoint.com The combinational circuit does not use any memory. Hence the previous

More information

TS555. Low-power single CMOS timer. Description. Features. The TS555 is a single CMOS timer with very low consumption:

TS555. Low-power single CMOS timer. Description. Features. The TS555 is a single CMOS timer with very low consumption: Low-power single CMOS timer Description Datasheet - production data The TS555 is a single CMOS timer with very low consumption: Features SO8 (plastic micropackage) Pin connections (top view) (I cc(typ)

More information

Sequential Circuits: Latches & Flip-Flops

Sequential Circuits: Latches & Flip-Flops ESD I Lecture 3.b Sequential Circuits: Latches & Flip-Flops 1 Outline Memory elements Latch SR latch D latch Flip-Flop SR flip-flop D flip-flop JK flip-flop T flip-flop 2 Introduction A sequential circuit

More information

Lecture 9: Flip-flops

Lecture 9: Flip-flops Points Addressed in this Lecture Properties of synchronous and asynchronous sequential circuits Overview of flip-flops and latches Lecture 9: Flip-flops Professor Peter Cheung Department of EEE, Imperial

More information

Lecture 8: Latch and Flip Flop Design

Lecture 8: Latch and Flip Flop Design Lecture 8: Latch and Flip Flop Design Slides originally from: Vladimir Stojanovic & Vojin G. Oklobdzija Computer Systems Laboratory Stanford University horowitz@stanford.edu 1 Outline Recent interest in

More information

DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: SEQUENTIAL CIRCUITS BASICS AND FLIP-FLOPS

DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: SEQUENTIAL CIRCUITS BASICS AND FLIP-FLOPS DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 5. LECTURE: SEQUENTIAL CIRCUITS BASICS AND FLIP-FLOPS 1st (Autumn) term 2014/2015 5. LECTURE 1. Sequential

More information

Sequential Circuits: Latches & Flip-Flops

Sequential Circuits: Latches & Flip-Flops Sequential Circuits: Latches & Flip-Flops Sequential Circuits Combinational Logic: Output depends only on current input Able to perform useful operations (add/subtract/multiply/encode/decode/ select[mux]/etc

More information

Sequential Circuits: Latches and Flip-Flops

Sequential Circuits: Latches and Flip-Flops Sequential Circuits: Latches and Flip-Flops Sequential circuits Output depends on current input and past sequence of input(s) How can we tell if the input is current or from the past? A clock pulse can

More information

ECE380 Digital Logic

ECE380 Digital Logic ECE38 igital Logic Flip-Flops, Registers and Counters: Flip-Flops r.. J. Jackson Lecture 25- Flip-flops The gated latch circuits presented are level sensitive and can change states more than once during

More information

Digital Controller for Pedestrian Crossing and Traffic Lights

Digital Controller for Pedestrian Crossing and Traffic Lights Project Objective: - To design and simulate, a digital controller for traffic and pedestrian lights at a pedestrian crossing using Microsim Pspice The controller must be based on next-state techniques

More information

Chapter 10 Advanced CMOS Circuits

Chapter 10 Advanced CMOS Circuits Transmission Gates Chapter 10 Advanced CMOS Circuits NMOS Transmission Gate The active pull-up inverter circuit leads one to thinking about alternate uses of NMOS devices. Consider the circuit shown in

More information

EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad

EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/20 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,

More information

IMPLEMENTATION OF HIGH SPEED ENHANCED CSLA BASED ON GATED D-LATCH

IMPLEMENTATION OF HIGH SPEED ENHANCED CSLA BASED ON GATED D-LATCH IMPLEMENTATION OF HIGH SPEED ENHANCED BASED ON GATED D-LATCH 1 MEDA NAGAPAVANI, 2 T. JYOTHI 1 P.G Student, VLSI Design, Dept of ECE, 2 Assistant Professor, Dept of ECE. Sri Venkatesa Perumal College of

More information

3 Flip-Flops. The latch is a logic block that has 2 stable states (0) or (1). The RS latch can be forced to hold a 1 when the Set line is asserted.

3 Flip-Flops. The latch is a logic block that has 2 stable states (0) or (1). The RS latch can be forced to hold a 1 when the Set line is asserted. 3 Flip-Flops Flip-flops and latches are digital memory circuits that can remain in the state in which they were set even after the input signals have been removed. This means that the circuits have a memory

More information

Micro-Step Driving for Stepper Motors: A Case Study

Micro-Step Driving for Stepper Motors: A Case Study Micro-Step Driving for Stepper Motors: A Case Study N. Sedaghati-Mokhtari Graduate Student, School of ECE, University of Tehran, Tehran, Iran n.sedaghati @ece.ut.ac.ir Abstract: In this paper, a case study

More information

Power Optimization Technique Based On Multi-Bit Flip-Flop Design

Power Optimization Technique Based On Multi-Bit Flip-Flop Design P. Sathyaa et al Int. Journal of Engineering Research and Applications RESEARCH ARTICLE OPEN ACCESS Power Optimization Technique Based On Multi-Bit Flip-Flop Design P. Sathyaa, K. Sinduja M.E. VLSI DESIGN

More information

Chapter 2 Logic Gates and Introduction to Computer Architecture

Chapter 2 Logic Gates and Introduction to Computer Architecture Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are

More information

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute. 2nd (Spring) term 2012/2013

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute. 2nd (Spring) term 2012/2013 DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 4. LECTURE: COUNTERS AND RELATED 2nd (Spring) term 2012/2013 1 4. LECTURE: COUNTERS AND RELATED 1. Counters,

More information

Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012

Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012 Latches, the D Flip-Flop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR

More information

Multivibrator Circuits. Bistable multivibrators

Multivibrator Circuits. Bistable multivibrators Multivibrator ircuits Bistable multivibrators Multivibrators ircuits characterized by the existence of some well defined states, amongst which take place fast transitions, called switching processes. A

More information

10 BIT s Current Mode Pipelined ADC

10 BIT s Current Mode Pipelined ADC 10 BIT s Current Mode Pipelined ADC K.BHARANI VLSI DEPARTMENT VIT UNIVERSITY VELLORE, INDIA kothareddybharani@yahoo.com P.JAYAKRISHNAN VLSI DEPARTMENT VIT UNIVERSITY VELLORE, INDIA pjayakrishnan@vit.ac.in

More information

Karnaugh Maps. Example A B C X 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1. each 1 here gives a minterm e.g.

Karnaugh Maps. Example A B C X 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1. each 1 here gives a minterm e.g. Karnaugh Maps Yet another way of deriving the simplest Boolean expressions from behaviour. Easier than using algebra (which can be hard if you don't know where you're going). Example A B C X 0 0 0 0 0

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic

More information

CMOS Binary Full Adder

CMOS Binary Full Adder CMOS Binary Full Adder A Survey of Possible Implementations Group : Eren Turgay Aaron Daniels Michael Bacelieri William Berry - - Table of Contents Key Terminology...- - Introduction...- 3 - Design Architectures...-

More information

Flip-Flops. Outline: 2. Timing noise

Flip-Flops. Outline: 2. Timing noise Outline: 2. Timing noise Flip-Flops Signal races, glitches FPGA example ( assign bad) Synchronous circuits and memory Logic gate example 4. Flip-Flop memory RS-latch example D and JK flip-flops Flip-flops

More information

IMPLEMENTATION OF HIGH SPEED ENHANCED CSLA BASED ON GATED D-LATCH:

IMPLEMENTATION OF HIGH SPEED ENHANCED CSLA BASED ON GATED D-LATCH: IMPLEMENTATION OF HIGH SPEED ENHANCED BASED ON GATED D-LATCH 1 MEDA NAGAPAVANI, 2 T. JYOTHI 1 P.G Student, VLSI Design, Dept of ECE, 2 Assistant Professor, Dept of ECE. Sri Venkatesa Perumal College of

More information

Timing pulses & counters

Timing pulses & counters Timing pulses & counters Timing Pulses Important element of laboratory electronics Pulses can control logical sequences with precise timing. If your detector sees a charged particle or a photon, you might

More information

Module 4 : Propagation Delays in MOS Lecture 20 : Analyzing Delay in few Sequential Circuits

Module 4 : Propagation Delays in MOS Lecture 20 : Analyzing Delay in few Sequential Circuits Module 4 : Propagation Delays in MOS Lecture 20 : Analyzing Delay in few Sequential Circuits Objectives In this lecture you will learn the delays in following circuits Motivation Negative D-Latch S-R Latch

More information

Layout of Multiple Cells

Layout of Multiple Cells Layout of Multiple Cells Beyond the primitive tier primitives add instances of primitives add additional transistors if necessary add substrate/well contacts (plugs) add additional polygons where needed

More information

DESIGN CHALLENGES OF TECHNOLOGY SCALING

DESIGN CHALLENGES OF TECHNOLOGY SCALING DESIGN CHALLENGES OF TECHNOLOGY SCALING IS PROCESS TECHNOLOGY MEETING THE GOALS PREDICTED BY SCALING THEORY? AN ANALYSIS OF MICROPROCESSOR PERFORMANCE, TRANSISTOR DENSITY, AND POWER TRENDS THROUGH SUCCESSIVE

More information

Digital Logic Design Sequential circuits

Digital Logic Design Sequential circuits Digital Logic Design Sequential circuits Dr. Eng. Ahmed H. Madian E-mail: ahmed.madian@guc.edu.eg Dr. Eng. Rania.Swief E-mail: rania.swief@guc.edu.eg Dr. Eng. Ahmed H. Madian Registers An n-bit register

More information

DIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department

DIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department Counters By: Electrical Engineering Department 1 Counters Upon completion of the chapter, students should be able to:.1 Understand the basic concepts of asynchronous counter and synchronous counters, and

More information

ET398 LAB 6. Flip-Flops in VHDL

ET398 LAB 6. Flip-Flops in VHDL ET398 LAB 6 Flip-Flops in VHDL Flip-Flops March 3, 2013 Tiffany Turner OBJECTIVE The objectives of this lab are for you to begin the sequential and memory programming using flip flops in VHDL program.

More information

Low Power VLSI Circuits and Systems Prof. Pro. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur

Low Power VLSI Circuits and Systems Prof. Pro. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Low Power VLSI Circuits and Systems Prof. Pro. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture No. # 14 Pass Transistor Logic Circuits - I Hello

More information

New Polymorphic NAND/XOR Gate

New Polymorphic NAND/XOR Gate 7th WSEAS International Conference on APPLIED COMPUTER SCIENCE, Venice, Italy, November 21-23, 2007 192 New Polymorphic NAND/XOR Gate RICHARD RUZICKA Faculty of Information Technology Brno University of

More information

MM74HC4046 CMOS Phase Lock Loop

MM74HC4046 CMOS Phase Lock Loop CMOS Phase Lock Loop General Description The MM74HC4046 is a low power phase lock loop utilizing advanced silicon-gate CMOS technology to obtain high frequency operation both in the phase comparator and

More information

Low Power AMD Athlon 64 and AMD Opteron Processors

Low Power AMD Athlon 64 and AMD Opteron Processors Low Power AMD Athlon 64 and AMD Opteron Processors Hot Chips 2004 Presenter: Marius Evers Block Diagram of AMD Athlon 64 and AMD Opteron Based on AMD s 8 th generation architecture AMD Athlon 64 and AMD

More information

Sequential Logic Latches & Flip-flops

Sequential Logic Latches & Flip-flops Sequential Logic Latches & Flip-flops Introduction Memory Elements Pulse-Triggered Latch S-R Latch Gated S-R Latch Gated D Latch Edge-Triggered Flip-flops S-R Flip-flop D Flip-flop J-K Flip-flop T Flip-flop

More information

Sequential Logic Design Principles.Latches and Flip-Flops

Sequential Logic Design Principles.Latches and Flip-Flops Sequential Logic Design Principles.Latches and Flip-Flops Doru Todinca Department of Computers Politehnica University of Timisoara Outline Introduction Bistable Elements Latches and Flip-Flops S-R Latch

More information

AN AUTOMATIC LINE VOLTAGE SWITCHING CIRCUIT

AN AUTOMATIC LINE VOLTAGE SWITCHING CIRCUIT APPLICATION NOTE ABSTRACT AN AUTOMATIC LINE VOLTAGE SWITCHING CIRCUIT The voltages found in line sockets around the world vary widely. Power supply designers have, most often, overcome this problem by

More information

Ring oscillators and multi-stable circuits

Ring oscillators and multi-stable circuits Chapter 6 ing oscillators and multi-stable circuits 6. ing oscillators uppose we take five inverters and connect them end to end as shown in Figure 6.. A B C E Figure 6.: Five stage ring oscillator. Let

More information

CMOS Thyristor Based Low Frequency Ring Oscillator

CMOS Thyristor Based Low Frequency Ring Oscillator CMOS Thyristor Based Low Frequency Ring Oscillator Submitted by: PIYUSH KESHRI BIPLAB DEKA 4 th year Undergraduate Student 4 th year Undergraduate Student Electrical Engineering Dept. Electrical Engineering

More information

Unit 4 Session - 15 Flip-Flops

Unit 4 Session - 15 Flip-Flops Objectives Unit 4 Session - 15 Flip-Flops Usage of D flip-flop IC Show the truth table for the edge-triggered D flip-flop and edge-triggered JK flip-flop Discuss some of the timing problems related to

More information