A NOVEL APPROACH FOR DESIGNING A DFLIP FLOP USING MTCMOS TECHNIQUE FOR REDUCING POWER CONSUMPTION


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1 A NOVEL APPROACH FOR DESIGNING A DFLIP FLOP USING MTCMOS TECHNIQUE FOR REDUCING POWER CONSUMPTION Megala. C. D PG Scholar, Department of VLSI Design, Sri Shakthi Institute Of Engineering and Technology, Venkatesan.K Asst.Professor,Department of VLSI Design, Sri Shakthi Institute Of Engineering and Technology, Abstract Power consumption is a major bottleneck of system performance. A large portion of the on chip power is consumed by the clock system. It is made of the any integrated circuit, clock distribution network and flopflops. A new system will considerably reduce the number of transistor it will lead to the reduction in clocking power and also improve the overall power consumption. Various design techniques used for a low power clocking system. Among those techniques Clocked Pair Shared Flip Flop(CPSFF) consume least power than Conditional Data Mapping Flip Flop(CDMFF), Conditional Discharge Flip Flop(CDFF) and Conventional double Edge Triggered FlipFlop (DEFF). A proposed novel Clocked Pair Shared Flip Flop(CPSFF) using MultiThreshold voltage CMOS(MTCMOS) technique which reduces the power consumption approximately by 20% to 90% than the original CPSFF. Simulation using Tanner Tool version with 250 nanometer technology. The power consumption is calculated by T Spice. The proposed work clock pair shared flip flop using MTCMOS technique is more efficient than all other designs. Key words MTCMOS technique, integrated circuit, CPSFF, CDMFF,CDFF, DEFF, power delay. I. INTRODUCTION To optimize the power consumption, many lowpower design techniques have been introduced, such as clock gating, power gating, creating multisupplyvoltage designs, dynamic voltage frequency scaling, and minimizing clock network. Among these techniques, minimizing clock network is very important in reducing power consumption of a SoC. Power has become a big issue in modern VLSI design. FlipFlop is an electronic circuit that is used to store a logical state of any data input signals with the response to a clock pulse. Flipflops are widely used to receive and maintain data in selected sequences during recurring clock intervals for a limited time period sufficient for other circuits within a system. A huge portion of the onchip power is consumed by clock systems, which consists of timing elements such as flipflops, latches and clock distribution network. These clock systems have redundant transition and the transition probability of the clock is 100% while an ordinary logic has onethird on average so clock systems are one of the most power consuming components in a VLSI system.these components consume 30% to 60% of the total power dissipation in 2.1a system Consequently, reduction in the power consumed by flipflops will show a deep impact on the total power consumed. Several techniques as well as various flipflops have been proposed recently to reduce redundancy in clock system. There are many flipflops given in the literature. II. RELATED WORKS 301
2 A. Double edge triggered flip flop(deff) Figure 1.2 Conditional discharge flipflop Figure 1.1 Double edge triggered flip flop Figure 1.1 shows that double edge triggered flip flop. Data sampling is done on both the rising and the falling edge of the clock signals by Double Edge triggered Flip Flop (DEFF)[1]. It has the same number of transistors as that of the conventional Single Edge triggered FlipFlop (SEFF). Reduction of the frequency to half in case of DEFF results in abatement of the power dissipation to approximately half of the value of SEFF. B. Conditional discharge flipflop(cdff) Figure 1.2 shows that the conditional discharge flip flop. CDFF operates in two stages. The first stage is mainly for the LOW to HIGH transition, and the second stage for HIGH to LOW transition. CDFF uses a pulse generator which eventually generates the pulses for implementing the circuit in double edge triggered technology. The discharge path of the first stage helps in preventing evaluation in the coming clock cycles as long as input remain stable level 1 C. Conditional Data Mapping Flip Flop(CDMFF) Figure 1.3 shows that the conditional data mapping flip flop. CDMFF uses only 7 clocked transistors.when compare with CDFF which uses 13clocked transistors [2] resulting in reduction of the power consumption. The conditional data mapping (CDM) methodology exploits the property of the flipflop, by providing the flipflop with a stage to map its inputs to (0, 0) if a redundant event is predicted, such that the outputs will be unchanged when clock signal is triggered. The CDMFF has the floating node problem. The input for conditional data mapping flip flop is D and clock, and the output is Q. 302
3 7 clocked transistors shown in Figure (1.3). Hence reducing the clock load. In CPSFF the clocked pair is shared by the first and second stage. The always on pmos in CPSFF allows the internal node to be always connected to Vdd thus prevents the floating problem. Thus in terms of power consumption of clock circuit CPSFF is high efficient than CDMFF. Figure 1.3 Conditional Data Mapping FlipFlop III.PROPOSED SYSTEM The main focus of this work is on minimizing the power consumption in any internal circuit. So that multi threshold CMOS (MTCMOS) technique is used with the clocked pair shared flip flop for reducing the power consumption. D. Clocked Pair Shared Flip Flop(CPSFF) Figure 1.5 Power gating technique using MTCMOS. Figure 1.4 Clocked Pair Shared FlipFlop Figure 1.4 shows that the clocked pair shared flip flop. The CPSFF overcomes the problem of floating node in CDMFF by reducing the number of clocked transistors. CPSFF uses 4 clocked transistors while comparing with CDMFF which uses The figure 1,5 shows that the power gating technique using MTCMOS. The diagram consists of two sleep transistors S1 and S2 with higher V. The logic circuit between the S1 and S2 is not directly connected to real supply lines V dd and G nd. but in turn it is connected to virtual power supply lines Vdd v and Gnd v and has low V. Both the sleep transistors are given complementary inputs S and SBAR. The circuit operates in two modes active mode and standby mode. In active mode, S=0 and SBAR=1 such that S1 and S2 are ON and virtual supply lines Vdd and Gnd work as real supply lines therefore the logic circuit operates normally and at t higher speed. 303
4 In sleep mode, S=1 and SBAR=0 such that S1 And S2 are OFF and this will cause virtual power supply lines to float and large leakage current present in circuit is suppressed by sleep transistors S1 and S2 resulting in lower leakage current and thus reducing power consumption. The figure 1.6 shows that the schematic diagram of CPSFF using MTCMOS technique[3]. The flip flop works, when both clk and clkdb are at logic 1. Pseudo nmos and conditional mapping technique both are combined using the above scheme. The nmos M3 is controlled by a feedback signal. For input D=1and S=1,Q will be high, switching ON the transistor M8, and turning OFF M3 thus parrying redundant switching activity and flow of short circuit current at the node X. the flip flop depends upon the state previously acquired by Q and QB along with the clock and the data signal inputs provided. IV. RESULT ANALYSIS The below table is shows the power analysis for various flip flop. The inputs are 1.5v, 3.3v and 5v.which is calculated in watts. The power analysis is calculated in different temperature. While comparing the various flip flop like, DEFF, CDFF, CMFF,CPSFF,MTCPSFF. The MTCPSFF consume least power then the other flip flop. Table 1 Comparison of power analysis for Dflipflops. The MTCPSFF waveform is shown below, D is the input and Q is the output, clock is also the input. Figure1.6 Schematic of Proposed CPSFF using MTCMOS. When D transits to 1 the output Q is pulled up by pmos M2 whereas M4 is used to pull down Q when D=0 and Y=1 at the arrival of clock pulse. When the input D transits from 01 the shortcircuit occurs for once even though M1 is always ON, thus disconnecting the discharge path and turning off M3 after two gates delay by feedback signal. There will be no shortcircuiting even if the input D stays high as M3 disconnects the discharge path. The output of Figure 5.5 Output waveform of MTCPSFF 304
5 Table 1.1 Power analysis Design name Temperature = 25 C Power consumption (in watts) 27 C 1.5v 3.3v 5v 1.5v 3.3v 5v CDFF 3.309x x x x x x10  DEFF x x x x x x10  CDMFF x x x x x x10  CPSFF x x x x x x10  MTCMOS x x x x x x10  V.CONCLUSION The existing clocked pair shared flip flop using MTCMOS reduces local clock transistor number and power consumption as well. The proposed MT CPSFF has given better result than the previously existing DEFF, CDFF, CDMFF and CPSFF in terms of power and good output response by approximately 20% to 90%. Furthermore, several low power techniques, including Forced stack technique, can be explored to incorporate into the new flipflop to build system. VII. FUTURE ENHANCEMENT The work will be extended by using Forced stack technique for reducing power consumption in D flipflop and can be implemented in any one of the applications. Further the work can be extended in reducing the number of transistors in MTCMOS Clock Pair Shared Flipflop. VI. ACKNOWLEDGMENT I thank my teachers for their continuous support and encouragement in this work, for cultivating new and aspiring ideas in my mind. I would especially thank to my friends and Mr. K.Venkatesan, Assistant Professor, for guiding through the process. VIII.REFERENCES [1] Pedram.M, Wu.Q, and Wu.X,(Jan.2002) A new Design for Double Edge Triggered Flipflops. [2] The.C.K, Hamada.M, Fujita.T,Hara.H, Ikumi.N, 305
6 and Oowaki.Y,(December 2006) Conditional Data Mapping FlipFlops for LowPower and HighPerformance Systems.IEEE Transactions on very largescale integration (VLSI) systems, vol. 14, no. 12. [3] Zhou.Q, Zhao.X, Cai.Y, Hong.X(2), An MTCMOS technology for lowpower physical design, Integration VLSI J. [4] Kavitha.T, Dr.Sumalatha.V, (2012. ) A New Reduced Clock Power Flip flop for Future SOC Applications.International Journal of Computer Trends and Technology,volume3 Issue4. [5] Weste.N and Harris.D (2), CMOS VLSI Design. Reading, MA: Addison Wesley. [6] F. Mohammad, L. A. Abhilasand P.Srinivas A new parallel counter architecture with reduced transistor count for power and area optimization, international conferenceon Electrical and Electronics Engineering, Sept., [7] HemanthaS, Dhawan A and Kar H, Multithreshold CMOS design for low power digital circuits, TENCON 22 IEEE Region 10 Conference, pp.15,
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