DESIGN AND IMPLEMENTATION OF MULTI-BIT FLIP FLOP FOR DIGITAL CIRCUITS

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1 DESIGN AND IMPLEMENTATION OF MULTI-BIT FLIP FLOP FOR DIGITAL CIRCUITS K. HEMA LATHA (1), DR. A.SUBBA RAO (2) M.Tech., Electronic Design Technology,SR Engineering College (1) Assoc.prof.,Dept.of ECE, SR Engineering College (2) Abstract Power has become a burning issue in modern VLSI design. In modern integrated circuits, the power consumed by clocking gradually takes a dominant part. If a design is given, power consumption can be reduced by replacing some flip-flops with fewer multi-bit flip-flops. However, this procedure may affect the performance of the original circuit. Hence, the flipflop replacement without timing and placement capacity constraints violation becomes a quite complex problem. We have mentioned several techniques, to deal with the difficulty efficiently. Finally, a hierarchical way is used to merge flip-flops. Besides power reduction, the objective of minimizing the total wire length is also considered. According to the experimental results, our design significantly reduces clock power and the running time is very short. In the largest test case, which contains large flip-flops, this design can be used to replace flip-flops and the power reduction can be reduced. Index Terms Clock power reduction, merging, multi-bit flip-flop, replacement, wire length. I. Introduction Optimization in VLSI has been done on three factors: Area, Power and Timing (Speed).Reducing the space of logic which occupy on the die is known as Area Optimization. This is done in both front-end and back-end of design. In front-end design, proper description of simplified Boolean expression and removing unused states will lead to minimize the gate/transistor utilization. But in back-end of the design, Floor planning, Placement, and Routing are performed which is done by CAD tool. The CAD tool has a specific algorithm for each process to produce an area efficient design similar to Power optimization. Reducing the power dissipation of the design which suffers by operating voltage, operating frequency, and switching activity is known as Power Optimization. The first two factors are merely specified in design constraints but switching activity is a parameter which varies dynamically, based on the way that designs the logic and input vectors. Timing optimization or speed of the design refers to meeting the user constraints in efficient manner without any violation otherwise, improving performance of the design. High performance designs are achieved by proper placement, routing and sizing the element. The word optimization is approached in different ways by merging, instead of sizing the memory element. Some of the basic ideas of timing optimization approach are (a) Circuit re- synthesis (b) gate resizing and (c) Circuit reposition as given in paper [1]. II. Related Work The idea of designing the multi-bit flip-flop arises for power considerations and placement rout-ability effectiveness. Some of them are discussed here: Minimization of dynamic clock power leads the way to merge the single-bit flipflops and constructed Multi-Bit Flip-Flops. This merging process also has to satisfy the certain area constraint which decreases the total flip-flop area in synchronous design as discussed in paper[2]. As given in paper [3],the clock power by congested constraints of unallocated bins and the length of constraints of the input and output signals of all the 1-bit flip-flop. Here redundant inverters in merging of single-bit flip-flop are eliminated. The multi-bit flip-flops are mostly viewed as low power design technique, MBFFs with larger bit numbers as possible to gain more clock power saving but larger bit number may lead to severe crosstalk s due to close interconnecting wires as discussed in paper [4].

2 A clustering and placement is done by reducing the interconnect wire length. Merging of Flip-Flop is done through library that perform a coordinate transformation to identify those flip-flops that can be merged and their legal regions. This approach reduces the wire length considerably as given in the paper [5] and paper [6]. a short circuit line. Fig 2 shows an example of merging two 1-bit flip-flops into one 2-bit flip-flop. Each 1-bit flip-flop contains two inverters, masterlatch and slave-latch. The Digital design uses the single-bit Flip Flop for memory applications and controller design. D flip flops are implemented in two ways which are Master-Slave latch pair and pulse-triggered latches. Most of the design involving standard cell follows Master-Slave approach because of the restricted timing constraints of pulse triggered latches. In master-slave approach, two latches are connected in serial manner with complementary clock signal in serial manner with complementary clock signal as given in paper [8]. III. Concept of Multi bit Flip-flop Consider a single bit flip-flop which has a single input and an output with a clock signal. Fig 1 shows an example of single-bit flip-flop. A single-bit flipflop has two latches (Master latch and slave latch). Fig 2: An example of merging two 1-bit flip-flops into one 2-bit flip-flop. Therefore only two clock buffers are used in MBFF for one 2- bit flip-flop rather than four clock buffers. Hence by merging single-bit flip-flops into one multibit flip-flop, duplicate inverters can be avoided or Hence number of inverters can be avoided. It lowers the total clock dynamic power consumption. By this way, the total area contributing to flip-flops can also be reduced. IV. Proposed system Fig 1: Single-Bit Flip-Flop The latches need Clk and Clk 1. Signals to Perform the operations, such as shown in the fig 1.In order to have better delay from Clk Q, we will regenerate Clk from Clk 1. Hence, two inverters are required in the clock path. The operation is whenever the Clk is high with any input value, the master latch works as a black box or it does not work and the input passes to the slave latch since it acts as This proposed method is based on the idea of merging clock pulse as given in paper [6]. The working of single-bit D flip flop is similar to the D latch except that the output of D Flip Flop takes the state of the D input at the moment of a positive edge at the clock pin (or negative edge if the clock input is active low) and delays it by one clock cycle. That's why, it is commonly known as delay flips flop. The D Flip-Flop can be interpreted as a delay line or zero order hold. The advantage of the D flip-flop over the

3 D-type "transparent latch" is that the signal on the D input pin is captured the moment the flip-flop is clocked, and subsequent changes on the D input will be ignored until the next clock event. From the timing diagram in fig 3, it is clear that the output Q changes only at the positive edge as shown in paper [9]. At each positive edge the output Q becomes equal to the input Data at that instant and this value of Q is held until the next positive edge. Fig 5:Timing diagram for MBFF. Fig 3: Timing diagram for SBFF. Multi-bit Flip Flop which takes multiple data input and results in multiple data output. The working of multi-bit flip flop is same as single-bit flip flop, whenever the clock gets active state, flip flop latches all input to output. For inactive state the flip flop holds the data. The basic structure of multi-bit flip flop is given in fig 4 and its corresponding waveform is given in fig 5. Fig 4: MBFF Fig 6: Part of MBFF 32 schematic. This paper experimented the proposed technique by designing the Serial-In Serial-Out using SBFF and MBFF separately. Designing of SISO has two reasons:- SISO is basic sequential device and easy to analyze. Another one is pipelining. SISO of n-bit register is nothing n-stage pipeline for many application such as Serial Bit Communication. In this paper, both existing and proposed designs are analyzed using basic SISO sequential circuit. For existing system and proposed system, Serial in serial out circuits are constructed by SBFF and MBFF which are shown in fig 7 and fig 8 respectively. The operation is described as arrival of a clock pulse and

4 data at the D input of each flip-flop is transferred to its Q output. If a 1 is to the input of the first flip flop. Then upon the arrival of the fist clock pulse, this 1 is transferred to the output of flip-flop 1. After four clock pulses this 1 will be at the output of flip-flop 4. In this manner, a four bit number can be Stored in the register. After four more clock pulses, this data will be shifted out of the register. Hence two SBFF s can be combined in to single MBFF. Hence two MBFF S are enough instead of four SBFF s as shown in the figure 8. V. Simulation results The proposed MBFF is coded in Verilog HDL, simulated using Xilinx ISim simulator, synthesized using Xilinx XST for Spartan 3E: XC3S500E-4FG320 FPGA and verified for possible inputs given below. Inputs are generated using Verilog HDL test bench. The simulation result for MBFF is shown in the Figure 10. Fig 7: SISO using SBFF The output Q is generated after four clock cycles from four SBFF s. The output of SBFF1 is given as input to next SBFF and the process continues until the last SBFF4. Hence, after four clock cycles output is generated at Q. But when compared with MBFF, the SBFF requires two clock cycles to generate two output bits. In this way, area and power gets reduced since the number of flipflops are reduced. Fig 8: SISO using MBFF Fig 9: Schematic of MBFF-32bit.

5 Fig 11: Schematic of MBFF-32by16 Fig 10: Simulation Results of MBFF-32bit Fig 12: Simulation Results of MBFF-32by16 The schematic diagrams of MBFF are shown with their results. MBFF-32x16 is formed from two MBFF-16x8 s. In the above simulation, inputs are d0 to d31.the outputs are resulted from q0 to q31.the output changes along with the clock and input. Since it is a edge triggering flipflop, output changes only at the edge of clock. The output remains constant until next positive or depending on the type of edge triggering. When reset pin is zero, all the output values changes according to the input and clock. But when reset is one, the output values remain constant,until reset value changes. Our proposed technique reduces the designer s difficulty for analyzing all the flipflops for meeting the timing requirements. Some of the default parameter of FPGA such as default offset after out for clock, default period analysis are most probably fixed and those are not have much variation.

6 Fig 13: Comparison of SBFF and MBFF. From the above table, the letter I indicates SBFF and the letters II indicates MBFF. We can notice that from 4 bit to 32 bit flipflops, the values has changed drastically. Number of flipflops usage and clock buffer from 4,8,16,32 bit SBFF to 4,8,16,32 bit MBFF has also changed. Hence we can say that area got reduced by flipflop usage and power consumption reduced by clock power usage. For 32 bit SBFF Minimum input arrival time before clock: ns Maximum output required time after clock: 4.04 ns Memory usage: kilobytes Total power= watts For 32 bit MBFF Minimum input arrival time before clock: ns Maximum output required time after clock: 4.04 ns Memory usage: kilobytes Total power=5.665 watts The power for MBFF is calculated for a 32 bit MBFF. Actually the separate use of 32 SBFFs gives watts but by this merging process watts of power has been saved. Hence as said earlier this technique is also known as low power design technique. Experimental results are targeted to number of flip flop usage, delay and clock buffer. Flip flop area usage is minimized to a greater extent. Thus this proposed method is more suitable for reduction of hardware. By this we can say that it can be implemented in digital circuits widely. This MBFF is mostly used for temporary storage purposes like cache memory, SRAM, DRAM and also communication based SOC applications. VI.Conclusion To achieve reduced area, MBFF s are implemented by merging SBFF s for communication based SOC applications in order to achieve optimized area and power for performance improvement of system on chip(soc). Single bit flip flop and Multi bit flip flop are implemented to achieve reduced area. Various sizes of MBFF are implemented. This proposed method is implemented in Xilinx Virtex 5 FPGA family. References: [1] Wen-Ben Jone and Chen-Liang Fang, Timing Optimization by Gate Resizing and Critical Path Identification, Design Automation Conference,1993. [2] Zhi-Wei Chen and Jin-Tai Yan, Routability Driven Flip-Flop Merging Process for Clock Power Reduction,ComputerDesign(ICCD),IEEE,Internation al Conference, [3] Jin-Tai Yan and Zhi-Wei Chen, Construction of Constrained Multi-Bit Flip-Flops for Clock Power Reduction, Green Circuits and Systems (ICGCS) International Conference, [4] Chih-Cheng Hsu, Yao-Tsung Chang and Mark Po-Hung Lin, Crosstalk-Aware Power Optimization with Multi-Bit Flip-Flops, 17th Asia and South Pacific Design Automation Conference, [5] Mark Po-Hung Lin, Chih-Cheng Hsu, and YaoTsung Chang, Recent Research in Clock Power Saving with Multi-Bit Flip-Flops, Midwest Symposium on Circuits and Systems Conference IEEE, [6] Ya-Ting Shyu et. Al., Effective and Efficient Approach for Power Reduction by Using Muti-Bit Flip-Flops, IEEE transactions on very large scale integration systems, [7] Rostislav Dobkin, Ran Ginosar, and Avionam Kolody, Fast Asynchronous Shift Register forbitserial Communication,12th IEEE international

7 symposium on asynchronous circuits and systems,2006. [8] LI Xia Yu, JIA Song, LIU LiMin, WANG Yuan and ZHANG GangGang,Design of Novel, Semitransparent flip-flops for high speed and low powerapplication, science china Press and Springerverlag Berlin Heidelberg,2012. [9] Vladimir Stojanovic and Vojin G.Oklobdzija, Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low Power Systems,IEEE journal of solid-state circuits, vol 34,no-4,april 1999.

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