ECE 331 Digital System Design
|
|
|
- Camilla Patrick
- 7 years ago
- Views:
Transcription
1 ECE 331 Digital System Design State Reduction and Derivation Flip-Flop Input Equations (Lecture #23) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.
2 Sequential Circuit Design 1. Understand specifications 2. Draw state graph (to describe state machine behavior) 3. Construct state table (from state graph) 4. Perform state reduction (if necessary) 5. Assign a binary value to each state (state assignment) 6. Create state transition table 7. Select type of Flip-Flop to use 8. Derive Flip-Flop input equations and FSM output equation(s) 9. Draw circuit diagram Spring 2011 ECE Digital System Design 2
3 State Reduction Spring 2011 ECE Digital System Design 3
4 Equivalent States Two states, p and q, of a sequential logic circuit, are equivalent iff for every input X, the outputs are equal the next states are equivalent. λ(p, X) = λ(q, X) Specifies the output given the present state and the input δ(p, X) == δ(q, X) Specifies the next state given the present state and the input Note: the next states do not need to be equal, just equivalent. Spring 2011 ECE Digital System Design 4
5 Determination of Equivalent States a b iff d f and c h a d iff a d and c e Spring 2011 ECE Digital System Design 5
6 FSM Design: Mealy Example: Design a sequence detector. The circuit (again) is of the form: serial bit stream (input) output (serial bit stream) Spring 2011 ECE Digital System Design 6
7 Example: Sequence Detector (Mealy) The sequential circuit has one input (X) and one output (Z). It examines groups of four consecutive inputs and produces an output Z = 1 if the input sequence 0101 or 1001 occurs. The circuit resets after every four inputs. A typical input and output sequence is: X = Z = (time: ) Spring 2011 ECE Digital System Design 7
8 Example: Sequence Detector (Mealy) State Table Spring 2011 ECE Digital System Design 8
9 Example: Sequence Detector (Mealy) Eliminating Redundant States Spring 2011 ECE Digital System Design 9
10 Example: Sequence Detector Since states H and I have the same next states and the same outputs, there is no way of telling states H and I apart. We can replace I with H. Spring 2011 ECE Digital System Design 10
11 Example: Sequence Detector (Mealy) Reduced State Table Spring 2011 ECE Digital System Design 11
12 Example: Sequence Detector Reduced State Graph Spring 2011 ECE Digital System Design 12
13 State Reduction using an Implication Chart Spring 2011 ECE Digital System Design 13
14 State Reduction using an I.C. 1.Construct an Implication Chart which contains a square for each pair of states (i, j). 2.Compare each pair of rows in the State Table. If outputs for states i and j are different, put an X in the corresponding square of the I.C. If outputs for states i and j are the same, indicate the implied pairs in the corresponding square of the I.C. If outputs and next states for states i and j are the same, put a check in the corresponding square of the I.C. Spring 2011 ECE Digital System Design 14
15 State Reduction using an I.C. 3.If square i-j contains the implied pair m-n, and square m-n contains an X, then i<>j, and an X must be placed in the corresponding square of the I.C. 4.If X's were added in step 3, repeat step 3 until no more X's are added. 5.For each square i-j, which does not contain an X, i==j. Spring 2011 ECE Digital System Design 15
16 Example: State Reduction using an I.C. Spring 2011 ECE Digital System Design 16
17 Example: State Reduction using an I.C. Spring 2011 ECE Digital System Design 17
18 Example: State Reduction using an I.C. Spring 2011 ECE Digital System Design 18
19 Example: State Reduction using an I.C. After first pass. Spring 2011 ECE Digital System Design 19
20 Example: State Reduction using an I.C. After second pass. Spring 2011 ECE Digital System Design 20
21 Example: State Reduction using an I.C. d = = a e = = c d and e are removed from the State Table Spring 2011 ECE Digital System Design 21
22 Future site of another example. Spring 2011 ECE Digital System Design 22
23 Derivation of Flip-Flop Input Equations Spring 2011 ECE Digital System Design 23
24 Derivation of FF Input Equations 1. Assign a binary value to each state in the reduced state table (state assignment). 2. Construct the state transition table. Include in the state transition table, columns for the Flip-Flop inputs. 3. Construct the K-maps for the Flip-Flop inputs. 4. Derive the minimized FF input equations. Spring 2011 ECE Digital System Design 24
25 Derivation of FF Input Equations Example #1: Derive the Flip-Flop input equations for the following sequential logic circuit. Assume that D Flip-Flops are used in the design. Excitation Equation: D = Q + Spring 2011 ECE Digital System Design 25
26 Example #1: FF Input Equations State Table Spring 2011 ECE Digital System Design 26
27 Example #1: FF Input Equations 1. Assign a binary value to each state. 2. Construct the state transition table. A + B + C + D A D B D C Z ABC X = 0 X = 1 X = 0 X = 1 X = 0 X = Spring 2011 ECE Digital System Design
28 Example #1: FF Input Equations 3. Construct K-maps for Flip-Flop inputs. 4. Derive the minimized FF input equation. D A = D B = Spring 2011 ECE Digital System Design 28
29 Example #1: FF Input Equations 3. Construct K-maps for Flip-Flop inputs. 4. Derive the minimized FF input equation. D C = Spring 2011 ECE Digital System Design 29
30 Derivation of FF Input Equations Example #2: Derive the Flip-Flop input equations for the following sequential logic circuit. Assume that JK Flip-Flops are used in the design. Excitation Table: Q Q + J K x x 1 0 x x 0 Spring 2011 ECE Digital System Design 30
31 Example #2: FF Input Equations State Table Spring 2011 ECE Digital System Design 31
32 Example #2: FF Input Equations 1. Assign a binary value to each state. 2. Construct the state transition table. A + B + C + J A K A J B K B J C K C ABC X = 0 X = 1 X = 0 X = 1 X = 0 X = 1 X = 0 X = ECE Digital System Design 32
33 Example #2: FF Input Equations 3. Construct K-maps for Flip-Flop inputs. 4. Derive the minimized FF input equation. J A = K A = Spring 2011 ECE Digital System Design 33
34 Example #2: FF Input Equations 3. Construct K-maps for Flip-Flop inputs. 4. Derive the minimized FF input equation. J B = K B = Spring 2011 ECE Digital System Design 34
35 Example #2: FF Input Equations 3. Construct K-maps for Flip-Flop inputs. 4. Derive the minimized FF input equation. J C = K C = Spring 2011 ECE Digital System Design 35
36 Derivation of FF Input Equations Example #3: Derive the Flip-Flop input equations for the following sequential logic circuit. Assume that SR Flip-Flops are used in the design. Excitation Table: Q Q + S R x x 0 Spring 2011 ECE Digital System Design 36
37 Example #3: FF Input Equations State Table Spring 2011 ECE Digital System Design 37
38 Example #3: FF Input Equations 1. Assign a binary value to each state. 2. Construct the state transition table. A + B + S A R A S B S B AB X=00 X=01 X=11 X=10 X=00 X=01 X=11 X=10 X=00 X=01 X=11 X= Spring 2011 ECE Digital System Design 38
39 Example #3: FF Input Equations 3. Construct K-maps for Flip-Flop inputs. 4. Derive the minimized FF input equation. S A = R A = Spring 2011 ECE Digital System Design 39
40 Example #3: FF Input Equations 3. Construct K-maps for Flip-Flop inputs. 4. Derive the minimized FF input equation. S B = R B = Spring 2011 ECE Digital System Design 40
41 Questions? Spring 2011 ECE Digital System Design 41
Counters are sequential circuits which "count" through a specific state sequence.
Counters Counters are sequential circuits which "count" through a specific state sequence. They can count up, count down, or count through other fixed sequences. Two distinct types are in common usage:
ENEE 244 (01**). Spring 2006. Homework 5. Due back in class on Friday, April 28.
ENEE 244 (01**). Spring 2006 Homework 5 Due back in class on Friday, April 28. 1. Fill up the function table (truth table) for the following latch. How is this latch related to those described in the lectures
To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC.
8.1 Objectives To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC. 8.2 Introduction Circuits for counting events are frequently used in computers and other digital
Counters & Shift Registers Chapter 8 of R.P Jain
Chapter 3 Counters & Shift Registers Chapter 8 of R.P Jain Counters & Shift Registers Counters, Syllabus Design of Modulo-N ripple counter, Up-Down counter, design of synchronous counters with and without
Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng
Digital Logic Design Basics Combinational Circuits Sequential Circuits Pu-Jen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction
Lecture 8: Synchronous Digital Systems
Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered
Asynchronous Counters. Asynchronous Counters
Counters and State Machine Design November 25 Asynchronous Counters ENGI 25 ELEC 24 Asynchronous Counters The term Asynchronous refers to events that do not occur at the same time With respect to counter
Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa
Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation
Chapter 5. Sequential Logic
Chapter 5 Sequential Logic Sequential Circuits (/2) Combinational circuits: a. contain no memory elements b. the outputs depends on the current inputs Sequential circuits: a feedback path outputs depends
IE1204 Digital Design F12: Asynchronous Sequential Circuits (Part 1)
IE1204 Digital Design F12: Asynchronous Sequential Circuits (Part 1) Elena Dubrova KTH / ICT / ES dubrova@kth.se BV pp. 584-640 This lecture IE1204 Digital Design, HT14 2 Asynchronous Sequential Machines
Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012
Latches, the D Flip-Flop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR
Sequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements )
Sequential Logic (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential vs. Combinational Circuits Combinatorial circuits: their outputs are computed entirely from their present
Flip-Flops and Sequential Circuit Design. ECE 152A Winter 2012
Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6
Flip-Flops and Sequential Circuit Design
Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6
RAM & ROM Based Digital Design. ECE 152A Winter 2012
RAM & ROM Based Digital Design ECE 152A Winter 212 Reading Assignment Brown and Vranesic 1 Digital System Design 1.1 Building Block Circuits 1.1.3 Static Random Access Memory (SRAM) 1.1.4 SRAM Blocks in
Let s put together a Manual Processor
Lecture 14 Let s put together a Manual Processor Hardware Lecture 14 Slide 1 The processor Inside every computer there is at least one processor which can take an instruction, some operands and produce
DIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse.
DIGITAL COUNTERS http://www.tutorialspoint.com/computer_logical_organization/digital_counters.htm Copyright tutorialspoint.com Counter is a sequential circuit. A digital circuit which is used for a counting
Combinational Logic Design Process
Combinational Logic Design Process Create truth table from specification Generate K-maps & obtain logic equations Draw logic diagram (sharing common gates) Simulate circuit for design verification Debug
Lesson 12 Sequential Circuits: Flip-Flops
Lesson 12 Sequential Circuits: Flip-Flops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability
Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.
Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage
L4: Sequential Building Blocks (Flip-flops, Latches and Registers)
L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Prof. Randy Katz (Unified
Module 3: Floyd, Digital Fundamental
Module 3: Lecturer : Yongsheng Gao Room : Tech - 3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental
ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies
ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher Asynchronous Counter Operation
Digital Logic Design Sequential circuits
Digital Logic Design Sequential circuits Dr. Eng. Ahmed H. Madian E-mail: ahmed.madian@guc.edu.eg Dr. Eng. Rania.Swief E-mail: rania.swief@guc.edu.eg Dr. Eng. Ahmed H. Madian Registers An n-bit register
DIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department
Counters By: Electrical Engineering Department 1 Counters Upon completion of the chapter, students should be able to:.1 Understand the basic concepts of asynchronous counter and synchronous counters, and
Take-Home Exercise. z y x. Erik Jonsson School of Engineering and Computer Science. The University of Texas at Dallas
Take-Home Exercise Assume you want the counter below to count mod-6 backward. That is, it would count 0-5-4-3-2-1-0, etc. Assume it is reset on startup, and design the wiring to make the counter count
WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1
WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits
CHAPTER 11 LATCHES AND FLIP-FLOPS
CHAPTER 11 LATCHES AND FLIP-FLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop
Digital Electronics Part I Combinational and Sequential Logic. Dr. I. J. Wassell
Digital Electronics Part I Combinational and Sequential Logic Dr. I. J. Wassell Introduction Aims To familiarise students with Combinational logic circuits Sequential logic circuits How digital logic gates
Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters:
Design Eample: ers er: a sequential circuit that repeats a specified sequence of output upon clock pulses. A,B,C,, Z. G, O, T, E, R, P, S,!.,,,,,,,7. 7,,,,,,,.,,,,,,,,,,,. Binary counter: follows the binary
Digital Electronics Detailed Outline
Digital Electronics Detailed Outline Unit 1: Fundamentals of Analog and Digital Electronics (32 Total Days) Lesson 1.1: Foundations and the Board Game Counter (9 days) 1. Safety is an important concept
ECE380 Digital Logic
ECE38 igital Logic Flip-Flops, Registers and Counters: Flip-Flops r.. J. Jackson Lecture 25- Flip-flops The gated latch circuits presented are level sensitive and can change states more than once during
1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1.
File: chap04, Chapter 04 1. True or False? A voltage level in the range 0 to 2 volts is interpreted as a binary 1. 2. True or False? A gate is a device that accepts a single input signal and produces one
Chapter 8. Sequential Circuits for Registers and Counters
Chapter 8 Sequential Circuits for Registers and Counters Lesson 3 COUNTERS Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline Counters T-FF Basic Counting element State
DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: REGISTERS AND RELATED
DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 5. LECTURE: REGISTERS AND RELATED 2nd (Spring) term 22/23 5. LECTURE: REGISTERS. Storage registers 2. Shift
CpE358/CS381. Switching Theory and Logical Design. Class 10
CpE358/CS38 Switching Theory and Logical Design Class CpE358/CS38 Summer- 24 Copyright 24-373 Today Fundamental concepts of digital systems (Mano Chapter ) Binary codes, number systems, and arithmetic
ECE232: Hardware Organization and Design. Part 3: Verilog Tutorial. http://www.ecs.umass.edu/ece/ece232/ Basic Verilog
ECE232: Hardware Organization and Design Part 3: Verilog Tutorial http://www.ecs.umass.edu/ece/ece232/ Basic Verilog module ();
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.
Simplifying Logic Circuits with Karnaugh Maps
Simplifying Logic Circuits with Karnaugh Maps The circuit at the top right is the logic equivalent of the Boolean expression: f = abc + abc + abc Now, as we have seen, this expression can be simplified
Upon completion of unit 1.1, students will be able to
Upon completion of unit 1.1, students will be able to 1. Demonstrate safety of the individual, class, and overall environment of the classroom/laboratory, and understand that electricity, even at the nominal
Systems I: Computer Organization and Architecture
Systems I: omputer Organization and Architecture Lecture 8: Registers and ounters Registers A register is a group of flip-flops. Each flip-flop stores one bit of data; n flip-flops are required to store
CS311 Lecture: Sequential Circuits
CS311 Lecture: Sequential Circuits Last revised 8/15/2007 Objectives: 1. To introduce asynchronous and synchronous flip-flops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce
Counters and Decoders
Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4-bit ripple-through decade counter with a decimal read-out display. Such a counter
Design: a mod-8 Counter
Design: a mod-8 Counter A mod-8 counter stores a integer value, and increments that value (say) on each clock tick, and wraps around to 0 if the previous stored value was 7. So, the stored value follows
CDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012
CDA 3200 Digital Systems Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012 Outline SR Latch D Latch Edge-Triggered D Flip-Flop (FF) S-R Flip-Flop (FF) J-K Flip-Flop (FF) T Flip-Flop
BINARY CODED DECIMAL: B.C.D.
BINARY CODED DECIMAL: B.C.D. ANOTHER METHOD TO REPRESENT DECIMAL NUMBERS USEFUL BECAUSE MANY DIGITAL DEVICES PROCESS + DISPLAY NUMBERS IN TENS IN BCD EACH NUMBER IS DEFINED BY A BINARY CODE OF 4 BITS.
Engr354: Digital Logic Circuits
Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flip-flops;
DEPARTMENT OF INFORMATION TECHNLOGY
DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF INFORMATION TECHNLOGY Lab Manual for Computer Organization Lab ECS-453
Binary Adders: Half Adders and Full Adders
Binary Adders: Half Adders and Full Adders In this set of slides, we present the two basic types of adders: 1. Half adders, and 2. Full adders. Each type of adder functions to add two binary bits. In order
Layout of Multiple Cells
Layout of Multiple Cells Beyond the primitive tier primitives add instances of primitives add additional transistors if necessary add substrate/well contacts (plugs) add additional polygons where needed
Chapter 7. Registers & Register Transfers. J.J. Shann. J. J. Shann
Chapter 7 Registers & Register Transfers J. J. Shann J.J. Shann Chapter Overview 7- Registers and Load Enable 7-2 Register Transfers 7-3 Register Transfer Operations 7-4 A Note for VHDL and Verilog Users
DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute. 2nd (Spring) term 2012/2013
DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 4. LECTURE: COUNTERS AND RELATED 2nd (Spring) term 2012/2013 1 4. LECTURE: COUNTERS AND RELATED 1. Counters,
CSE140: Components and Design Techniques for Digital Systems
CE4: Components and esign Techniques for igital ystems Tajana imunic osing ources: Where we are now What we ve covered so far (Chap -5, App. A& B) Number representations Boolean algebra OP and PO Logic
Sequential Logic Design Principles.Latches and Flip-Flops
Sequential Logic Design Principles.Latches and Flip-Flops Doru Todinca Department of Computers Politehnica University of Timisoara Outline Introduction Bistable Elements Latches and Flip-Flops S-R Latch
Napier University. School of Engineering. Electronic Engineering A Module: SE42205 Digital Design
Napier University School of Engineering Digital Design Clock + U1 out 5V "1" "2" "4" JK-FF D JK-FF C JK-FF B U8 SN7408 signal U4 SN74107 U5 SN74107 U6 SN74107 U3 SN7408 U2 J Q J Q & J Q & K CQ K CQ K CQ
Cascaded Counters. Page 1 BYU
Cascaded Counters Page 1 Mod-N Counters Generally we are interested in counters that count up to specific count values Not just powers of 2 A mod-n counter has N states Counts from 0 to N-1 then rolls
EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/20 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,
Finite State Machine Design and VHDL Coding Techniques
Finite State Machine Design and VHDL Coding Techniques Iuliana CHIUCHISAN, Alin Dan POTORAC, Adrian GRAUR "Stefan cel Mare" University of Suceava str.universitatii nr.13, RO-720229 Suceava iulia@eed.usv.ro,
(1) /30 (2) /30 (3) /40 TOTAL /100
Your Name: SI Number: UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY AVIS IRVINE LOS ANGELES RIVERSIE SAN IEGO SAN FRANCISCO epartment of Electrical Engineering and Computer Sciences SANTA BARBARA SANTA
Finite State Machine. RTL Hardware Design by P. Chu. Chapter 10 1
Finite State Machine Chapter 10 1 Outline 1. Overview 2. FSM representation 3. Timing and performance of an FSM 4. Moore machine versus Mealy machine 5. VHDL description of FSMs 6. State assignment 7.
The components. E3: Digital electronics. Goals:
E3: Digital electronics Goals: Basic understanding of logic circuits. Become familiar with the most common digital components and their use. Equipment: 1 st. LED bridge 1 st. 7-segment display. 2 st. IC
Gray Code Generator and Decoder by Carsten Kristiansen Napier University. November 2004
Gray Code Generator and Decoder by Carsten Kristiansen Napier University November 2004 Title page Author: Carsten Kristiansen. Napier No: 04007712. Assignment title: Design of a Gray Code Generator and
BOOLEAN ALGEBRA & LOGIC GATES
BOOLEAN ALGEBRA & LOGIC GATES Logic gates are electronic circuits that can be used to implement the most elementary logic expressions, also known as Boolean expressions. The logic gate is the most basic
Lecture 12: More on Registers, Multiplexers, Decoders, Comparators and Wot- Nots
Lecture 12: More on Registers, Multiplexers, Decoders, Comparators and Wot- Nots Registers As you probably know (if you don t then you should consider changing your course), data processing is usually
LAB #4 Sequential Logic, Latches, Flip-Flops, Shift Registers, and Counters
LAB #4 Sequential Logic, Latches, Flip-Flops, Shift Registers, and Counters LAB OBJECTIVES 1. Introduction to latches and the D type flip-flop 2. Use of actual flip-flops to help you understand sequential
Topics of Chapter 5 Sequential Machines. Memory elements. Memory element terminology. Clock terminology
Topics of Chapter 5 Sequential Machines Memory elements Memory elements. Basics of sequential machines. Clocking issues. Two-phase clocking. Testing of combinational (Chapter 4) and sequential (Chapter
Modeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit
Modeling Sequential Elements with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 4-1 Sequential Circuit Outputs are functions of inputs and present states of storage elements
Register File, Finite State Machines & Hardware Control Language
Register File, Finite State Machines & Hardware Control Language Avin R. Lebeck Some slides based on those developed by Gershon Kedem, and by Randy Bryant and ave O Hallaron Compsci 04 Administrivia Homework
CHAPTER 3 Boolean Algebra and Digital Logic
CHAPTER 3 Boolean Algebra and Digital Logic 3.1 Introduction 121 3.2 Boolean Algebra 122 3.2.1 Boolean Expressions 123 3.2.2 Boolean Identities 124 3.2.3 Simplification of Boolean Expressions 126 3.2.4
Memory Elements. Combinational logic cannot remember
Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic
6.02 Fall 2012 Lecture #5
6.2 Fall 22 Lecture #5 Error correction for linear block codes - Syndrome decoding Burst errors and interleaving 6.2 Fall 22 Lecture 5, Slide # Matrix Notation for Linear Block Codes Task: given k-bit
DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute
DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 2. LECTURE: ELEMENTARY SEUENTIAL CIRCUITS: FLIP-FLOPS 1st year BSc course 2nd (Spring) term 2012/2013 1
7. Latches and Flip-Flops
Chapter 7 Latches and Flip-Flops Page 1 of 18 7. Latches and Flip-Flops Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one bit of information. The
(Refer Slide Time: 00:01:16 min)
Digital Computer Organization Prof. P. K. Biswas Department of Electronic & Electrical Communication Engineering Indian Institute of Technology, Kharagpur Lecture No. # 04 CPU Design: Tirning & Control
CHAPTER 11: Flip Flops
CHAPTER 11: Flip Flops In this chapter, you will be building the part of the circuit that controls the command sequencing. The required circuit must operate the counter and the memory chip. When the teach
PROGRAMMABLE LOGIC CONTROLLERS Unit code: A/601/1625 QCF level: 4 Credit value: 15 OUTCOME 3 PART 1
UNIT 22: PROGRAMMABLE LOGIC CONTROLLERS Unit code: A/601/1625 QCF level: 4 Credit value: 15 OUTCOME 3 PART 1 This work covers part of outcome 3 of the Edexcel standard module: Outcome 3 is the most demanding
Reliability Applications (Independence and Bayes Rule)
Reliability Applications (Independence and Bayes Rule ECE 313 Probability with Engineering Applications Lecture 5 Professor Ravi K. Iyer University of Illinois Today s Topics Review of Physical vs. Stochastic
Honors Class (Foundations of) Informatics. Tom Verhoeff. Department of Mathematics & Computer Science Software Engineering & Technology
Honors Class (Foundations of) Informatics Tom Verhoeff Department of Mathematics & Computer Science Software Engineering & Technology www.win.tue.nl/~wstomv/edu/hci c 2011, T. Verhoeff @ TUE.NL 1/20 Information
Gates, Circuits, and Boolean Algebra
Gates, Circuits, and Boolean Algebra Computers and Electricity A gate is a device that performs a basic operation on electrical signals Gates are combined into circuits to perform more complicated tasks
One-Way ANOVA using SPSS 11.0. SPSS ANOVA procedures found in the Compare Means analyses. Specifically, we demonstrate
1 One-Way ANOVA using SPSS 11.0 This section covers steps for testing the difference between three or more group means using the SPSS ANOVA procedures found in the Compare Means analyses. Specifically,
Sequential Circuit Design
Sequential Circuit Design Lan-Da Van ( 倫 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2009 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines
CHAPTER IX REGISTER BLOCKS COUNTERS, SHIFT, AND ROTATE REGISTERS
CHAPTER IX-1 CHAPTER IX CHAPTER IX COUNTERS, SHIFT, AN ROTATE REGISTERS REA PAGES 249-275 FROM MANO AN KIME CHAPTER IX-2 INTROUCTION -INTROUCTION Like combinational building blocks, we can also develop
MICROPROCESSOR. Exclusive for IACE Students www.iace.co.in iacehyd.blogspot.in Ph: 9700077455/422 Page 1
MICROPROCESSOR A microprocessor incorporates the functions of a computer s central processing unit (CPU) on a single Integrated (IC), or at most a few integrated circuit. It is a multipurpose, programmable
Computer Systems Structure Main Memory Organization
Computer Systems Structure Main Memory Organization Peripherals Computer Central Processing Unit Main Memory Computer Systems Interconnection Communication lines Input Output Ward 1 Ward 2 Storage/Memory
Course Requirements & Evaluation Methods
Course Title: Logic Circuits Course Prefix: ELEG Course No.: 3063 Sections: 01 & 02 Department of Electrical and Computer Engineering College of Engineering Instructor Name: Justin Foreman Office Location:
Decimal Number (base 10) Binary Number (base 2)
LECTURE 5. BINARY COUNTER Before starting with counters there is some vital information that needs to be understood. The most important is the fact that since the outputs of a digital chip can only be
Flip-Flops, Registers, Counters, and a Simple Processor
June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 Flip-Flops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number
Master/Slave Flip Flops
Master/Slave Flip Flops Page 1 A Master/Slave Flip Flop ( Type) Gated latch(master) Gated latch (slave) 1 Gate Gate GATE Either: The master is loading (the master in on) or The slave is loading (the slave
Writing Assignment #2 due Today (5:00pm) - Post on your CSC101 webpage - Ask if you have questions! Lab #2 Today. Quiz #1 Tomorrow (Lectures 1-7)
Overview of Computer Science CSC 101 Summer 2011 Main Memory vs. Auxiliary Storage Lecture 7 July 14, 2011 Announcements Writing Assignment #2 due Today (5:00pm) - Post on your CSC101 webpage - Ask if
COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design
PH-315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits
Copyright Peter R. Rony 2009. All rights reserved.
Experiment No. 1. THE DIGI DESIGNER Experiment 1-1. Socket Connections on the Digi Designer Experiment No. 2. LOGIC LEVELS AND THE 7400 QUADRUPLE 2-INPUT POSITIVE NAND GATE Experiment 2-1. Truth Table
2014 HSC Software Design and Development Marking Guidelines
014 HSC Software Design and Development Marking Guidelines Section I Multiple-choice Answer Key Question Answer 1 B A A 4 D 5 A 6 D 7 A 8 B 9 C 10 D 11 B 1 B 1 A 14 A 15 B 16 D 17 C 18 C 19 D 0 D 1 Section
Lecture-3 MEMORY: Development of Memory:
Lecture-3 MEMORY: It is a storage device. It stores program data and the results. There are two kind of memories; semiconductor memories & magnetic memories. Semiconductor memories are faster, smaller,
INTRODUCTION TO DIGITAL SYSTEMS. IMPLEMENTATION: MODULES (ICs) AND NETWORKS IMPLEMENTATION OF ALGORITHMS IN HARDWARE
INTRODUCTION TO DIGITAL SYSTEMS 1 DESCRIPTION AND DESIGN OF DIGITAL SYSTEMS FORMAL BASIS: SWITCHING ALGEBRA IMPLEMENTATION: MODULES (ICs) AND NETWORKS IMPLEMENTATION OF ALGORITHMS IN HARDWARE COURSE EMPHASIS:
SEQUENTIAL CIRCUITS. Block diagram. Flip Flop. S-R Flip Flop. Block Diagram. Circuit Diagram
SEQUENTIAL CIRCUITS http://www.tutorialspoint.com/computer_logical_organization/sequential_circuits.htm Copyright tutorialspoint.com The combinational circuit does not use any memory. Hence the previous
MATRIX ALGEBRA AND SYSTEMS OF EQUATIONS. + + x 2. x n. a 11 a 12 a 1n b 1 a 21 a 22 a 2n b 2 a 31 a 32 a 3n b 3. a m1 a m2 a mn b m
MATRIX ALGEBRA AND SYSTEMS OF EQUATIONS 1. SYSTEMS OF EQUATIONS AND MATRICES 1.1. Representation of a linear system. The general system of m equations in n unknowns can be written a 11 x 1 + a 12 x 2 +
Chapter 9 Latches, Flip-Flops, and Timers
ETEC 23 Programmable Logic Devices Chapter 9 Latches, Flip-Flops, and Timers Shawnee State University Department of Industrial and Engineering Technologies Copyright 27 by Janna B. Gallaher Latches A temporary
Chapter 4 Register Transfer and Microoperations. Section 4.1 Register Transfer Language
Chapter 4 Register Transfer and Microoperations Section 4.1 Register Transfer Language Digital systems are composed of modules that are constructed from digital components, such as registers, decoders,
A New Paradigm for Synchronous State Machine Design in Verilog
A New Paradigm for Synchronous State Machine Design in Verilog Randy Nuss Copyright 1999 Idea Consulting Introduction Synchronous State Machines are one of the most common building blocks in modern digital