AN4619 Application note

Transcription

1 Application note STLC2690 PCB layout guideline Introduction This application note provides a guideline for PCB implementation of the STCL2690 in a typical mobile handset. This guideline is essential to achieve optimal performance of the STLC2690, described in [1]. Purpose The purpose is to give general instructions to CAD (PCB layout) engineers regarding how to incorporate the STLC2690 (housed in a WLCSP61R8 package) in a final application design (mobile handset). Scope This note provides generic guidelines for STLC2690 integration on a representative PCB stackup. The recommendations are based on current knowledge of how to achieve the desired performance of the STLC2690. The layout of the rest of the PCB could have an impact on the Bluetooth part, so these recommendations should be used as a guideline and complemented by the experience of the designer. Audience RF application engineers, CAD engineers and other STLC2690 customers. December 2014 DocID Rev 1 1/17

2 Contents AN4619 Contents 1 General information Electrical schematics Target PCB stackup Component placement Layout rules Bluetooth RF interface Balanced part Unbalanced part FM-RX RF front-end FM-TX RF interface Ground connection RF ground connection Analog ground connection FM ground connection Digital ground connection Decoupling and compensation capacitors ground connection Power supply distribution Other signals Reference clock High speed digital interfaces Other signals References Appendix A STLC2645 PCB implementation Revision history /17 DocID Rev 1

3 General information 1 General information 1.1 Electrical schematics The electrical circuitry around the STLC2690 must be completed based on the STLC2690 datasheet and platform requirements, taking into account the particularities of the modes, interfaces and features described in [2]. This application note is based on the reference application schematic presented in [1]. As additional information, the electrical schematic as implemented in the STLC2645_Rev 3.0 reference design is presented in the diagrams below. Figure 1: STLC2690 electrical schematic: main signal part Figure 2: STLC2690 electrical schematic: FM transceiver part DocID Rev 1 3/17

4 General information Figure 3: STLC2690 electrical schematic: power supply and ground connection AN Target PCB stackup In order to use all the features and all interfaces of the STLC2690, 3 PCB layers are required for routing including the top layer, while a solid ground plane can be located from 4th layer onwards. The minimum PCB stackup must permit: Pads for the WLCSP package with 0.4 mm pitch on 1st layer (typical pad size 0.25 mm diameter) Minimum trace width of 0.06 mm on inner layers Layer interconnect microvias between the 1st and 2nd layers, as well as between the 2nd and 3rd layers More than 3 layers with microvias are allowed It is preferred to have stacked microvias with copper fill Buried vias Dielectric materials and thicknesses between metal layers are not critical, but should permit RF microstrip lines and striplines with 50 Ω characteristic impedance. The target 6-layer PCB stackup example is presented in Figure 4: "Target PCB stackup example". The PCB stackup for dedicated platforms can be different in view of layer count, metal and dielectric thickness, and relative position of the solid ground plane layer. However it has to respect the minimum requirements, as mentioned previously. If some features and interfaces of the STLC2690 are not used in the final application, the PCB layout may be significantly simplified. It may allow the use of only two layers for routing with the ground layer on the 3rd layer. 4/17 DocID Rev 1

5 Figure 4: Target PCB stackup example General information 1.3 Component placement The recommended component placement is presented in Figure 5: "Component placement" below. All components must be placed on the same side of the PCB. Figure 5: Component placement Compensation capacitors C1-C4 must be placed near the corresponding pin of the STLC2690. The balanced BPF must be placed in such a way that the RF terminals of FL1 are symmetrically opposite to the RF terminals of the STLC2690. In case a balun is used instead of a balanced BPF, the same rule applies. Placement of FM-RX front-end components (L1, L2, C6-C8) may be further optimised if the FM-TX feature of the DocID Rev 1 5/17

6 General information AN4619 STLC2690 is not used. As an alternative, FM-RX front-end components (L1, L2, C6-C8) can be placed near the FM antenna PCB connection. This alternative option is more recommended if the FM antenna PCB connection is greater than ~20 mm from the STLC2690. In this case, any side of the PCB can be used for placement of the FM-RX front end components. 6/17 DocID Rev 1

7 Layout rules 2 Layout rules 2.1 Bluetooth RF interface Balanced part The PCB layout of the Bluetooth RF interface in the balanced parts involves connection to ground (pins A8, D8, B7 and C7 of the STLC2690, pins 4, 5 and 8 of the balanced BPF. May be referred to as GND_RF) and the differential RF port (pins B8, C8 of the STLC2690 and pins 6, 7 of the BPF). Each ground pin A8, D8, B7 and C7 of the STLC2690 should be connected through microvias to the ground plane on layer 2 and further. There should be at least 3 buried vias placed nearby: one as close as possible to pin A8, one to pin D8 and one connected to pins C7 and B7. Another 3 buried vias should be placed close to the BPF (pins 4, 8 and one in the center). These vias should be connected to layer 1 with the help of microvias. It is absolutely necessary to provide good ground connections between pins A8 and D8 of the STLC2690, and pins 4, 5, 8 of the BPF on layer 1. Ground pins A8, D8, B7 and C7 of the STLC2690 should also be connected to each other on layer 1. An example of the layout is presented in Figure 6: "BT RF layout example: balanced part", (layers 1 and 2 are shown). Figure 6: BT RF layout example: balanced part DocID Rev 1 7/17

8 Layout rules AN4619 Differential RF port connection (pins B8, C8 of the STLC2690 and pins 6, 7 of the BPF) should be made in accordance with the following rules: Each of two RF traces is a microstrip line with 50 Ω characteristic impedance. Characteristic impedance tolerance of ±10% is recommended. In no case should characteristic impedance be more than 20% from nominal. Despite the differential nature of the STLC2690 RF port, those RF traces should be treated as single-ended. However, traces must be routed symmetrically to each other. Recommended electrical length of RF traces is 3º 2.45 GHz, the maximum allowed electrical length is 2.45 GHz. This roughly corresponds to mm typical and 1.0 mm maximum mechanical length. Reference ground on layers 2 or 3 may be used for these traces depending on PCB dielectric thickness. The goal is to achieve trace width in the range of 0.2 to 0.3 mm, corresponding to 50 Ω characteristic impedance. Trace width less than 0.1 mm and greater than 0.35 should be avoided. In cases where layer 3 is used as reference ground for RF traces, an opening in GND_RF on layer 2 should be made. This opening must repeat the inner ground shape as on 1st layer, but maintaining the connection in between under pins A8 and D8 of the STLC2690. Bending of RF traces more than 45º is not allowed. The explanation and rules above are given for the BT RF interface with balanced BPF. If just a balun is used, the same principles apply Unbalanced part The unbalanced part of BT RF interface involves RF connection between balanced BPF and antenna or between balun and WLAN FEM. In both cases connection must be done according to the following rules: RF trace may be implemented as a microstrip line, coplanar waveguide or stripline with 50 Ω characteristic impedance. Characteristic impedance tolerance of ±10% is recommended. In no case should characteristic impedance be more than 20% from nominal. Stripline with a solid ground plane as reference is the most preferred solution. It allows some extra routing flexibility, e. g. PCB side change for final destination (antenna or FEM) If a microstrip line is used, a solid ground plane should be used as reference ground. The RF trace s reference ground continuity must be preserved. If more than one reference ground is used (e. g. for stripline and coplanar waveguide), those secondary grounds have to be well stitched to a solid ground plane. If othr components are foreseen for antenna impedance matching, they must be placed near the antenna feed terminal. The ground pads of shunt components have to have good direct connection to RF reference ground(s). Bending of RF trace more than 45º is not allowed. If the RF trace has to be turned by 90º, than two 45º bends shall be used with a distance between bend points of at least 1 mm. 2.2 FM-RX RF front-end The STLC2690 implements differential LNA for FM-RX input and requires a conversion to be connected to single-ended antenna. Two capacitors and one inductor are needed for this conversion (L1, C6, and C7). During layout, the following rules must be respected: The connection between ground pads of capacitors C6 and C7 should be good and short. These ground pads should have connection to solid ground plane with at least 8/17 DocID Rev 1

9 Layout rules one buried via. These ground pads must not be connected to ground pins H8, G6 of the STLC2690. Connection to FM-RX LNA (pins H7 and G8 of the STLC2690) should be implemented with differential pair, especially in cases where the front end is located far from the STLC2690. A characteristic impedance of 200 Ω is recommended for this differential pair. However, due to some constraints it is not always possible. In this case, a characteristic impedance greater than 100 Ω is acceptable. Special care should be taken to avoid any noisy or high-speed digital signal routing in the proximity the FM-RX front-end and connection to the FM antenna. The ground connection of the resonant circuit (capacitors C6 and C7) shall be placed further away from the STLC2690 in order to reduce noise pick-up from ground bouncing. It is also not recommended to put in proximity other ground vias carrying significant current. Separation of at least 2-3 mm is recommended. Figure 7: FM_RX RF front-end: layout example 2.3 FM-TX RF interface The STLC2690 implements differential PA for FM-TX output and requires direct connection to the antenna (an electrically short loop antenna is assumed). This connection should be differential, of any kind. In order to reduce parasitic capacitance to ground, a characteristic impedance greater than 100 Ω is recommended. The overall DC resistance of this connection shall not exceed 0.2 Ω. If additional ESD protection is foreseen for the FM-TX antenna, ESD component(s) must be located close to the antenna feed point. DocID Rev 1 9/17

10 Layout rules 2.4 Ground connection AN RF ground connection The RF ground connection involves pins A8, D8, B7 and C7 of the STLC Analog ground connection The analog ground connection involves A7, C5, D6, E7 and E8 pins of the STLC2690. Pin A7 does not have any special requirements for ground connection, though "direct ground connection" as expressed in Figure 8: "Direct ground connection, cross section view" is recommended. Figure 8: Direct ground connection, cross section view Pins D6 and E7 should be connected to each other on layer 1 and should have a "direct ground connection" towards solid ground plane with one via. In addition, pin D6 should be connected to pin C7 on layer 1. Pin C5 can be connected to pin D6 on second layer. Pin E8 should be connected to solid ground plane with "direct ground connection" outside of the STLC2690 perimeter. The best approach is to put this connection close to the ground pad of capacitor C4. This ground connection should be kept apart from the FM ground connection including FM-RX front end. There should be no ground, other connections or any copper on layers 1 and 2 layers in the perimeter between pins A6, B7, C7, D6, C5, and B FM ground connection The FM ground connection involves pins G6 and H8 of the STLC2690. Pin G6 should be connected on layers 1 and 2 to pin H8. Then, pin H8 should be connected to solid ground plane with one "vertical ground" connection. 10/17 DocID Rev 1

11 2.4.4 Digital ground connection The digital ground connection involves pin E1 of the STLC2690. This pin should be connected to solid ground plane with one "vertical ground" connection Decoupling and compensation capacitors ground connection Layout rules The ground pads of the C1 to C5 capacitors should be connected directly to solid ground plane with one "vertical ground" connection. If possible, it is recommended to make an extra ground connection on Layer 3: For capacitor C4: Ground pad of C4 should be connected to pin E8 of the STLC2690. For capacitor C1: Ground pad of C1 should be connected to pin E1 of the STLC Power supply distribution The power supply shall be routed in a "star like" manner starting from decoupling on the 1.8 V supply rail (capacitor C5). Wherever possible, the power supply track width should be at least 0.25 mm. All connections to compensation and decoupling capacitors must respect a maximum series resistance of 0.4 Ω including ESR of the capacitor, and a maximum 2.6 nh series inductance including ESL of the capacitor (ESL at 10 MHz). Capacitor C9 connected to pin E2 of the STLC2690 (digital part supply) is optional and can be recommended in cases where the 1.8 V voltage source is located >30 mm away from the STLC Other signals Reference clock The following rules must be respected for routing of the reference clock track: The path from the clock source to the STLC2690 should be clean and protected by ground from any disturbance. It is not permitted to rout any other track in parallel to the reference clock track from side, top or bottom. The number of orthogonal crossings on other layers should be reduced, especially for powerful and dynamic signals High speed digital interfaces In case the SPI interface is selected as HOST interface for the STLC2690, the generic rules for high speed digital signal routing shall apply: Other signals Signals SPI_CLK (pin D3), SPI_DI (pin D2), SPI_DO (pin C3) should have double clearance. These signals should experience continuous ground along the entire path. These signals should have equal length. Recommended minimum tolerance in propagation delay difference is ±1 ns (for 52 MHz interface speed). There are no special requirements for all other signals. DocID Rev 1 11/17

12 Layout rules 2.7 References AN Datasheet: STLC2690 Bluetooth TM and FM transceiver system-on-chip; Revision 3 or later 2. BMDS_STLC2690_HW_Manual_Bluetooth_ED10.pdf 12/17 DocID Rev 1

13 Appendix A STLC2645 PCB implementation Figure 9: Example of PCB implementation, layer 1 DocID Rev 1 13/17

14 Figure 10: Example of PCB implementation, layer 2 AN /17 DocID Rev 1

15 Figure 11: Example of PCB implementation, layer 3 DocID Rev 1 15/17

16 3 Revision history Table 1: Document revision history Date Revision Changes 02-Dec Initial release. 16/17 DocID Rev 1

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