1) For a RS flip flop constructed out of NAND gates complete the following table. R S Q Q\ State name Q Q\

Transcription

1 Sequential logic tutorial Flip Flops 1) For a RS flip flop constructed out of NAND gates complete the following table R S Q Q\ State name Q Q\ 2) Complete the following timing diagram. Under the diagram write the state of the flip flop 3) For a NOR gate flip-flop complete its truth table R S Q Q\ State name 0 0 Q Q\ ) Complete the following timing diagram. Under the diagram write the name of each state the flip flop is in.

2 5) For a positive level triggered RS flip flop fill in the missing parts in the following truth table Clock R S Q Q\ State name Set 0 1 Reset 1 1 Q Q\ 6) Finish of the following timing diagram. Write the name of each state under the diagram 7) Using an RS NAND gate flip flop draw a timing diagram to show what the RS inputs have to be for the flip-flop to be in the following states : RESET,HOLD,HOLD,SET,SET,HOLD,RESET 8) Using an RS NOR gate flip flop draw a timing diagram to show what the RS inputs have to be for the flip-flop to be in the following states : RESET,SET,HOLD,RESET,HOLD,SET,SET,HOLD 9) Repeat question 8 this time a clocked RS flip flop is used.

3 10) A positive edge triggered D-Flip flop has the following binary signals applied to it as well as the clock. The signals are Draw the resulting timing diagram including the Q and Q\ outputs 11) Complete the following timing diagram for a 74HC74 Clock D PS CLR Q Q\ 12) The circuit shown below shows a circuit designed to synchronize the input to the clock. Complete the timing diagram shown after the circuit diagram. 13) Some times a circuit needs to be clocked a specific number of pulses which are proportional to the width of the input pulse. Such a circuit is shown below:

4 i. Complete the following timing diagram ii. iii. Redraw the circuit minimizing the number of logic gates used. Can you find a suitable application for such a circuit? 14) For a 74HC76 JK flip Flop with both its PS and CLR inputs tied to +5V finish the following timing diagram 15) If the 74HC76 flip flop in question 14 is replaced by a 74HC109, positive edge triggered flip flop redraw the timing diagram. 16) Show how a D type flip flop can be converted into a T type flip flop and draw a timing diagram to illustrate the conversion.

5 Counters 17) Use a 74HC76 to draw a 3 stage counter that is cleared to 0 at startup. Draw the resulting circuit and function table. 18) Mention the differences between a ripple counter and a synchronous counter. Which is the easiest type of counter to implement? 19) If a 4 stage counter is clocked at 1kHz, what is the frequency that the counter will reset and start from the beginning? 20) Draw a 4 stage asynchronous down counter. Add extra logic gates to indicate that the counter output has reached 12,10 and 8 and connect the output of each logic circuit to an LED. 21) Design and draw a mod 11 up counter. Draw the related timing diagram showing relevant points at the output. 22) Design a ripple down counter that starts from 8 and resets when the value at the output reaches 4. 23) The following is a simple circuit using the 74HC193 binary counter. Draw a timing diagram illustrating outputs Q0,Q1,Q2,Q3,TCU and TCD when the output is 1110 to ) Modify the circuit in question 23 to work as a decade up counter. 25) By adding suitable components make the circuit shown in question 23 work as a down counter. Shift registers 26) For a 4 bit serial in parallel out register using D flip flops draw a function table when the input data is is provided at the input. The clear signal is 0 for one clock pulse only. Clock pulse Clear Data A B C D 27) Draw a timing diagram for the data, A, B,C,D in question 26.

6 28) Use the serial in parallel out shift register in question 26 as a Serial in, Serial out shift register to shift the input data Assume that the shift register is cleared at the beginning of the sequence. For how many clock cycles does the shift register delay the signal? How can the delay length be increased? 29) Draw a timing diagram for 6 cycles for this circuit, showing Q 0 to Q 3 and the clock pulses. Assume that the registers are cleared at the start of the timing diagram. 30) The following diagram shows a Parallel in Serial out shift register a. Explain how the data is loaded asynchronously in the shift register. b. Explain the disadvantage of such a system.

7 c. Assume that the data 1001 will be loaded into the shift register and shifted out, draw a timing diagram for 6 clock cycles, for Q A,Q B,Q C,Q D and Clear. Assume that the shift register will be cleared at the beginning of the sequence. d. Explain why in such a shift register the data is recycled back to the input. 31) Show how two universal shift registers can be cascaded together to form an 8 bit shift left register. What control pins have to be shorted together? 32) This shift register circuit produces a sequential light, at reset one LED energizes, then two LEDs energize, and then all three LEDs energize before all deenergizing and repeating the sequence. The 74HC194 shift register circuit is set to always operate in the "shift right" mode with the shift-right serial input (DSR) tied high, the master reset (MR) input used to set all output lines to a low state at the end of each cycle: The sequential light pattern is supposed to begin whenever the "Trigger" input momentarily goes high. Unfortunately, something has failed in this circuit which is preventing any of the LEDs to come on. No blinking light sequence ensues, no matter what the state of the "Trigger" input. Identify some likely failures in this circuit that could cause this to happen, other than a lack of power supply voltage. Explain why each of your proposed faults would cause the problem, and also identify how you would isolate each fault using test equipment.