Clocked R S, D, J K and T Flip Flop

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1 C22: Digial i Design Clocked, D, J K and T Flip Flop Dr. A. ahu Dep of Comp. c. & Engg. Indian Insiue of Technology Guwahai

2 Ouline Design a new building block, a flip flop, ha sores one bi Lach Vs Flip Flop Maser lave Flip Flop D Flip Flop Flop, J K Flip Flop Flop and T Flip Flop Flop Combine ha block o build muli bi sorage a regiser

3 equenial Circui Inpu b Combinaional logic s s n n x oupu clk Hisory/ equence/ae Where o ore his Hisory Y () = F (a(),b(), H) H is Hisory/equence/ae (Memory Elemen)

4 Bi orage Using an Lach Does he circui o he righ, wih crosscoupled NO gaes, do wha we wan? Yes! How did someone come up wih ha circui? Maybe jus rial and error, a bi of insigh... (se) (rese) lach = = = = = = = =

5 Problem wih Lach: ace Condiion Problem: If = & = simulaneously and boh released o, we don know wha value will = ake = = = = = may oscillae. Then, because one pah will be slighly longer han he oher, will evenually sele o or bu we don know which.

6 Problem wih Lach Problem no jus one of a user pressing wo buons a same ime Can also occur even if inpus come from a circui ha supposedly never ses = and = a same ime Bu does, due o differen delays of differen pahs X Arbirary circui lach X Y Y The longer pah from X o han o causes = for shor ime could be long enough o cause oscillaion =

7 oluion: Level ensiive Lach Add enable inpu C as shown Only le and change when C= Ensure circui in fron of never ses =, excep briefly due o pah delays Change C o only afer sufficien i ime for and o be sable bl When C becomes, he sable and value passes hrough he wo AND gaes o he lach s inpus. C Level-sensiive lach C Level-sensiive lach symbol

8 oluion: Level ensiive Lach X Level-sensiive lach Clk C Y Though = briefly... C a... never =

9 oluion: Ensure, abilize, ore X Level-sensiive lach Clk C Y Ensure age Never Happens = abilize age When C= abilize and Use when C= ore age ore bi

10 Clocks Clock period: ime inerval beween pulses Above signal: period = 2 ns Freq Period Clock cycle: one such ime inerval GHz. ns Above signal shows 3.5 clock cycles Clock frequency: /period Above signal: frequency = / 2 ns = 5 MHz Hz = /s GHz GHz MHz MHz. ns ns ns ns

11 Clock ignals for a Lach How do we know when i s safe o se C=? Mos common soluion make C pulse up/down Cafe C=: o change X, Y CMus C=: no change X, Y Clock signal Pulsing signal used o enable laches Because i icks like a clock equenial circui whose sorage componens all use clock signals: synchronous circui X Level-sensiive lach Clk C Y

12 Level ensiive D Lach lach requires careful design o ensure = never occurs D lach relieves designer of ha burden Insered inverer ensures always opposie of D C D lach D C D C D lach symbol

13 Problem wih Level ensiive D Lach D lach sill has problem (as does lach) When C=, hrough how many laches will a signal ravel? Depends on for how long C C= Clk_A signal may ravel hrough muliple laches Clk_B signal may ravel hrough fewer laches Hard o pick ikc ha is jus he righ ihlengh Can we design bi sorage ha only sores a value on he rising edge of a clock signal? Y D D2 2 D3 3 D4 4 rising edges C C2 C3 C4 Clk Clk Clk_A Clk_B

14 Flip Flop Coin Flip : Head/Tail (/) Lach have eiher one sae or Flip Flop (Boh Maser/lave) Flip ae/flop ae

15 Maser lave D Flip Flop Flip flop: sores on clock edge, no level Two laches, oupu of firs goes o inpu of second, maser lach has invered clock signal o maser loaded when C=, hen servan when C= When C changes from o, maser disabled, servan loaded wih value ha was a D jus before C changed i.e., value a D during rising edge of C D Dm Cm D lach maser m Ds D flip-flop D lach s Cs s servan Clk D/Dm Cm m/ds Cs Clk s

16 Thanks

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