Set-Reset (SR) Latch
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1 Set-Reset (SR) Latch Asynchronous Level sensitive cross-coupled Nor gates active high inputs (only one can be active) S R S R Function Reset Set ? 0-? Indeterminate State cross-coupled Nand gates active low inputs (only one can be active) S R S R Function ? 1-? Indeterminate State Set Reset C.. Stroud, ept. of C, Auburn Univ.
2 nabled Set-Reset (SR) Latch Asynchronous Level sensitive cross-coupled AOI21 gates active high inputs (S & R cannot be active) S R S R Function 0 x x Reset Set ? 0-? Indeterminate State cross-coupled OAI21 gates active low inputs (S & R cannot be active) S R S R Function ? 1-? Indeterminate State Set Reset x x + C.. Stroud, ept. of C, Auburn Univ.
3 Transparent Latch Asynchronous Level sensitive cross-coupled AOI21 gates and inverter active high enable () Function 0 x Transparent Mode Transparent Mode cross-coupled OAI21 gates active low enable () Function 1 x Transparent Mode Transparent Mode C.. Stroud, ept. of C, Auburn Univ.
4 Flip-Flop Synchronous (also know as Master-Slave FF) dge Triggered (data moves on clock transition) one latch transparent - the other in storage active low latch followed by active high latch positive edge triggered (rising edge of ) Master Section active low latch Slave Section active high latch active high latch followed by active low latch negative edge triggered (falling edge of ) Master Section active high latch Slave Section active low latch C.. Stroud, ept. of C, Auburn Univ.
5 Timing Considerations Set-up time (t s )= minimum time data must be valid before active edge of clock Hold time (t h )= minimum time data must be held valid after active edge of clock Clock-to-output delay (t do )= maximum time before output data is valid with respect to active edge of clock t s t h t do Set-up or Hold Time violation => metastability ( & go to intermediate voltage values which are eventually resolved to an unknown state) Set-up & Hold Time violations in a vector set referred to as clock-data races C.. Stroud, ept. of C, Auburn Univ.
6 Good esign Practices Use single clock, single edge synchronous design techniques as much as possible Asynchronous interfaces lead to metastability (minimize the async interface & double clock data to reduce probability of metastability) Avoid asynchronous presets & clears on FFs (use sync presets & clears whenever possible) O NOT construct a FF from two level sensitive latches of the same type with an inverter on the clock input to one latch active low latch active low latch O NOT gate clocks!!! Create clock enabled FFs via a MUX to feed back current data BA esign 0 1 CN CN BA esign GOO esign Active high clock enable (CN) C.. Stroud, ept. of C, Auburn Univ.
7 Transmission Gate Latches/FFs A single NFT (PFT) looks like a active high (low) level sensitive dynamic latch (storage mechanism is capacitive load) But NFT (PFT) passes a poor logic 1 (0) with both, enable inverter can cause timing problems inverter on gives consistent capacitive load ynamic FF made with 2 latches falling edge triggered dynamic FF ynamic latches/ffs require data refresh C.. Stroud, ept. of C, Auburn Univ.
8 Transmission Gate Latches/FFs Static FFs & Latches require feedback Cross-coupled gate FFs are static (like OAI21s & AOI21s - data lasts indefinitely) Static T-gate Latch => extra inverter & T-gate Static T-gate FF made with 2 latches falling edge triggered static FF T-gate based latches/ffs require careful design, layout, and simulation to ensure proper operation (no timing problems) C.. Stroud, ept. of C, Auburn Univ.
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