Quiet Expert 5.0 update

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1 Quiet Expert 5.0 update Chang, SungHyuk Sr. Application Engineer System Design Division May 26, 2010

2 Why DRC? PCB layout verification All PCB design teams use some form of manual PCB verification Many PCB designs face compliance problems because of improperly routed structures that are hard to find and impossible to simulate For this purpose, DRC provides... A verification process that is uniform and repeatable across design teams in different locations to prevent variance or out of control verification processes Global design teams Quality control on 3 rd party boards Verify complex boards routed in house A customizable platform for capture and implementation of a company s own design rules 2

3 Why DRC? (Cont ) Proper layout of PCBs can significantly reduce system EMI Early preparation in the design cycle is the best place to fix potential EMI problems DRCs give the quickest, most cost effective, and most understandable method to solving EMI problems Doesn t require extensive simulation times Makes the verification process repeatable Can significantly reduce design cycle times by eliminating late design changes needed to improve EMC performance Easy for anyone to use once the EMC engineer has built their knowledge into the tool 3

4 Why DRC? (Cont ) Ground Return Analysis Is this an EMI problem? A grounding problem? A SI problem? What can simulate this? (No, I mean really simulate it ) Can Simulation help here? 4

5 Hand Check Design Rules Works if you know your rules Time Consuming Prone to human error Most companies have rules, but no automation or mechanism to implement and enforce them 5

6 Quiet Expert - Fast, Flexible EMC Verification Fuction - Rules-based PCB design verification - Flag area of potential problems - Gives advice on how to fix the problem Benefits - Find problematic structures that are not able to be simulated - Ships with 24 built-in DRCs - User customizable 6

7 Quiet Expert (Cont ) Provides companies with a platform to automate the board verification process Scans the whole board, using fast scanning technology to find, display and highlight DRC viloations Repeatability that allows the same verification process to be used over and over on different designs Read designs from following interfaces QE 4.x, Expedition, BoardStation, HyperLynx PADS, Allegro, Zuken, Cadstar Setup common environments using.qeset file 7

8 Main Display Window Project Explorer Design Viewer (Support Shortcut) Properties Datails (Design or DRC results) Spreadsheet Drag and Drop for moving windows 8

9 Interface BoardStation classic Ample installs new menu and creates 5 files for translation QE opens.prt file 9

10 Interface QE4.x or HyperLynx Just open QE4.x project file or.hyp file QE 4.x HyperLynx 10

11 Interface - Expedition Just click menu for export design to QE Reopen.ibd for updating design changes 11

12 Interface Expedition (Cont ) Changes in CES, and then updated in QE Changes in CES Updated in QE 12

13 Interface Expedition (Cont ) Changes in Expedition, and then updated in QE Changes in Expedition Updated in QE 13

14 Sync with CES Not Editable, Locked by CES Editable, without CES 14

15 Project Explorer General Settings Paths Units Default Values Project Data Layers Componensts Nets Analysis Setup Models Object Lists Rules and Results Rules Violations 15

16 Create Object Lists Manual Click New List Select Object Type Select Method Copy and Paste 16

17 Create Object Lists - Auto Any or All Select Condition Enter value 17

18 Create Models Some DRCs needs Models Use.qmf files of QE4.x Use.ibs files Convert.ibs to.qmf 18

19 Customize Rules and Groups Create New groups and Import new rules 19

20 Change parameter values Click the DRCs and enter the value in Parameters tab 20

21 Run DRCs Whole Design Check the DRC to run, applied to whole design 21

22 Run DRCs Object List Check the DRC to run, applied to Object List 22

23 Look over violations Click Violation Highlight violation Properties Datails Spreadsheet results 23

24 Cross Probing Check the violation in QE and Expedition at same time Can take a close look in Expedition 24

25 Export results to files Spreadsheet.html.csv 25

26 Sort results by Objects Viloations of Objects in Project Explorer Violations of Objects in Spreadsheet 26

27 Built in DRCs : requires model 27

28 DRC example : Differential Pairs Theory To prevent excessive common mode currents, you should length match both halves of a differential pair and have consistent spacing between them Objective Identify any differential pairs that exceed a specified skew tolerance 28

29 DRC example : IC Over Split Theory ICs that reside over splits often result in gap crossing or instant reference plane changes These lead to increased loop areas for return currents which could cause common mode emissions Objective Look for ICs with multiple reference area fills 29

30 DRC example : Reference Plane Change Theory When different traces on the same net have different references, this can cause discontinuities in the return path causing large loop areas This typically occurs at a gap in a plane or a via Objective Eliminate or minimize the number of instances where a net changes its respective reference 30

31 DRC example : Net Crossing Gaps Theory Nets crossing gaps, slots, or splits can create large loop areas leading to increased EMI Objective Ensure that routed traces do not cross gaps in the reference plane 31

32 32 Your Initials, Presentation Title, Month Year

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