SERVICE MANUAL VHF TRANSCEIVER. if110 if111 if121

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1 SERVICE MANUAL VHF TRANSCEIVER if0 if if

2 INTRODUCTION This service manual describes the latest service information for the IC-F0, F and F VHF TRANSCEIVER at the time of publication. DANGER NEVER connect the transceiver to an AC outlet or to a DC power supply that uses more than 6 V. This will ruin the transceiver. MODEL IC-F0 IC-F IC-F VERSION Europe General General U.S.A. SYMOL EUR GEN GEN USA DO NOT expose the transceiver to rain, snow or any liquids. DO NOT reverse the polarities of the power supply when connecting the transceiver. DO NOT apply an RF signal of more than 0 dm (00 mw) to the antenna connector. This could damage the transceiver s front end. To upgrade quality, any electrical or mechanical parts and internal circuits are subject to change without notice or obligation. ORDERING PARTS e sure to include the following four points when ordering replacement parts:. 0-digit order numbers. Component part number and name. Equipment model name and unit name. Quantity required <SAMPLE ORDER> S.IC TA6FN IC-F0 MAIN UNIT pieces Screw PH T M 8 ZKIC-F0 ottom cover 0 pieces Addresses are provided on the inside back cover for your convenience. REPAIR NOTES. Make sure a problem is internal before disassembling the transceiver.. DO NOT open the transceiver until the transceiver is disconnected from its power source.. DO NOT force any of the variable components. Turn them slowly and smoothly.. DO NOT short any circuits or electronic parts. An insulated tuning tool MUST be used for all adjustments.. DO NOT keep power ON for a long time when the transceiver is defective. 6. DO NOT transmit power into a signal generator or a sweep generator. 7. ALWAYS connect a 0 d to 0 d attenuator between the transceiver and a deviation meter or spectrum analyzer when using such test equipment. 8. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.

3 EXPLICIT DEFINITIONS FREQUEY COVERAGE 6 7 MHz CHANNEL SPACING Narrow/Wide-type Narrow/Middle-type. khz/.0 khz.0 khz/ 0.0 khz. khz/ 0.0 khz TALE OF CONTENTS SECTION SECTION SECTION SECTION SPECIFICATIONS INSIDE VIEW DISASSEMLY INSTRUCTIONS CIRCUIT DESCRIPTION - RECEIVER CIRCUITS TRANSMITTER CIRCUITS PLL CIRCUITS POWER SUPPLY CIRCUITS PORT ALLOCATIONS SECTION ADJUSTMENT PROCEDURES - PREPARATION PLL ADJUSTMENT SOFTWARE ADJUSTMENT SECTION 6 SECTION 7 SECTION 8 SECTION 9 PARTS LIST MECHANICAL PARTS AND DISASSEMLY SEMI-CONDUCTOR INFORMATION OARD LAYOUTS 9 - FRONT UNIT MAIN UNIT SECTION 0 SECTION LOCK DIAGRAM VOLTAGE DIAGRAMS - FRONT UNIT MAIN UNIT

4 SECTION SPECIFICATIONS RECEIVER TRANSMITTER GENERAL Measurement method Frequency coverage Type of emission Number of conventional channels Antenna impedance Power supply voltage (negative ground) Current drain (approx.) Usable temperature range Dimensions (proj. not included) Weight RF output power Modulation system Maximum permissible deviation Frequency error Spurious emissions Adjacent channel power Audio frequency response Audio hormonic distortion FM hum and noise (typical) (without CCICT filter) Residual modulation (typical) (with CCICT filter) Limitting charact of modulator Microphone connector Receive system Intermediate frequencies Sensitivity (typical) Squelch sensitivity (at threshold) Hum and noise Adjcent channel selectivity Spurious response Intermoduration Audio output power External SP connector [GEN], [USA] [EUR] EIA--C/0D or TIA-60 ETS MHz N/W: (. khz; Narrow/ khz; Wide): 8K0FE/6K0FE [EUR] (. khz; Narrow/ khz; Wide): K0FE/6K0FE [GEN] ( khz; Narrow/0 khz; Wide): K0FE/6K0FE [USA] N/M (. khz; Narrow/0 khz; Middle): 8K0FE/K0FE [EUR] maximum 8 channels 0 Ω nominal (SO-9).6 V DC nominal. V DC nominal TX; 7.0 A (at W),.0 A (at 0 W) Rx; 00 ma (maximum audio) 00 ma (stand-by) 0 C to +60 C ( F to +0 F) C to + C 0(W) 0(H) 7.(D) mm; 9 (W) 9 6(H) 8(D) inch [ W] 0(W) 0(H) 67.(D) mm; 9 (W) 9 6(H) 6 9 (D) inch [0 W] 0.8 kg; lb oz [ W],. kg; lb 7 oz [0 W] High/Low/Low: W/0 W/. W [ W] High/Low/Low: 0 W/ W/ W [0 W] Variable reactance frequency modulation ±. khz [Narrow], ±.0 khz [Middle], ±.0 khz [Wide] ±.0 ppm ±. khz 70 d (typical) 0. µw GHz,.0 µw > GHz 60 d minimum [Narrow]; 70 d minimum [Middle], [Wide] + d to d of 6 d/octave Range from 00 Hz to 0 Hz [Narrow] / 000 Hz [Middle], [Wide] % typical at khz (0% deviation) d (min.), 0 d (typ.) [Narrow] 0 d (min.), 6 d (typ.) [Wide] 0 d (min.), 0 d (typ.) [Narrow] d (min.), d (typ.) [Middle] d (min.), d (typ.) [Wide] 70 00% of maximum deviation 8-pin modular (600 Ω) Double-conversion superheterodyne system st: 6. MHz, nd: 0 khz 0. µv typical at d SINAD dµv (emf) typical at 0 d SINAD 0. µv typical dµv (emf) typical d (min.), 0 d (typ.) [Narrow] 0 d (min.), d (typ.) [Wide] 0 d (min.), 0 d (typ.) [Narrow] d (min.), d (typ.) [Middle] d (min.), d (typ.) [Wide] 60 d (min.), 6 d (typ.) [Narrow] 70 d (min.), 7 d (typ.) [Middle]/[Wide] 7 d 70 d (min.), 7 d (typ.) 6 d (min.), 67 d (typ.) W typical at 0% distortion with a Ω load -conductor. (d) mm ( 8")/ Ω All stated specifications are subject to change without notice or obligation. -

5 SECTION INSIDE VIEW Antenna switch/ Low-pass filter circuit Mixer* (Q: SK99) nd IF filter* (FI: ALFYM0F=K) D/A converter* (IC6: M66FP-60C) IF IC (IC: TA6FN) st IF filter (FI: FL-) Final FET module (IC: S-AV) CPU V regurator* (IC0: AN78L0M) regurator (IC9: TA7808F) VCO circuit AF amplifier (IC8: LAA) Reference crystal oscillator* (X: CR-70. MHz) PLL IC (IC: MA0PFV-) * Located under side of the point. -

6 SECTION DISASSEMLY INSTRUCTIONS Opening case ➀ Unscrew screws A, and remove the bottom cover. ➁ Disconnect the flat cable from J. ➂ Disconnect the cable C from J7. ➃ Unscrew screws D, and remove the front unit. ➉ Lift up the front portion of the main unit and remove it. A J J7 Installation location UT-0 SmarTrank logic board UT-08 DTMF decoder unit UT-09 UT-0 Voice scrambler unit UT- Trunking unit OPC-67 ACC cable (for external terminal connection) C D ➄ Unscrew 8 screws E. ➅ Remove the filter case F. ➆ Unscrew the screw G. ➇ Unsolder points H from the antenna connector. ➈ Unsolder points I from IC. UT-0 UT-08 UT-09 UT-0 UT- J OPC-67 J6 E F H I G -

7 SECTION CIRCUIT DESCRIPTION - RECEIVER CIRCUITS -- ANTENNA SWITCHING CIRCUIT (MAIN UNIT) The antenna switching circuit functions as a low-pass filter while receiving and as resonator circuit while transmitting. This circuit does not allow transmit signals to enter the receiver circuits. -- ST MIXER AND ST IF CIRCUITS (MAIN UNIT) The st mixer circuit converts the received signals to a fixed frequency of the st IF signal with the PLL output frequency. y changing the PLL frequency, only the desired frequency will pass through a MCF (Monolithic Crystal Filter; FI) at the next stage of the st mixer. Received signals enter the antenna connector and pass through the low-pass filters (L L, C, C, C6 8). The filtered signals are then applied to the RF circuit passed through the λ type antenna switching circuit (D D7, D8, L, L6). -- RF CIRCUIT (MAIN UNIT) The RF circuit amplifies signals within the range of frequency coverage and filters out-of-band signals. The signals from the antenna switching circuit pass through the two-stage tunable bandpass filters (D8, D). The filtered signals are amplified at the RF amplifier (Q) and then enter other two-stage bandpass filters (D9, D0) to suppress unwanted signals. The filtered signals are applied to the st mixer circuit (Q). The tunable bandpass filters (D, D8 D0) employ varactor diodes to tune the center frequency of the RF passband for wide bandwidth receiving and good image response rejection. These diodes are controlled by the CPU (FRONT unit; IC) via the D/A converter (IC6). The gate control circuit reduces RF amplifier gain and attenuates RF signal to keep the audio output at a constant level. The receiver gain is determined by the voltage on the RSSI line from the FM IF IC (IC, pin ). The gate control circuit (Q) supplies control voltage to the RF amplifier (Q) and sets the receiver gain. When receiving strong signals, the RSSI voltage increases and the gate control voltage decreases. As the gate control voltage is used for the bias voltage of the RF amplifier (Q), then the RF amplifier gain is decreased. ND IF AND DEMODULATOR CIRCUIT "SQLIN" signal AF signals FM detector 8 7 Active filter 9 0 Limiter amp. Noise detector V X Discriminator RSSI The RF signals from the bandpass filter are applied to the st mixer circuit (Q). The applied signals are mixed with the st LO signal coming from the RX VCO circuit (Q) to produce a 6. MHz st IF signal. The st IF signal passes through a MCF (Monolithic Crystal Filter; FI) to suppress out-of-band signals. The filtered signal is amplified at the st IF amplifier (Q) and applied to the nd IF circuit. -- ND IF AND DEMODULATOR CIRCUITS (MAIN UNIT) The nd mixer circuit converts the st IF signal to a nd IF signal. A double-conversion superheterodyne system improves the image rejection ratio and obtains stable receiver gain. The st IF signal from the st IF amplifier (Q) is applied to the nd mixer section of the FM IF IC (IC, pin 6) and is then mixed with the nd LO signal for conversion to a 0 khz nd IF signal. IC contains the nd mixer, limiter amplifier, quadrature detector, active filter and noise amplifier circuits, etc. A tripled frequency from the PLL reference oscillator is used for the nd LO signal (.9 MHz). The nd IF signal from the nd mixer (IC, pin ) passes through a ceramic filter (FI) to remove unwanted heterodyned frequencies. It is then amplified at the limiter amplifier section (IC, pin ) and applied to the quadrature detector section (IC, pins 0, and X) to demodulate the nd IF signal into AF signals. The AF signals are output from pin 9 (IC) and are then applied to the AF amplifier circuit. nd IF filter 0 khz FI.9 MHz Mixer 6 "RSSI" signal to the CPU PF IC TA6FN Q X. MHz st IF from the IF amplifier (Q) "NOIS" signal to the CPU -

8 -- AF AMPLIFIER CIRCUIT (MAIN UNIT) The AF amplifier circuit amplifies the demodulated AF signals to drive a speaker. The AF signals from the FM IF IC (IC, pin 9) are applied to the active filter circuit (IC6). The active filter circuit (highpass filter) removes CTCSS or DTCS signals. The filtered AF signals are output from pin (IC6) and are applied to the de-emphasis circuit (R7, C78) with frequency characteristics of 6 d/octave, and then passed through the analog switch (IC, pins ) and low-pass filter (IC). The filtered signal is applied to the electronic volume controller (IC6, pin 9). The output AF signals from the electronic volume controller (IC6, pin 0) are passed through the analog switch (IC pins 9 ) and are applied to the AF amplifier (IC) and AF power amplifier (IC8) to drive the speaker. --6 RECEIVER MUTE CIRCUITS (MAIN AND FRONT UNITS) NOISE SQUELCH The noise squelch circuit cuts out AF signals when no RF signals are received. y detecting noise components in the AF signals, the squelch circuit switches the AF mute switch. Some noise components in the AF signals from the FM IF IC (IC, pin 9) are passed through the level controller (IC6, pins, ). The level controlled signals are applied to the active filter section in the FM IF IC (IC, pin 8). Noise components about 0 khz are amplified and output from pin 7. The filtered signals are converted to the pulse-type signals at the noise detector section and output from pin (NOIS). The NOIS signal from the FM IF IC is applied to the CPU (FRONT unit; IC, pin ). The CPU then analyzes the noise condition and controls the AF mute signal via AFON line (D, D) to the AF mute circuit (Q, Q6, D9, D0). CTCSS AND DTCS The tone squelch circuit detects AF signals and opens the squelch only when receiving a signal containing a matching subaudible tone (CTCSS or DTCS). When tone squelch is in use, and a signal with a mismatched or no subaudible tone is received, the tone squelch circuit mutes the AF signals even when noise squelch is open. A portion of the AF signals from the FM IF IC (IC, pin 9) passes through the low-pass filter (IC6) to remove AF (voice) signals and is applied to the CTCSS or DTCS decoder inside the CPU (FRONT unit; IC, pin 60) via the CDEC line to control the AF mute switch. - TRANSMITTER CIRCUITS -- MICROPHONE AMPLIFIER CIRCUIT (MAIN AND FRONT UNITS) The microphone amplifier circuit amplifies audio signals within +6 d/octave pre-emphasis characteristics from the microphone to a level needed for the modulation circuit. The AF signals (MIC) from the MIC jack (FRONT unit; J) are amplified at the AF amplifier (FRONT unit; IC) and applied to the MAIN unit via J (pin 8). The AF signal are applied to the limiter amplifier (IC, pin ). The entered signals are pre-emphasized with +6d/octave at a limiter amplifier, then passed through the analog switch (IC, pins ) and splatter filter (IC, pins, ). The output signals from the splatter filter are applied to the level controller (IC6, pin 9). The deviation level controlled signals are then applied to the modulation circuit (D8) as the MOD signal after being passed through the analog switch (IC, pins 9, 8). -- MODULATION CIRCUIT (MAIN AND FRONT UNITS The modulation circuit modulates the VCO oscillating signal (RF signal) using the microphone audio signals. The AF signals from the analog switch (IC, pin 8) change the reactance of varactor diode (D8) to modulate the oscillated signal at the TX VCO circuit (Q, D6, D). The modulated VCO signal is amplified at the buffer amplifiers (Q, Q0) and is then applied to the drive amplifier circuit via the T/R switch (D). The CTCSS/DTCS signals from the CPU (FRONT unit; IC, pins ) are passed through the low-pass filter (FRONT unit; IC), and mixer and splatter filter (IC), and are then applied to the VCO circuit. -- DRIVE AMPLIFIER CIRCUIT (MAIN UNIT) The drive amplifier circuit amplifies the VCO oscillating signal to the level needed at the power amplifier. The RF signal from the buffer amplifier (Q0) passes through the T/R switch (D) and is amplified at the drive amplifier circuit (Q8). The amplified signal is applied to the power amplifier circuit. -

9 -- POWER AMPLIFIER CIRCUIT (MAIN UNIT) The power amplifier circuit amplifies the driver signal to an output power level. The RF signal from the drive amplifier (Q8) is passed through the low-pass filter circuit (L8, L, C89, C90, C9, C80, C8, C0) and applied to the power module (IC) to obtain W or 0 W of RF power. The amplified signal is passed through the antenna switching circuit (D), low-pass filter and APC detector, and is then applied to the antenna connector. Control voltage for the power amplifier (IC, pin ) comes from the APC amplifier (IC) to stabilize the output power. The transmit mute switch (D8) controls the APC amplifier when transmit mute is necessary. -- APC CIRCUIT (MAIN UNIT) The APC circuit protects the power amplifier from a mismatched output load and stabilizes the output power. The APC detector circuit detects forward signals and reflection signals at D and D respectively. The combined voltage is at minimum level when the antenna impedance is matched at 0 Ω, and is increased when it is mismatched. The detected voltage is applied to the APC amplifier (IC, pin ), and the power setting T signal from the D/A converter (IC6, pin ), controlled by the CPU (FRONT unit; IC), is applied to the other input for reference. When antenna impedance is mismatched, the detected voltage exceeds the power setting voltage. Then the output voltage of the APC amplifier (IC, pin ) controls the input current of the drive amplifier (Q8) and power module (IC) to reduce the output power. - PLL CIRCUITS -- PLL CIRCUIT (MAIN UNIT) A PLL circuit provides stable oscillation of the transmit frequency and receive st LO frequency. The PLL output compares the phase of the divided VCO frequency to the reference frequency. The PLL output frequency is controlled by the divided ratio (N-data) of a programable divider. The PLL circuit contains the TX/RX VCO circuit (Q, Q). The oscillated signal is amplified at the buffer amplifiers (Q, Q) and then applied to the PLL IC (IC, pin 8) via the low-pass filter (L, C98 C00). The PLL IC contains a prescaler, programable counter, programable divider and phase detector, etc. The entered signal is divided at the prescaler and programable counter section by the N-data ratio from the CPU. The reference signal is generated at the reference oscillator (X) and is also applied to the PLL IC. The PLL IC detects the out-of-step phase using the reference frequency, and outputs it from pin. The output signal is passed through the loop filter (R97/C9, R96/C7), and is then applied to the VCO circuit as the lock voltage. If the oscillated signal drifts, its phase changes from that of the reference frequency, causing a lock voltage change to compensate for the drift in the oscillated frequency. -- VCO CIRCUIT (MAIN UNIT) The VCO circuit contains a separate RX VCO (Q, D, D) and TX VCO (Q, D6, D8, D). The oscillated signal is amplified at the buffer amplifiers (Q, Q0) and is then applied to the T/R switch circuit (D, D). Then the receive st LO (Rx) signal is applied to the st mixer (Q) and the transmit (Tx) signal to the drive amplifier circuit (Q8). A portion of the signal from the buffer amplifier (Q) is fed back to the PLL IC (IC, pin 8) via the buffer amplifier (Q) and low-pass filter (L, C98 C00) as the comparison signal. PLL CIRCUIT Loop filter RX VCO Q, D, D TX VCO Q, D8, D9, D uffer Q uffer Q0 uffer Q D to st mixer circuit D to transmitter circuit IC MA0PFV nd LO signal to the FM IF IC.9 MHz X. MHz Tripler Q Phase Programmable 8 Prescaler detector counter Programmable divider Shift register 9 0 SCK SO PLST -

10 - POWER SUPPLY CIRCUITS -- VOLTAGE LINES (MAIN UNIT) Line HV VCC CPUV V R T Description The voltage from a DC power supply. The same voltage as the HV line which is controlled by the power switching circuit (Q, Q). When the [POWER] switch is pushed, the CPU outputs the PWON control signal to the power switching circuit to turn the circuit ON. Common V for the CPU converted from the HV line by the CPUV regulator circuit (IC0). The circuit outputs the voltage regardless of the power ON/OFF condition. Common 8 V converted from the VCC line by the regulator circuit (IC9). Common V converted from the 8 V and CPU lines by the V regulator circuit (Q7, Q8). Receive 8 V controlled by the R8 regulator circuit (Q6, Q0) using the RXC signal from the expander IC (IC7, pin ). Transmit 8 V controlled by the T8 regulator circuit (Q, Q9, D) using the TMUT signal from the expander IC (IC7, pin ). - PORT ALLOCATIONS -- CPU (FRONT UNIT; IC) Pin number 7 6 7, , Port name Description TEMP Input port for the internal temperature. Input port for the low voltage detection ATV from the connected power supply. RES Input port for reset signal. SE0 Output ports for / tone and DTMF SE signals. CSFT Outputs the CPU clock shift signal. Outputs cut-off frequency control signal DUSE to the low-pass filter (MAIN unit; IC) for CTCSS/DTCS switching. KS0, KS Input port for the key matrix. SE Output ports for / tone and DTMF SE signals. Input port for the PLL unlock signal UNLK from the PLL IC (MAIN unit; IC). KR0 Input port for the key matrix. CENO0 Output ports for CTCSS/DTCS signals. CENO KR, KR Input ports for the key matrix. Outputs the clock signal to the PLL IC (MAIN unit; IC), D/A converter (MAIN SCK unit; IC6), LED driver (IC) and optional board (connect to MAIN unit; J). Outputs the data signal to the PLL IC (MAIN unit; IC), D/A converter (MAIN SO unit; IC6) and optional board (connect to MAIN unit; J). EEP Output port for beep sound signal. I/O port for the data signal for the EEP- ESDA ROM (IC) Outputs the clock signal for the EEP- ESCL ROM (IC). Outputs the clock signal for the LCD LSCK driver (IC6, pin 7). Outputs the data signal for the LCD driver (IC6, pin 8). LSO Outputs the strobe signal for the PLL PLST IC (MAIN unit; IC). Outputs the strobe signal for the D/A DAST converter IC (MAIN unit; IC6). Outputs the strobe signal for the EXST expander IC (IC7). Outputs the control signal for the LCD EXOE driver IC (IC6). Outputs the control signal for the power PWON switching circuit (MAIN unit; Q, Q). -

11 CPU-Continued Pin Port number name OPT OPT SI CLI CLO POSW IGSW NOIS CIRQ CCS PTT EPTT HANG AFVI CDEC SDEC OPVV RSSI LVIN Description I/O ports for the optional board control signals. Input port for the clock sigal from the optional board via J. Input port for the cloning signal. Output port for the cloning signal. Input port for the POWER switch. Input port for the remote power control signal from the external connector.(j6) Input port for the dimmer control. Input port for the NOIS signal from the FM IF IC (MAIN unit; IC) for noise squelch operation. Input port for interruption signal from the optional board via J. Outputs chip select signal for the optional board via J. Input port for the PTT switch from microphone. Input port for the PTT switch from the external connector (J6). Low : External PTT switch is ON. Input port for the microphone hanger detection signal. Low : Microphone on hook. Input port for the AF volume control signal (R). High : [VOL] is maximum clockwise. Input port for the CTCSS/DTCS decoding signals. Input port for the single tone decoding signal. Input port for the optional board detection signal. Input port for receiving signal strength level detection. Input port for the PLL lock voltage. -- OUTPUT EXPANDER (MAIN UNIT; IC7) Pin number 6 7 Pin number 8 Port name RXC AFON NWC RMUT TMUT MMUT Port name LIGT LIGT SEG SEG COM COM Description Outputs transmit/receive control signal. High: While receiving. Outputs audio output control signal. High: While receiving. Outputs wide/narrow control signal. High: Wide is selected. Outputs receiving mute control signal. Low: While receiving is muting. Outputs transmitting mute control signal. Low: While transmitting is muting. Outputs the microphone mute control signal. Low: While the microphone is muting. -- LCD DRIVER (FRONT UNIT; IC6) Description Outputs dimmer control signal. High: Dimmter is ON. Outputs backlight control signal. High: acklight is ON. Output LCD segment signals. Output LCD common signals. -

12 SECTION ADJUSTMENT PROCEDURES - PREPARATION When you adjust the contents on pages - and -6, SOFT- WARE ADJUSTMENT, the optional CS-F00 ADJ ADJUST- MENT SOFTWARE (Rev..0 or later), *OPC- JIG CALE (modified OPC- CLONING CALE; see illustration below) are required. SYSTEM REQUIREMENTS IM PC compatible computer with an RS-C serial port (800 bps or faster). Microsoft Windows 9/98 or Windows ME Intel Pentium 00 MHz processor or faster At least 6 M RAM and 0 M of hard disk space pixel display ( pixel display recommended) IM is a registered trademark of International ussiness Machines Corporation in the U.S.A. and other countries. Microsoft and Windows are registered trademarks of Microsoft Corporation in the U.S.A. and other countries. Screen shots produced with permission from Microsoft Corporation. All other products or brands are registered trademarks or trademarks of their respective holders. ADJUSTMENT SOFTWARE INSTALLATION q oot up Windows. - Quit all applications when Windows is running. w Insert the CS-F00 into the appropriate CD drive. e Select Run from the [Start] menu. r Type the setup program name using the full path name, then push [Enter] key. (ex. D:\CSF00ADJ\Setup.exe) t Follow the prompts. y Program group CS-F00 ADJ appears in the Programs folder of the [Start] menu. STARTING SOFTWARE ADJUSTMENT q Connect IC-F0 and PC with *OPC- JIG CALE. w Turn the transceiver power ON. e oot up Windows, and click the program group CS-F00 ADJ in the Programs folder of the [Start] menu, then CS-F00 ADJ s window appears. r Click Connect on the CS-F00 ADJ s window, then appears IC-F0 s up-to-date condition. t Set or modify adjustment data as desired. *OPC- (JIG CALE) Add a jumper wire here OPC- (Cloning cable) PTTE PTT MIC MICE PTT switch + Audio generator 00 Hz to khz Electrolytic capacitor 7 F AC millivoltmeter -

13 REQUIRED TEST EQUIPMENT EQUIPMENT GRADE AND RANGE EQUIPMENT GRADE AND RANGE DC power supply Output voltage Current capacity :. V DC : A or more Audio generator Frequency range Measuring range : Hz : 00 mv RF power meter (terminated type) Frequency counter FM deviation meter DC voltmeter Measuring range : 00 W Frequency range : MHz Impedance : 0 Ω SWR : Less than. : Frequency range : MHz Frequency accuracy : ± ppm or better Sensitivity : 00 mv or better Frequency range : DC 00 MHz Measuring range : 0 to ±0 khz Input impedance : 0 kω/v DC or better Standard signal generator (SSG) Oscilloscope AC millivoltmeter External speaker Attenuator Frequency range Output level Frequency range Measuring range Measuring range Input impedance Capacity Power attenuation Capacity : MHz : 0. µv mv ( 7 to 7 dm) : DC 0 MHz : V : 0 mv 0 V : Ω : 7 W or more : 0 or 0 d : 0 W or more CONNECTIONS CAUTION: DO NOT transmit while the SSG is connected to the antenna connector. Standard signal generator 7 to 7 dm (0. V to mv) Personal computer FM deviation meter (DC measurable) Attenuator 0 d or 0 d RF power meter 0 / 0 W to the antenna connector Frequency counter to an RS-C port DC power supply. V / A to DC cable D9 female plug to the MIC connector RS-C cable (straight) *OPC- (JIG CALE) Audio generator AC millivoltmeter -

14 SCREEN DISPLAY EXAMPLE CS-F00 ADJ Rev..0 File Option COM : OPEN Connect Reload (F) Disp para [A / D] VIN : 78 : h : 9.96 V TEMPS : 77 : h : 6. C LVIN : 76 : 0h :. V SD : : 7h : 0. V [D / A] PF T : 97 : h : 0.98 V T/POW : 7 : h : 0.98 V REF : : Dh : 0.88 V MOD AL : 9 : 6h :.8 Dev : 0 : 00h : 0.00 V CTCSS : 7 : AEh :. V SQL Lev : 0 : 00h : 0.00 AGC : : FFh :.00 V CH No. : 0 RX Freq = , TX Freq = < RF Power: High Mode: Wide Power (Hi) : 98 [ # # # # # # # # # # # # # # # # # ] Power (L) : [ # # # # # # # # # ] Power (L) : [ # # # # ] AL W : [ # # # # # # # # # # # ] AL Ratio : 8 [ # # # # # # # # # ] MOD W : [ # # # # # # # # # # # # # # # # # ] MOD Ratio : [ # # # # # # # # # ] CTCS/DTCS : 86 [ # # # # # ] SQL : 0 [ # # # # # # # # # # # # # # # ] PF ALL : [Enter] to sweep PF T : [ # # # # # # # # # # # ] [Enter] to sweep PF T : [ # # # # # # # # # ] [Enter] to sweep TXF : [Enter] to start S-Meter : [Enter] to start NOTE: The above values for settings are example only. Each transceiver has its own specific values for each setting : Transceiver s connection state : Reload adjustment data : Receive sensitivity measurement : Connected DC voltage : PLL lock voltage : Operating channel select : RF output power : Modulation balance 9 : FM deviation 0 : CTCSS/DTCS deviation : Squelch level : Receive sensitivity (automatically) : Receive sensitivity (manually) : Reference frequency : S-meter 6 : Adjustment items -

15 - PLL ADJUSTMENT ADJUSTMENT ADJUSTMENT CONDITIONS UNIT MEASUREMENT LOCATION VALUE ADJUSTMENT UNIT ADJUST PLL LOCK VOLTAGE Operating freq. : MHz Receiving MAIN Connect a digital multimeter or an oscilloscope to the check point, LV.. V MAIN C Output power Transmitting : Low.6 V C Operating freq. : MHz Receiving 0.9. V Verify Output power Transmitting : Low 0.8. V DC power supply. V / A C PLL lock voltage adjustment for RX LV PLL lock voltage check point C PLL lock voltage adjustment for TX -

16 - SOFTWARE ADJUSTMENT Select an operation using [ ] / [ ] keys, then set specified value using [ ] / [ ] keys on the connected computer keyboard. ADJUSTMENT REFEREE FREQUEY [TXF] OUTPUT POWER [Power (Hi)] [Power (L)] [Power (L)] FM DEVIATION [MOD W] [MOD Ratio] MODULATION ALLAE [AL W] ADJUSTMENT CONDITION Operating freq. : MHz Output power : Low Connect the RF power meter or 0 Ω dummy load to the antenna connector. Transmitting Operating freq. :.000 MHz Output power : High Transmitting Output power : Low Transmitting Output power : Low Transmitting Operating freq. :.000 MHz Output power : Low IF bandwidth : Wide Connect an audio generator to the [MIC] jack through the JIG cable and set as:.0 khz/0 mvrms Set an FM deviation meter as: HPF : OFF LPF : 0 khz De-emphasis: OFF Detector : (P P)/ Transmitting IF bandwidth : Narrow Transmitting Set to the DTCS set channel, and push [Connect] on the Adjustment software. Operating freq. :.000 MHz Output power : Low Transmitting UNIT Rear panel Rear panel Rear panel Rear panel MEASUREMENT LOCATION Loosely couple a frequnecy counter to the antenna connector. Connect an RF power meter to the antenna connector. Connect an FM deviation meter to the antenna connector through the attenuator. Connect an FM deviation meter with an oscilloscope to the antenna connector through an attenuator. VALUE MHz.0 W ( W type) 0.0 W (0 W type) 0.0 W ( W type).0 W (0 W type). W ( W type).0 W (0 W type) ±. khz [N/W] ±. khz [N/M] ±. khz Set to square wave form [AL Ratio] IF bandwidth Transmitting : Narrow CTCSS/DTCS DEVIATON [CTCS/DTCS] Operating freq. :.000 MHz Output power : Low IF bandwidth : Wide CTCSS :. Hz DTCS code : 007 Set the FM deviation meter as: HPF : OFF LPF : 0 khz De-emphasis: OFF Detector : (P P)/ No audio applied to the [MIC] connector. Transmitting Rear panel Connect an FM deviation meter to the antenna connector through the attenuator. ±0.7 khz [N/W] ±0.6 khz [N/W] -

17 SOFTWARE ADJUSTMENT continued Select an operation using [ ] / [ ] keys, then set specified value using [ ] / [ ] keys on the connected computer keyboard. ADJUSTMENT RX SENSITIVITY [PF T], [PF T] SQUELCH LEVEL [SQL] S-METER [S-METER] (S LEVEL) (S LEVEL) ADJUSTMENT CONDITION Operating freq. : MHz IF bandwidth : Wide Connect a standard signal generator to the antenna connector and set as: Frequency : MHz Level : 0 µv* ( 87 dm) Modulation : khz Deviation : ±. khz [N/W] ±.8 khz [N/M] Receiving Operating freq. : MHz IF bandwidth : Narrow Connect an SSG to the antenna connector and set as: Frequency : MHz Level : 0. µv* ( dm) Modulation : khz Deviation : ±.7 khz Receiving Operating freq. : MHz IF bandwidth : Wide Connect an SSG to the antenna connector and set as: Frequency : MHz Level : µv* ( 8 dm) Modulation : khz Deviation : ±. khz [N/W] ±.8 khz [N/M] Receiving Set an SSG as: Level : 0. µv* ( dm) UNIT MAIN Rear panel MEASUREMENT LOCATION Connect a SINAD meter with a Ω load to the external [SP] jack. CONVENIENT: The PF T PF T can be adjusted automatically. q-: Set the cursol to PF ALL on the adjustment program and then push [ENTER] key. q-: The connected PC tunes PF T, PF T to peak levels. or w-: Set the cursol to PF T or PF T as desired. w-: Push [ENTER] key to start tuning. w-: Repeat w- and w- to perform additional PF tuning. Connect a SINAD meter with a Ω load to the external [SP] jack. *The output level of the standard signal generator (SSG) is indicated as the SSG s open circuit. VALUE Minimum distortion level Set SQL level to close squelch. Then set SQL level at the point where the audio signals just appears. Adjusting S and S s S-meter level automatically when push the return key on the key board. - 6

18 SECTION 6 PARTS LIST [FRONT UNIT] REF ORDER IC 0060 S.IC HD6687AFP (FX-6A) IC S.IC S-809CNMC-G9C-T IC S.IC HN8X6TI IC 0000 S.IC NJM90V-TE IC S.IC LC78W Q Q Q Q DESCRIPTION S.TRANSISTOR SC6-L (TE8R) S.TRANSISTOR DTCTUA T S.TRANSISTOR DTCEUA T S.TRANSISTOR DTCTUA T06 D S.ZENER MA806-M (TX) D S.ZENER MA806-M (TX) D S.ZENER MA806-M (TX) D S.DIODE MA77 (TX) D S.DIODE MAS-(TX) X S.XTAL CR-0 ( MHz+) L S.COIL MLF608E 00K-T L S.COIL NL 08T-R0J R S.RESISTOR ERJGEJ 8 X (80 Ω) R S.RESISTOR ERJGEJ 8 X (80 Ω) R S.RESISTOR ERJGEJ 7 X (70 Ω) R S.RESISTOR ERJGE R S.RESISTOR ERJGEJ 7 X (.7 kω) R VARIALE EVU-FKFK (0K) R S.RESISTOR ERJGEJ 0 X ( kω) R S.RESISTOR ERJGEJ 0 X ( kω) R S.RESISTOR ERJGEJ 0 X (00 kω) R S.RESISTOR ERJGEJ 0 X (00 kω) R S.RESISTOR ERJGEJ 8 X (80 kω) R S.RESISTOR ERJGEJ 6 X (6 kω) R S.RESISTOR ERJGEJ X ( kω) R S.RESISTOR ERJGEJ 7 X (7 kω) R S.RESISTOR ERJGEJ 7 X (7 kω) R S.RESISTOR ERJGEJ X ( kω) R S.RESISTOR ERJGEJ 7 X (7 kω) R S.RESISTOR ERJGEJ 7 X (7 kω) R S.RESISTOR ERJGEJ 7 X (.7 kω) R S.RESISTOR ERJGEJ 8 X (8 kω) R S.RESISTOR ERJGEJ X (0 kω) R S.RESISTOR ERJGEJ 0 X (00 kω) R S.RESISTOR ERJGEJ 7 X (7 kω) R S.RESISTOR ERJGEJ X ( kω) R S.RESISTOR ERJGEJ X ( kω) R S.RESISTOR ERJGEJ 68 X (68 kω) R S.RESISTOR ERJGEJ 68 X (68 kω) R S.RESISTOR ERJGEJ 68 X (68 kω) R S.RESISTOR ERJGEJ 68 X (68 kω) R S.RESISTOR ERJGEJ 68 X (68 kω) R S.RESISTOR ERJGEJ 7 X (7 kω) R S.RESISTOR ERJGEJ 0 X (0 kω) R S.RESISTOR ERJGEJ 9 X (9 kω) R S.RESISTOR ERJGEJ X ( kω) R S.RESISTOR ERJGEJ X (0 kω) R S.RESISTOR ERJGEJ 00 X (0 Ω) R S.RESISTOR ERJGEJ 0 X ( MΩ) R S.RESISTOR ERJGEJ X ( kω) R S.RESISTOR ERJGEJ X ( kω) R S.RESISTOR ERJGEJ X ( kω) R S.ARRAY EX0JX R S.RESISTOR ERJGEJ 0 X (00 kω) R S.RESISTOR ERJGEJ 0 X ( kω) R S.ARRAY EX0JX R S.ARRAY EX-VV 0JV ( kω) R S.ARRAY EX0JX R S.RESISTOR ERJGEJ 0 X ( MΩ) R S.RESISTOR ERJGEJ 0 X (0 kω) R S.TRIMMER RV-0 (RH0AAX0FC) 0 A: [F0] : [F] and [F] C: IC-F0 for [EUR] D: IC-F0 for [GEN] E: IC-F0 for khz F: IC-F0 for 0 khz [FRONT UNIT] REF ORDER DESCRIPTION R S.RESISTOR ERJGEJ 0 X (00 kω) R S.RESISTOR ERJGEJ 0 X ( kω) R S.RESISTOR ERJGEJ 0 X (0 kω) R S.RESISTOR ERJGEJ 0 X (0 kω) R S.RESISTOR ERJGEJ 0 X (0 kω) R S.RESISTOR ERJGEJ 0 X (0 kω) R S.RESISTOR ERJGEJ 0 X (0 kω) R S.RESISTOR ERJGEJ 0 X ( kω) R S.RESISTOR ERJGEJ X (. kω) R S.RESISTOR ERJGEJ 7 X (7 kω) R S.ARRAY EX-VV 0JV ( kω) R S.RESISTOR ERJGEJ 0 X (00 kω) R S.RESISTOR ERJGEJ 0 X (00 kω) R S.RESISTOR ERJGEJ 0 X (00 kω) R S.RESISTOR ERJGEJ 0 X (00 kω) R S.RESISTOR ERJGEJ 0 X (00 kω) R S.RESISTOR ERJGEJ 0 X (00 kω) R S.RESISTOR ERJGEJ 0 X (00 kω) R S.RESISTOR ERJGEJ 0 X (00 kω) R S.RESISTOR ERJGEJ 0 X (00 kω) R S.RESISTOR ERJGEJ 0 X (00 kω) R S.RESISTOR ERJGEJ 9 X (90 kω) C S.CERAMIC ECJ0EH68K C S.CERAMIC ECJ0ECH70J C S.CERAMIC ECJ0ECH70J C S.CERAMIC ECJ0ECH70J C S.CERAMIC ECJ0ECH70J C S.CERAMIC ECJ0ECH70J C S.CERAMIC ECJ0ECH70J C S.CERAMIC ECJ0EE0K C S.CERAMIC ECJ0EE0K C S.CERAMIC ECJ0EE0K C S.CERAMIC ECJ0ECH70J C S.CERAMIC ECJ0EE0K C S.CERAMIC ECJ0EE0K C S.CERAMIC ECJ0ECK C S.CERAMIC ECJ0EA0K C S.CERAMIC ECJ0EE8K C S.CERAMIC ECJ0EA0K C S.CERAMIC ECJ0EH7K C S.CERAMIC ECJ0EE6K C S.CERAMIC ECJ0ECH8J C S.CERAMIC ECJ0EC8K C S.CERAMIC ECJ0ECH680J C S.CERAMIC ECJ0EC0K C S.CERAMIC ECJ0EA0K C S.CERAMIC ECJ0EE7K C S.CERAMIC ECJ0EA0K C S.TANTALUM TEMSVA 0J 06M8L C S.CERAMIC ECJ0EA7K C S.CERAMIC ECJ0ECH0J C S.CERAMIC ECJ0ECH0J C S.CERAMIC ECJ0ECH680J C S.CERAMIC ECJ0EE7K C S.CERAMIC ECJ0EA0K C S.CERAMIC ECJ0EA0K C S.CERAMIC ECJ0ECH70J C S.CERAMIC ECJ0ECH70J C S.CERAMIC ECJ0EE0K C S.CERAMIC ECJ0ECH70J C S.CERAMIC ECJ0ECH70J C S.CERAMIC ECJ0ECH70J C S.CERAMIC ECJ0ECH70J C S.CERAMIC ECJ0EA0K C S.CERAMIC ECJ0EA0K C S.CERAMIC ECJ0EA7K C S.CERAMIC ECJ0EE0K C S.CERAMIC ECJ0EA0K C S.CERAMIC ECJ0EA0K C S.CERAMIC ECJ0EE0K C S.CERAMIC ECJ0ECH70J C S.CERAMIC ECJ0ECH70J C S.CERAMIC ECJ0ECH70J C S.CERAMIC ECJ0ECH70J S.=Surface mount 6 -

19 [FRONT UNIT] REF ORDER J CONNECTOR <KIN> J S.CONNECTOR 0FLT-SM-T DS S.LED SML-YTT86 DS S.LED SML-YTT86 DS S.LED SML-YTT86 DS S.LED SML-YTT86 DS S.LED SML-YTT86 DS S.LED SML-YTT86 DS S.LED SML-YTT86 DS S.LED SML-YTT86 DS S.LED SML-YTT86 DS LCD L-0607TAY SP 0000 SPEAKER C0S00- W CALE OPC-06 EP PC 90D EP LCD CONTACT SRCN-6-SP-N-W [MAIN UNIT] REF ORDER DESCRIPTION DESCRIPTION IC S.IC TA6FN (D,EL) IC S.IC TA7S0F (TE8R) IC IC S-AV (I) 0000 IC S-AV (I) A IC S.IC MA0PFV-G-ND-ER IC 0000 S.IC NJM90V-TE IC S.IC M66FP-60C IC IC LAA IC S.IC TA7808F (TE6L) IC S.IC AN78L0M-(E) IC S.IC U066CFV-E IC S.IC TA7S0F (TE8R) IC S.IC NJM90V-TE IC S.IC U09CFV-E [MAIN UNIT] REF Q8 ORDER DESCRIPTION S.TRANSISTOR SC- (TE8R) D S.DIODE SS7-TL D S.DIODE UM90F A only D DIODE XA07 only D S.VARICAP HVC7TRF D S.DIODE UM90F D S.DIODE MA77 (TX) D S.DIODE MAS78-(TX) D S.VARICAP HVC7TRF D S.VARICAP HVC0TRF D S.VARICAP HVC0TRF D S.DIODE SS7-TL D S.DIODE SS7-TL only D S.DIODE MA77 (TX) D S.DIODE MA77 (TX) D S.VARICAP HVC76TRF D S.VARICAP SV9 (TPH) D S.DIODE MAS-(TX) D S.VARICAP HVC6TRF D DIODE DSAA D S.DIODE DA TL D S.DIODE MAS-(TX) D S.DIODE MAS-(TX) D S.DIODE MAS78-(TX) D S.DIODE MAS-(TX) D S.VARICAP HVC76TRF D S.VARICAP HVC76TRF D S.VARICAP HVC76TRF D S.DIODE MAS-(TX) D S.DIODE DANTL D S.DIODE DAP TL D S.DIODE DAP TL D S.DIODE MAS-(TX) D S.DIODE MAS-(TX) D S.DIODE SV07 (TPH) A only D S.DIODE DA TL D S.DIODE MAS-(TX) D S.DIODE SS7-TL FI S.MONOLITH FL- (6.0 MHz) FI CERAMIC ALFYM0F=K FI S.LC NFEPTZE9L (NFM60R0T) FI S.LC NFEPTZE9L (NFM60R0T) FI S.LC NFEPTZE9L (NFM60R0T) only Q S.FET SK89 (TE8R) Q S.FET SK9 (TE8L) Q S.FET SK99-T U7 Q S.TRANSISTOR SC-O (TE8R) Q S.TRANSISTOR DTCEUA T06 Q S.TRANSISTOR SC6-T Q S.TRANSISTOR SC07-O (TE8R) Q 0000 S.TRANSISTOR SC07-O (TE8R) Q 0000 S.TRANSISTOR SC07-O (TE8R) Q S.TRANSISTOR SC6-T R Q S.TRANSISTOR SC6-T R Q S.TRANSISTOR XP (TX) Q S.TRANSISTOR DTCEUA T06 Q S.TRANSISTOR SC6-L (TE8R) Q S.FET SK880-Y (TE8R) Q S.TRANSISTOR SC-O (TE8R) Q S.TRANSISTOR SC6-L (TE8R) only Q S.FET SJ77 (TE6R) Q S.TRANSISTOR DTCEUA T06 Q S.TRANSISTOR SD66 T00Q Q S.TRANSISTOR SA77 T06 Q Q S.TRANSISTOR SA77 T06 Q Q S.TRANSISTOR XP60-(TX).A Q S.TRANSISTOR DTCTUA T06 Q S.TRANSISTOR DTCEUA T06 Q S.FET SJ-GR (TE8R) Q S.TRANSISTOR DTCEUA T06 Q S.TRANSISTOR SC6-L (TE8R) Q S.TRANSISTOR DTC6EK T6 Q S.TRANSISTOR DTCEUA T06 Q S.TRANSISTOR DTCEUA T06 A: [F0] : [F] and [F] C: IC-F0 for [EUR] D: IC-F0 for [GEN] E: IC-F0 for khz F: IC-F0 for 0 khz X S.DISCRIMINATORCDC0KCAY-R0 (CDC0CX) X S.XTAL CR-70 (.00 MHz) L S.COIL AS0807-7N L S.COIL AS0807-7N L S.COIL AS0807-7N L S.COIL TL L S.COIL FHW0HC R0JGT L S.COIL ELJRE 9NJ 9N L S.COIL LQWHN68NJ0L (LQNA 68NJ0) L S.COIL LQWHN68NJ0L (LQNA 68NJ0) L S.COIL LQWHN6NJ0L (LQNA 6NJ0) L S.COIL MLF608A R8K-T L S.COIL LQWHN6NJ0L (LQNA 6NJ0) L S.COIL ELJRE R0J-F L S.COIL ELJFC R0K-F L S.COIL AS0807-7N L S.COIL ELJRE 7NJ-F A only L S.COIL ELJRE 8NJ-F L S.COIL ELJRE 8NJ-F L S.COIL ELJRE 68NJ-F L S.COIL TL 67N L S.COIL TL L S.COIL NL 08T-RJ L S.COIL NL 08T-RJ L S.COIL MLF608A R8K-T L S.COIL LQWHN6NJ0L (LQNA 6NJ0) L S.COIL ELJRE NJ-F L S.COIL MLF608D R8K-T L S.COIL MLF608D RK-T S.=Surface mount 6 -

20 [MAIN UNIT] REF ORDER DESCRIPTION L S.COIL MLF608E 00K-T L S.COIL TL 67N L S.COIL TL N L S.COIL ELJRE 68NJ-F L S.COIL MLF608A R7K-T L S.COIL ELJRE 7NG-F R S.RESISTOR MCR0EZHJ 00 kω R S.RESISTOR MCR0EZHJ 7 Ω (70) R S.RESISTOR MCR0EZHJ 7 Ω (70) R S.RESISTOR ERJGEYJ 7 V (70 Ω) R S.RESISTOR ERJGEYJ 0 V (0 kω) A S.RESISTOR ERJGEYJ 7 V (7 kω) R S.RESISTOR ERJGEYJ 7 V (7 kω) S.RESISTOR ERJGEYJ V ( kω) A R S.RESISTOR ERJGEYJ 7 V (70 Ω) R S.RESISTOR ERJYJ0U (00 Ω) R S.RESISTOR ERJGEYJ 0 V (0 kω) only R S.RESISTOR ERJGEYJ 7 V (70 kω) only R S.RESISTOR ERJGEYJ 0 V (00 kω) R S.RESISTOR ERJGEJ 00 X (0 Ω) R S.RESISTOR ERJGEYJ 0 V (00 kω) R S.RESISTOR ERJGEYJ 0 V (0 kω) R S.RESISTOR ERJGEYJ 7 V (70 kω) R S.RESISTOR ERJGEYJ 7 V (70 Ω) R S.RESISTOR ERJGEYJ 0 V (00 Ω) R S.RESISTOR ERJGEYJ R0 V ( Ω) R S.RESISTOR ERJGEYJ 0 V (00 kω) R S.RESISTOR ERJGEYJ 7 V (70 Ω) C S.RESISTOR ERJGEYJ 7 V (70 Ω) D, R S.RESISTOR ERJGEYJ V (0 kω) R S.RESISTOR ERJGEYJ 0 V (0 kω) R S.RESISTOR ERJGEYJ V (0 kω) R S.RESISTOR ERJGEYJ 7 V (70 Ω) R S.RESISTOR ERJGEYJ 7 V (70 Ω) R S.RESISTOR ERJGEYJ 0 V ( Ω) R S.RESISTOR ERJGEYJ 0 V (00 Ω) R S.RESISTOR ERJGEYJ 0 V (00 Ω) R S.RESISTOR ERJGEYJ V (0 Ω) R S.RESISTOR ERJGEYJ V (0 Ω) R S.RESISTOR ERJGEYJ 0 V (00 kω) R S.RESISTOR ERJGEYJ 0 V (00 Ω) R S.RESISTOR ERJGEYJ 9 V (.9 kω) R S.RESISTOR ERJGEYJ 7 V (.7 kω) E, S.RESISTOR ERJGEYJ 7 V (.7 kω) F R S.RESISTOR ERJGEYJ 0 V (00 kω) R S.RESISTOR ERJGEYJ 70 V (7 Ω) R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ 0 V (00 kω) R S.RESISTOR ERJGEYJ 7 V (70 Ω) R S.RESISTOR ERJGEYJ V (0 kω) R S.RESISTOR ERJGEYJ V (0 kω) R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ 8 V (80 kω) only R S.POSISTOR PRF8D7QR only R S.RESISTOR ERJGEYJ 0 V (0 kω) R S.RESISTOR ERJGEYJ 6 V (60 kω) A S.RESISTOR ERJGEYJ 0 V (00 kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ R0 V ( Ω) A S.RESISTOR ERJGEYJ V (0 Ω) R S.RESISTOR ERJGEYJ 8 V (8. kω) S.RESISTOR ERJGEYJ 0 V (0 kω) A R S.RESISTOR ERJGEYJ 7 V (.7 kω) R S.RESISTOR ERJGEYJ V (0 kω) R S.RESISTOR ERJGEYJ 0 V (0 kω) R S.RESISTOR ERJGEYJ 0 V (00 Ω) R S.RESISTOR ERJGEYJ 0 V (0 kω) S.RESISTOR ERJGEYJ 8 V (8 kω) A R S.RESISTOR ERJGEYJ 0 V (00 Ω) R S.RESISTOR ERJGEYJ 70 V (7 Ω) R S.RESISTOR ERJGEYJ 60 V (6 Ω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ 0 V (00 Ω) A S.RESISTOR ERJGEYJ 680 V (68 Ω) R S.RESISTOR ERJGEYJ 0 V (0 kω) R S.RESISTOR ERJGEYJ 7 V (.7 kω) A: [F0] : [F] and [F] C: IC-F0 for [EUR] D: IC-F0 for [GEN] E: IC-F0 for khz F: IC-F0 for 0 khz [MAIN UNIT] REF ORDER DESCRIPTION R S.RESISTOR ERJGEYJ 0 V (00 Ω) R S.RESISTOR ERJGEYJ 0 V (00 Ω) R S.RESISTOR ERJGEYJ 0 V (00 Ω) R S.RESISTOR ERJGEYJ V (0 kω) R S.RESISTOR ERJGEYJ V (0 kω) R S.RESISTOR ERJGEYJ 7 V (70 Ω) R S.RESISTOR ERJGEYJ 0 V (0 kω) R S.RESISTOR ERJGEYJ 0 V ( kω) R S.RESISTOR ERAYED R S.RESISTOR ERJGEYJ 0 V ( kω) R S.RESISTOR ERAYED R S.RESISTOR ERAYED 9V R S.RESISTOR ERAYED 9V R S.RESISTOR ERJGEYJ V (0 kω) R S.RESISTOR ERJGEYJ 0 V (0 kω) R S.RESISTOR ERJGEYJ 7 V (7 kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ 0 V (00 kω) R S.RESISTOR ERJGEYJ 0 V ( kω) R S.RESISTOR ERJGEYJ V (0 Ω) C S.RESISTOR ERJGEYJ V (0 Ω) D, R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ R0 V ( Ω) R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ 0 V ( kω) R S.RESISTOR ERJGEYJ 0 V (0 kω) R S.RESISTOR ERJGEYJ 0 V ( kω) R S.RESISTOR ERJGEYJ V (0 kω) R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ 7 V (7 kω) R S.RESISTOR ERJGEYJ 8 V (8 kω) R S.RESISTOR ERJGEYJ 70 V (7 Ω) R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ 7 V (7 kω) R S.RESISTOR ERJGEYJ V (. kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ 9 V (.9 kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ 8 V (80 kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ 6 V (.6 kω) R S.RESISTOR ERJGEYJ 0 V (0 kω) R S.RESISTOR ERJGEYJ 7 V (7 kω) R S.RESISTOR ERJGEYJ 6 V (.6 kω) R S.RESISTOR ERJGEYJ 0 V (00 kω) R S.RESISTOR ERJGEYJ 7 V (.7 kω) R S.RESISTOR ERJGEYJ 0 V (00 kω) R S.RESISTOR ERJGEYJ 7 V (70 Ω) R S.RESISTOR ERJGEYJ 9 V (9 kω) R S.RESISTOR ERJGEYJ 0 V (0 kω) R S.RESISTOR ERJGEYJ 0 V (00 Ω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ 8 V (80 kω) R S.RESISTOR ERJGEYJ 7 V (7 kω) R S.RESISTOR ERJGEYJ 7 V (70 kω) R S.RESISTOR ERJGEYJ 0 V (0 kω) R S.RESISTOR ERJGEYJ 68 V (68 kω) R S.RESISTOR ERJGEYJ 0 V (00 kω) R S.RESISTOR ERJGEYJ 0 V (00 kω) R S.RESISTOR ERJGEJ 0 X ( kω) R S.ARRAY EX0JX R S.RESISTOR ERJGEJ 0 X ( kω) R S.RESISTOR ERJGEJ 0 X ( kω) R S.RESISTOR ERJGEJ 0 X ( kω) R S.RESISTOR ERJGEJ 0 X ( kω) R S.ARRAY EX0JX R S.ARRAY EX0JX R S.ARRAY EX0JX R S.ARRAY EX0JX R S.RESISTOR ERJGEYJ 7 V (.7 kω) R S.RESISTOR ERJGEYJ 0 V (0 kω) R S.RESISTOR ERJGEYJ V (0 kω) R S.RESISTOR ERJGEYJ V ( kω) R S.RESISTOR ERJGEYJ V (0 kω) R S.RESISTOR ERJGEYJ 0 V (00 kω) R S.RESISTOR ERJGEYJ 0 V (0 kω) R S.RESISTOR ERJGEYJ 7 V (70 Ω) R S.RESISTOR ERJGEYJ V (0 kω) R S.RESISTOR ERJGEYJ V (0 kω) R S.RESISTOR ERJGEYJ 7 V (70 kω) R S.RESISTOR ERJGEYJ V (. kω) S.=Surface mount 6 -

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