Maximizing the potential of the platform FPGA for high performance computing. Gordon Brebner Xilinx Research Labs

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1 Maximizing the potential of the platform FPGA for high performance computing Gordon Brebner Xilinx Research Labs

2 What this talk is about Background summary of raw FPGA capabilities Barriers to access Hardware and Software words considered harmful Domain specificity Hyper-programmable network on chip Interface-centric design actually, non processor-centric design Example: high performance networking systems

3 Comparison of raw performance Pentium Virtex-II Pro Virtex Computation (GOPS) Memory Bandwidth (Gbps) I/O Bandwidth (Gbps) I/O Bandwidth Memory Bandwidth Virtex-II Pro Virtex 4 Pentium Computation

4 The Xilinx Virtex-4 FPGA 200,000 Logic Cells Gbps Transceivers 0-24 Channels 500 MHz Differential Clocking 500 MHz BRAM with FIFO & ECC Up to 10Mb AES Design Security >1 Gbps I/O PowerPC Processor with APU 1-2 PPCs/Device 10/100/1000 Ethernet MAC 2-4 MACs 500 MHz DSP Slice 256 GMAC/s bandwidth

5 Xilinx and HPC Berkeley BEE2 scalable system contains five Xilinx XC2VP70 FPGAs per node FPGA High Performance Computing Alliance (Scotland) Mini-system based on Virtex-II Pro Full system to be based on Virtex-4

6 Barriers to access FPGA use normally features a hardware design experience due to history as ASIC substitutes deterrent to domain experts and/or software guys Attempting directly to port domain-specific and/or software languages over often results in very inefficient FPGA use a further deterrent Inclusion of the new extra embedded features in platform FPGAs may feel grafted on to the design experience yet another deterrent

7 No need for a holy grail The key attribute of platform FPGA technology: Everything is programmable but with different styles of programming So FPGAs can deliver different micro-architectures to different domains, indeed to different applications These can support different high level languages These should influence how FPGAs are viewed as part of particular overall system architectures Programmability at design time, execution time, and during execution reconfigurable computing

8 Hardware and Software These words perpetuate legacy thinking: hardware : hardness, data flow, architectures software : softness, control flow, algorithms Hardware/software co-design : Collision of the two legacy worlds Should now think in terms of domain-specific: Algorithm/architecture co-design Sometimes data-centric, sometimes control-centric and most things are soft

9 Domain specificity Three major digital domains of current research interest: stream-based: digital signal processing (DSP) pipeline-style architectures, natural for FPGAs block-based: message processing (MP) threaded and other architectures, natural for platform FPGAs processor-based: data processing (DP) shrink of processor-centric system-on-board Where might high performance reconfigurable computing fit into the domain-specific picture as a fourth domain perhaps?

10 Characteristics of the gang of three Dominant system flow Raw data complexity Input / output relationship Scope for concurrency Randomness of data access DSP Stream-based MP Block-based DP Processor-based Synchronous data flow Asynchronous data flow Control flow Numerical Nested records, Complex data values but no iterators types Size similar; Size similar; Size dissimilar; Complex ops Simple ops Complex ops High High-medium Low Low Low-medium High

11 Hyper-programmability Application description Domain-specific data model and programming language API to access features of the domain-specific micro-architecture Hyper-programmed soft micro-architecture Efficiently exploit logic, immersed IP, processing blocks, memory, interconnection, and programmability of FPGA

12 Programmable network on chip Hyper-programmed soft micro-architecture: Program heterogeneous on-chip components Program interconnections between components Can build: Diverse range of processing elements and data paths Diverse memory architectures Can deliver a programmable micro-architecture that provides an impedance match between a specific application and the underlying FPGA technology

13 Interface-centric design Paradigm suitable for use in the networking and DSP domains, where required behavior at external interfaces drives the system architecture In particular, embedded processors (or external processors in fact) become assistants in the outside-in model, rather than the central focus Thus, processors are responding to events at their interfaces to provide programmed algorithmic support to the network on chip

14 Question for HPC applications Obvious starting point for FPGA incorporation is a processor-centric hardware accelerator model Are there good examples where the required high performance is relative to interfaces, and so a more interface-centric model might yield benefits? Key message is that the capabilities of an FPGA should not be assumed a priori to be secondary to the capabilities of a processor

15 High performance networking research at Xilinx Establish unique Xilinx FPGA advantages for networking: over ASICs and ASSPs (e.g. flexibility, time to market) over NPUs and microprocessors (e.g. scalability, flexibility) by demonstrating cheap and easy access combining: exploitation of the programmability of the FPGA design flows to hook in software guys new use models for platform FPGA resources Then to look beyond current high-speed networking focus to future low-cost pervasive networking

16 Flexibility and scalability Packet processing per second 20m IP packets routed per sec. Scalable in performance, and re-usable solution FPGA Network processor (NPU) Next fixed architecture Next fixed architecture No re-use, architecture dependent Flexible system on chip used for tailored system architectures Processor / memory bottlenecks worsen

17 Main projects in a nutshell Pebbles: stitch together wide range of blocks programmable modules and subsystems together <thread name="rx_thread"> <useinterface intname="rx" name="mygmac" p <usemem intname="put" name="ethrecv_buf" <variables> <internal name="len" width="16"/> <internal name="addr" width="11"/> </variables> <states start="startstate" altstart="rx_datavali <state name="startstate"> <operation op="write_data" params= P <operation op="assign" params="addr, 4" <transition next="writedata"/> </state> PitStop: create high speed packet processing subsystems Software-style descriptions mapped to IP blocks PitStop

18 The pit stop analogy PitStop Packet is the racing car Processing elements are the engineers and equipment Lots of concurrent activity, exact tasks determined on a per-packet basis Platform corresponds to the pits Lots of concurrent activity, with many packets being handled at the same time, in different ways

19 Summary of recent results Processing of packets at 1 Gb/s and 10 Gb/s transmission rates, with zero latency possible between store-and-forward packet receipt and transmission Up to 16 concurrent Gb/s ports on a single FPGA device Embedded PowerPC processor used as software assistant for infrequent cases and for algorithmics Design productivity significantly improved working systems in days/weeks rather than months/years Xilinx

20 Conclusions FPGAs have a lot to offer for HPC, rather more than might appear obvious at first sight Need thorough global review of possibilities for programmable system architectures, beyond the immediate approach of scaling down conventional processor-centric architectures Devising appropriate design flows and associated tools is the essential ingredient, including thinking outside the box to derive full benefits

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