TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS FOR DIGITAL COMMUNICATIONS

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1 TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS FOR DIGITAL COMMUNICATIONS Tsung-Heng Tsai, Paul J. Hurst, and Stephen H. Lewis Solid-State Circuits Research Laboratory Departent of Electrical and Coputer Engineering University of California, Davis USA ABSTRACT Techniques to overcoe the errors caused by the offset, gain, and saple-tie isatches aong tieinterleaved analog-to-digital converters (ADCs) in highspeed digital counication systes are presented. The errors introduced by these isatches are adaptively corrected using digital signal processing blocks. Sapletie errors are corrected by odifying the operation of the existing adaptive receive equalizer to reduce the hardware overhead. Siulations are presented that show that the gain, offset, and saple-tie isatches are corrected by the adaptive loops. KEY WORDS Analog circuits, digital signal processing, counication systes, calibration 1. Introduction Digital processing of analog signals has becoe an attractive option in any applications, such as digital counications, storage channels, and wavefor acquisition. A key advantage of digital processing blocks is that they can be easily scaled as CMOS technology advances. In a digital counication receiver, an 'alldigital' receiver requires a high-resolution analog-todigital converter (ADC) to digitize the received signal. A block diagra of a candidate receiver is shown in Fig. 1. The ADC is followed by a digital autoatic gain control (AGC) block, which aplifies the signal, an adaptive equalizer, which copensates for intersybol interference (ISI) introduced by the channel, and a digital interpolated tiing recovery (ITR) block, which uses interpolation to recover saples at the sybol rate fro the slightly oversapled signal fro the ADC [1]. The resulting signal is sliced to produce an estiate of the transitted data. The resolution required in the ADC will be typically at least 10 bits, because it ust not overload when receiving a strong signal and ust give a reasonable output signal-to-noise-and-distortion ratio (SNDR) when receiving a weak signal. For exaple, if the input signal range is 40 db, the peak-to-rs ratio of the receive signal is 2, and the desired SNDR is 20 db, then an ADC with 11 bits of resolution is required. While high-resolution ADCs can be built, their conversion rates are liited. Fig. 1: Block diagra of a receiver. To achieve high resolution at speeds near and above 1Gb/s, for exaple, ultiple ADCs could be tieinterleaved, as shown in Fig. 2 [2-10]. Here, ultiple parallel ADCs are used in a parallel tie-interleaved array. In this structure, each ADC channel saples the input in turn. With M ADC channels operating in parallel, the overall sapling rate increases by the factor M over that of a single channel. However, isatches in gain, offset, and saple tie aong the tie-interleaved ADCs generate undesired spectral coponents [2-10] and degrade the SNDR of the syste. Fig. 2: Block diagra of the tie-interleaved ADCs. Digital background calibration has been deonstrated for correcting offset and gain isatches [2-7]. A calibration signal added to the input of the ADC or a rando chopping signal in the saple-and-hold

2 circuit has been used to reove the offset and gain isatches. Previous work regarding saple-tie isatches in parallel channels was reported in [7-9]. In [9], a two-rank saple-and-hold (S/H) structure is used to reduce saple-tie errors. Here, the first S/H ust operate at the overall sapling rate of the converter, which will be difficult at high sapling rates with any ADC channels. In [8], linear interpolation is proposed and relies on oversapling the input signal to accurately estiate the corrected outputs. Without oversapling, the proposed ethod does not work well. In another approach [7], saple tie errors in a two-channel ADC are detected and corrected digitally using a FIR filter. Saple-tie errors are corrected by adaptively adjusting the coefficients of the FIR filter as a function of the detector signal. However, the hardware overhead increases as the required accuracy becoes higher. Also, the published technique works for only two channels. In this paper, techniques to adaptively correct the errors caused by gain, offset, and saple-tie isatches are presented. A front-rank S/H is not required, which allows any ADC channels to be tie interleaved. The offset and gain correction circuits are relatively siple. The correction of saple-tie errors can be perfored using a odified version of the equalizer, which is an existing block in ost digital counication receivers. Hence, the offset, gain, and saple-tie isatches can be corrected with low hardware overhead. 2. Digital Calibration Algoriths Digital adaptive correction loops based on the least eansquare (LMS) algorith [11-12] are used to reduce the effects of offset, gain and saple-tie isatches. The loops operate to iniize the ean-squared value of the slicer error, which is e[n] in Fig. 1. This paper focuses on a baseband receiver. The desired equalizer output is chosen to be a 3-level signal (e.g., a MLT3 signal as used in ethernet [13] or an equalized signal for a Viterbi detector as used in soe agnetic recording channels [14-15]); however, the techniques described will work for any pulse-aplitude odulated signal (including a binary transit signal). The transit data is assued to have been scrabled, so that it has zero ean and its autocorrelation function is an ipulse. The receive input signal is sapled by the ADC at a rate that is soewhat faster than the baud rate, as required by the digital tiing recovery block [1]. A linear odel of the th channel ADC, ADC, with gain A (ideally 1), offset O (ideally 0), and sapletie error Δt (ideally 0) is shown in Fig. 3. Here, q is the quantization error, which is assued to be sall and uncorrelated with the input signal, which is a coon assuption for a ediu- to high-resolution ADC with a busy input. Here is the channel index, while M is the total nuber of ADC channels, and X (i) is the i th saple output of this ADC channel. The tie index for each ADC channel operating at a rate 1/MT is i, and n is the tie index for saples at the overall saple rate of 1/T. Therefore, saple index i in channel corresponds to a saple index of n = im+. T will be assued equal to the bit period in Sections 2A-2C for siplicity. Fig. 3: Linear odel of the th ADC. A. Gain Misatch Calibration To correct the gain isatches aong the ADC channels, an independent AGC is used for each channel. For siplicity here, assue the ADCs are ideal except that they have different gains A (i.e., the ADC offsets and saple-tie errors are zero). Further, assue the channel is ideal and the equalizer is not needed. The gain is adjusted using a digital ultiplier operating on the ADC output saples. An adaptive feedback loop sets the gain K of the AGC in channel to iniize its contribution to the ean-squared error (MSE) across the slicer. The block diagra of the AGC loop for channel is shown in Fig. 4. Under the assuption that the transitted data is rando, the signal statistics at the slicer input are the sae for all channels, and the total effective gain of each ADC channel after its AGC, the product A K, will be the sae for all channels after convergence. With a perfect unity-gain counication channel, A K should equal 1. In this case, the gain K will converge to A 1. In general, K will converge to copensate for the gain of ADC and any loss in the counication channel. is Fig. 4: Block diagra of the AGC loop for channel. The digital update equation for the variable gain K K ( i + 1) = K ( i) + µ G ( i) e ( i) (1) e gain ( i) = aˆ( im + ) G ( i) (2) where i is a saple-tie index for channel. e (i) is the slicer error associated with decisions â(im+) ade every M saple periods using the output of channel. The key to this algorith is that the feedback loop forces the error e to converge to a sall value with a ean of zero.

3 B. Offset Calibration The goal of the offset calibration syste is to cancel the DC offset in each channel. If the offset is cancelled in each channel, then offset isatches are eliinated and all channel offsets are zero. For siplicity, assue the gain isatch has been corrected by the loop described above, and the saple-tie errors are zero. Also, assue the channel is ideal and the equalizer is not needed. The offset cancellation loop for channel is shown in Fig. 5, and the corresponding LMS update equation is: OC ( i + 1) = OC ( i) + µ e ( i) (3) offset In steady state, OC has been adjusted so that the error e has zero ean. The error e is the difference between the slicer output decision and the slicer input. Since the transitted data was scrabled, the data decisions output by each channel have zero ean; therefore, the slicer input (which is the output of the offset cancellation loop) should have zero ean. Therefore, any DC offset in channel has been cancelled by the loop in Fig. 5. Fig. 6: Saple-tie correction. In Fig. 6, the signal Y(n) is fed into an adaptive FIR equalizer that adapts its coefficients to reove any ISI. Through extensive block-diagra or equation anipulations, it can be shown that the filters F (z) and the FIR equalizer in Fig. 6 can be replaced by an adaptive FIR equalizer that has two sets of coefficients; one set is used to produce the equalizer output saples at odd saple ties and the other set used for even saple ties. This leads to the syste shown in Fig. 7. The two sets of equalizer coefficients can be adapted using the LMS algorith to iniize the ean-square value of the slicer error e, which is due to both saple-tie errors and ISI. Such an equalizer requires ore taps than an equalizer that only reoves ISI. Fig. 5: Block diagra of the offset cancellation syste. C. Saple-Tie Error Calibration As shown in Fig. 3, sapling by ADC ideally occurs at ties imt+t, but the actual saples are taken at the ties imt+t+δt, where Δt is the constant sapletie error of the th ADC. Since the gain and offset isatches can be reoved by the correction loops in Sections A and B, gain and offset will be ignored in this section for siplicity. Furtherore, assue for siplicity here that T is the bit period. (This assuption will be reoved in the next section.) To explain the saple-tie correction concept, consider a syste with a two-channel ADC (M=2). A saple-tie error in a channel is equivalent to a tie shift of the input X(t) before a sapler with zero saple-tie error in that channel. The effect of saple-tie errors in the channels can be corrected by adding a filter F (z) in each channel [16]. This is shown in Fig. 6, where each ADC is siply shown as a sapler. The corrected output of the 2 ADC channels is also cobined to for a signal Y(n), which is ideally the input signal X(t) uniforly sapled at a rate 1/T. The filters F (z) would have to adapt to correct for the unknown Δt. Fig. 7: Saple-tie correction using two sets of equalizer coefficients. This concept can be extended to M ADC channels, as shown in Fig. 8. In this general case, an FIR equalizer with M sets of coefficients is needed to both cancel ISI and correct for the M saple-tie errors in the M ADC channels. X(t) t=imt+t+ t1 ADC 1 t=imt+t+ t ADC t=imt+ t M ADC M Y(n) Equalizer w/ M sets of Coeff e Slicer + Σ Fig. 8: Saple-tie correction - general case with M ADCs. In Fig. 8, the j th equalizer coefficient of the th set of equalizer coefficients, C,j, can be adapted by: C ( im + j) e( im ), j [ i + 1] = C, j [ i] + µ eq Y (4) + â

4 Each set of coefficients is updated after every M th decision. The equalizer with M sets of coefficients not only eliinates the ISI introduced by the counication channel, but also corrects the saple-tie errors at the sae tie. Furtherore, the equalizer can be ipleented by swapping coefficient sets each bit period, but only one input delay line and one set of hardware ultipliers are required. D. Calibration of All Channel Misatches In the previous subsections, each calibration approach was considered independently. In practice, all the correction loops ust operate together to cancel the gain, offset, and saple-tie errors. The correction loops are placed as shown in Fig. 9. Initially, ignore the ITR and Linear Interpolator blocks. Gain correction follows each ADC. The gain update equation is as given in (1), but e (i) is a downsapled values of the error e(n) that would be taken fro the slicer in Fig. 9, since a slicer does not exist at the AGC output as in Fig. 4. Also, to assure proper adaptation, signal G is delayed by an aount equal to the latency through the equalizer and ITR before it is ultiplied by e as in (1). The output of the gain correction blocks are cobined to give saples Y(n) that are fed into the equalizer, which corrects for saple-tie errors and cancels ISI in the received signal. Eqn. 4 is used to adapt the M sets of equalizer coefficients, using the slicer error and the saples Y(n). The output of the equalizer is then ultiplexed into M separate signal paths, and the offset cancellation schee of Fig. 5 is applied to each channel. The offset cancellation is perfored after the equalizer rather than before to avoid potential interaction between the offset cancellers and the equalizer. For exaple, if the offset cancellation blocks were before the equalizer, and the equalizer had a zero at DC, then the average DC offset of the channels could not be cancelled since the equalizer would effectively break the forward path of the correction loop at DC. To avoid interaction between the equalizer and gaincorrection blocks, the center equalizer coefficient in each coefficient set is fixed and equal to 1. Therefore, the equalizer coefficients cannot adjust to correct the gain errors. Now, consider the ITR and Linear Interpolation blocks in Fig. 9. These blocks ipleent fully digital tiing recovery in the proposed receiver. The ADC array saples X(t) at a fixed frequency 1/T S, which is slightly higher than the sybol rate 1/T. Each ADC saples at a rate of 1/MT S. The input to all blocks except the slicers are saples at a rate of 1/T S or 1/MT S. A digital interpolated tiing recovery (ITR) loop is used to recover the desired saples [1]. In the ITR, T-spaced ITR output saples are generated by interpolating between T S -spaced saples using the phase inforation fro a phase-tracking loop, which tracks the phase differences between the desired and actual saples. A training sequence is needed to estiate the initial phase offset. The ITR schee used here is explained in detail in [1]. The error signal e generated by the slicer is T- spaced and asynchronous to the saples in the correction loops. A T S -spaced synchronous error signal e is needed for the LMS equations used in the correction loops [Equations (1), (3), and (4)]. Error e is found fro e by linear interpolation. Since an accurate error signal for the LMS updates is not required, a linear interpolation is sufficient. The inaccuracy of this siple linear interpolation does not affect the convergence of the correction loops. 3. Siulation Results Fig. 9: Syste block diagra. Siulations were carried out on the syste in Fig. 9, which has four tie-interleaved ADCs. The syste siulated is a read channel; the ADC input signal is the output of a Lorentzian channel odel [12] T h( T) = π PW 1 t 1+ PW with a 50% pulse width (PW 50 ) of 3T. The siulations use 10-bit ADCs, a 25-tap adaptive equalizer, and a 30-tap adaptive digital interpolation filter in the ITR. The signal is equalized to a 3-level signal, so that the resulting slicer input signal could be processed by a Viterbi detector [14-15] to achieve a lower bit-error rate (BER) than a siple slicer can achieve. Table I gives the coparisons of the overall MSE before and after the calibration loops are enabled for cases with only gain errors, only offset errrors, only sapletie errors, and finally for the case where all errors exist and all calibration loops are operated. Type of Error MSE Calibration Off Calibration On ±10% Gain 22.9 db 44.2 db ±10% Offset 33.1 db 43.3 db ±5% Saple-Tie 22.8 db 43.0 db All errors present 8.9 db 42.9 db Table 1: Coparison of MSEs with calibration Off and On. 2 (6)

5 Fig. 10 shows the plots of the MSE (=E[e(n)] 2 ) without and with the calibration loops running for the case with all errors. In this siulation, large channel isatches were used to clearly show the operation of the correction loops. There are ±10% peak gain isatches, peak DC offsets that are ±10% of the ADC full scale voltage, and ±5% peak saple-tie errors introduced into the four ADC channels. Without calibration, as shown in Fig. 10(a), the channel isatches result in a very poor MSE of -8.9 db, which would lead to an unacceptable BER. After calibration, the MSE is a very low db. This MSE would fall far below the channel noise that exists in practical read channels, which is often -20 to -30 db below the signal. MSE db 0 MSE db Conclusion MSE = -8.9 db Saples n x 10 4 Fig. 10(a): MSE without calibration. MSE = -42.9dB Saples n x 10 4 Fig. 10(b): MSE with calibration. Parallelis can increase the effective throughput of a syste. Unfortunately, tie-interleaved ADC channels introduce errors such as gain, offset, and tiing isatches. As a result, the noise floor is raised and the overall SNDR is reduced. Techniques for iniizing these sources of error in a receiver have been described in this paper. All the corrections are perfored by digital signal processing blocks, which can scale to take advantage of evolving CMOS technologies. The correction of saple-tie errors is achieved by odifying the existing equalizer block to reduce hardware overhead. The techniques presented can be applied to any high speed counication receivers. While 4 ADCs were used in the siulations, these correction schees will work with any nuber of ADC channels. 4. Acknowledgeents This work was supported by NSF Grant CCR and by UC MICRO Grant References: [1] Z. Wu, J. M. Cioffi, & K. D. Fisher, A MMSE interpolated tiing recovery schee for the agnetic recording channel, IEEE International Conference on Counications, 3(6), 1997, [2] C. S. G. Conroy, D. W. Cline, & P. R. Gray, An 8-b 85-MS/s parallel pipeline A/D converter in 1-μ CMOS, IEEE Journal of Solid-State Circuits, 28(4), 1993, [3] A. Petraglia & S. K. Mitra, Analysis of isatch effects aong A/D converters in a tie-interleaved wavefor digitizers, IEEE Trans. Instru. and Meas., 40(5), 1991, [4] K. C. Dyer, D. Fu, S. H. Lewis, & P. J. Hurst, An analog background calibration technique for tieinterleaved analog-to-digital converters, IEEE Journal of Solid-State Circuits, 33(12), 1998, [5] D. Fu, K. C. Dyer, S. H. Lewis, & P. J. Hurst, A digital background calibration technique for tieinterleaved analog-to-digital converters, IEEE Journal of Solid-State Circuits, 33(12), 1998, [6] N. Kurosawa, H. Kobayashi, K. Maruyaa, H. Sugawara, & K. Kobayashi, Explicit analysis of channel isatch effects in tie-interleaved ADC systes, IEEE Transactions on Circuits and Systes I, 48(3), 2001, [7] S. M. Jaal, D. Fu, S. H. Lewis, & P. J. Hurst, A 10- bit 120 Msaple/s tie-interleaved analog-to-digital converter with digital background calibration, IEEE Journal of Solid-State Circuits, 37(12), 2002, [8] H. Jin & E. K. F. Lee, A digital-background calibration technique for iniizing tiing-error effects in tie-interleaved ADCs, IEEE Transactions on Circuits and Systes II, 47(7), 2000, [9] K. Poulton, J. Corcoran, & T. Hornak, A 1-GHz 6-bit ADC syste, IEEE J. Solid-State Circuits, 22 (6), 1987, [10] K. Y. Ki, N. Kusayanagi, & A. A. Abidi, A 10-b 100-MS/s CMOS A/D Converter, IEEE Journal of Solid-State Circuits, 32(3), 1998, [11] B. Widrow & S.Stearns, Adaptive signal processing (Englewood Cliffs, NJ: Prentice-Hall, 1985).

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