Nyquist-Rate A/D Converters. A/D Converter Basics

Transcription

1 Nyquist-ate A/D Converters slide 1 of 23 A/D Converter Basics A/D B out ( b b b N 2 N ) = ± x where V 2 LSB < x < --V 2 LSB ange of valid input values produce the same output signal quantization error. (1) B out 11 V LSB = 1/4 = 1 LSB /4 1/2 3/4 1 V in slide 2 of 23

2 Low-to-Medium Speed, High Accuracy Integrating Oversampling (not Nyquist-rate) Analog to Digital Converters Medium Speed, Medium Accuracy Successive approximation Algorithmic High Speed, Low-to-Medium Accuracy Flash Two-step Interpolating Folding Pipelined Time-interleaved slide 3 of 23 Integrating Converters C 1 S 2 S 1 S 2 Vin S 1 1 V x Comparator Control logic Counter b 1 b 2 b 3 (Vin is held constant during conversion.) b N Clock 1 f = clk T clk B out Low offset and gain errors for low-speed applications Small amount of circuitry Conversion speed is 2 N+1 times 1/T clk slide 4 of 23

3 Integrating Converters V x Phase (I) 3 Phase (II) (Constant slope) 2 1 T 1 Time T 2 (Three values for three inputs) Count at end of T 2 is digital output Does not depend on C time-constant slide 5 of 23 Integrating Converters 0 Hf () 20 db/decade slope (db) Frequency (Hz) (Log scale) Notches the input frequencies which are multiples of 1/T 1 slide 6 of 23

4 Successive-Approximation Converters Sample Start, V D/A = 0, i = 1 > V D/A Yes No Signed input b i = 1 b i = 0 V D/A V D/A + 2 i 1 V D/A V D/A 2 i 1 ( ) Makes use of binary search algorithm /equires N steps for N-bit converter Successively tunes a signal until within 1 LSB of input Medium speed Moderate accuracy i i+ 1 No i N Stop Yes slide 7 of 23 DAC Based Successive-Approximation Successive-approximation register (SA) and control logic b 1 b 2 b N B out V D/A D/A converter Adjust V D/A until within 1 LSB of Start with MSB and continue until LSB found D/A mainly determines overall accuracy Input required slide 8 of 23

5 16C 8C V 0 x 4C Charge edistribution A/D 2C b 1 b 2 b 3 b 4 b 5 s 3 C C s 2 SA 1. Sample mode s 1 V x = s 2 16C 8C 4C 2C C C b b b b b s 3 SA 16C V x 8C = V in 2 4C 2C b 1 b2 b 3 b 4 b 5 s 3 C C s 2 SA s 1 2. Hold mode s 1 3. Bit cycling slide 9 of 23 Charge edistribution A/D Combines, D/A converter, and difference circuit Sample mode: Caps charged to, compar reset. Hold mode: Caps switched to gnd so Vx Vin Bit cycling: Cap switched to. If V x < 0 cap left connected to and bit=1. Otherwise, cap back to gnd and bit=0. epeat N times Cap bottom plates connected to side to minimize parasitic capacitance at V x. Parasitic cap does not cause conversion errors but it attenuates. = V x slide 10 of 23

6 Algorithmic (or Cyclic) A/D Converter Start Sample V =, i = 1 V > 0 Yes No b i = 1 b i = 0 Signed input Operates similar to successiveapprox converter Successive-approx halves ref voltage each cycle Algorithmic doubles error each cycle (leaving ref voltage unchanged) V 2(V /4) V 2(V + /4) i i + 1 No i > N Stop Yes slide 11 of 23 atio-independent Algorithmic Converter Out Vin Cmp Shift register Gain amp X2 Vref /4 Vref /4 Small amount of circuitry reuse cyclically in time equires a high-precision multiply by 2 gain stage slide 12 of 23

7 atio-independent Algorithmic Converter Q1 Verr C1 Q1 C2 Cmp Verr C1 Q1 C2 Cmp 1. Sample remainder and cancel input-offset voltage. Q1 2. Transfer charge Q 1 from C 1 to C 2. C2 C1 Verr Q2 3. Sample input signal with C 1 again after storing charge Q 1 on C 2. Cmp C2 C1 Verr Cmp Q1+Q2 Vout = 2 Verr 4. Combine Q 1 and Q 2 on C 1, and connect C 1 to output. Does not rely on cap matching Sample input twice using C 1 ; hold first charge in C 2 and re-combine with first charge on C 1 slide 13 of V r7 V r6 V r5 V r4 V r3 V r2 V r1 Flash (or Parallel) Converters Over range (2 N 1) to N encoder N digital outputs High-speed Large size and power hungry 2 N comparators Speed bottleneck usually large cap load at input Thermometer code out of comps Nands used for simpler decoding and/or bubble error correction Use comp offset cancellation 2 Comparators slide 14 of 23

8 Issues in Designing Flash A/D Converters Input Capacitive Loading use interpolating arch. esistor-string Bowing Due to I in of bipolar comps force center tap (or more) to be correct. Signal and/or Clock Delay Small arrival diff in clock or input cause errors. (250MHz 8-bit A/D needs 5ps matching for 1LSB) route clock and together with the delays matched [Gendai, 1991]. Match capacitive loads Substrate and Power-Supply Noise = 2 V and 8-bit, 7.8 mv of noise causes 1 LSB error shield clocks and use on-chip supply cap bypass Flashback Glitch at input due to going from track to mode use preamps in comparators and match input impedances slide 15 of 23 Flash Converters Bubble Errors Thermometer code should be Bubble error (noise, metastability) Usually occurs near transition point but can cause gross errors depending on encoder slide 16 of 23

9 V ri (2N 1) to N encoder N digital outputs slide 17 of 23 Two-Step A/D Converters Vin 4-bit MSB A/D V 1 V q 4-bit D/A 16 Gain amp 4-bit LSB A/D First 4 bits Lower 4 bits ( b, b, b, b ) ( b, b, b, b ) High-speed, medium accuracy (but 1 sample latency) Less area and power than flash Only 32 comparators in above 8-bit two-step Gain amp likely sets speed limit Without digital error correction, many blocks need at least 8-bit accuracy slide 18 of 23

10 Digital Error Correction 2 (8-bit accurate) Vin 1 (8-bit accurate) 4-bit MSB A/D (4-bit accurate) V 1 Gain amp 4-bit V q D/A 8 3 (8-bit accurate) (5-bit accurate) Digital delay 5 bits 4 bits D Error correction 5-bit LSB A/D (5-bit accurate) elaxes requirements on input A/D equires a 5-bit 2nd stage since V q increased 8 bits slide 19 of 23 V = V 0.5 V 0.25 V Interpolating A/D Converters V (Overflow) V V V 2c 6 V 2b V 5 2a V Input amplifiers 1 Latch comparators Digital logic b 1 b 2 b 3 b 4 Use input amps to amplify input around reference voltages Latch thresholds less critical Less cap on input (faster than flash) Match delays to es Often combined with folding architecture slide 20 of 23

11 Interpolating Converters 5.0 V 2 V 2b V2c (Volts) V 1 Latch threshold V 2a (Volts) slide 21 of 23 Pipelined A/D Converters b 1 N 1-bit shift register Q N D N Q N-1 D N-2 Q N-1 D N-2 b 2 b N 1 Q 1 D 1 Q 1 Q 1 D 1 D 1 b N 1-bit DAPX 1-bit DAPX 1-bit DAPX 1-bit DAPX (DAPX - digital approximator) Analog pipeline b i V i 1 Cmp /4 /4 2 V i slide 22 of 23

12 Time-Interleaved A/D Converters [Black, 80] f 1 N-bit A/D f 2 f 0 f 3 N-bit A/D Dig. mux Digital output N-bit A/D f 4 N-bit A/D Use parallel A/Ds and multiplex them Tone occurs at fs/n for N converters if mismatched Input critical, others not perhaps different tech for input slide 23 of 23