Lecture 10: Analog/Digital Conversion

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1 Lecture 0: Analog/Digital onversion Example: ounter made from two JK flip-flops. This circuit counts from is the lowest order bit, is the higher order bit. The output is a binary number =. The o s on the clock means that the output transition occurs on the trailing edge of the clock pulse. Output of circuit is most conveniently displayed using a timing diagram: High input J o High J output K K o output Input Output 0 0 high = low = 0 Output 0 0 Time L0: Analog/Digital onversion

2 A few words about clocking the flip-flops and timing of inputs. Setup time: For each type of flip-flop there is a minimum specified time relative to the clock pulse during which time the input(s) to the FF must be stable (i.e. not change logic levels). Hold time: For each type of flip-flop there is a minimum specified time after changes state that the input(s) to the FF must be stable (i.e. not change logic levels). Example: 74LS JK flip-flop (the one we use in lab) This FF changes state () relative to the trailing edge of the clock. The setup time is 0 nsec (x0-8 sec) while the hold time is 0 nsec. The maximum clock speed of this FF is 30 MHz. lock 0 leading edge 5 t setup trailing edge t hold the data on J and K must be stable for at least t setup + t hold. L0: Analog/Digital onversion

3 Sometimes circuits with flip-flops are classified according to how the clock is distributed to the FF's. There are two clocking schemes: Synchronous: All FF's are clocked at the same time. The easiest way to do this is to use one clock and distribute it to all the FF's. Asynchronous: FF's are clocked at different times, usually by different clocks. The previous circuit with two flip-flops was an example of this type of circuit. The first FF was clocked by a clock. The second FF was clocked by the output () of the first FF. L0: Analog/Digital onversion 3

4 +5 +5 clock J S K R A +5 J S K R J S K R J S K R +5 D J A = J = D = + D J = J D = + = K A = K = K = K D = high low clock Divide by 0 ripple down counter (counts from 9 to zero) Asynchronous counter high low high low high low count L0: Analog/Digital onversion = clock for = clock for = clock for D A A A D 4

5 Digital to Analog onversion (DA): There are two simple circuits commonly used to convert a digital signal to an analog voltage. Weighted Resistor Ladder: We assume that the input voltages (,, 3, and 4 ) are logic levels. Let us use TTL levels and assume a high = 3 and a low = 0. The output voltage is given by: R b R out = a " R R R3 R % 4 $ ' # R R R 3 R 4 & R 0 R R R 3 R 4 If we choose the resistors as follows: R0 74 R = R a = kω, R = kω, R 3 = 4 kω, R R 4 = R 0 = 8 kω and R b = 5 kω, R b a we get the following simple relationship for out : out = If in represents a binary number (e.g. 00 = 3 4 with being the highest order bit) the output voltage varies from 0 to 45 olts (remember.. 4 are all either 0 or 3 ) example: the digital input 00 has an analog output of 7 = (3x8 + 3). Unfortunately there are several bad points with this conversion scheme: the output can be a large voltage (e.g. 45 ) circuit needs 5 high precision resistors (expensive) the current (and therefore power) in the resistors varies by a factor of 5 out L0: Analog/Digital onversion 5

6 inary Ladder Network (R-R Network): 3 4 R R R R R R R R 74 out This circuit fixes up many of the problems in previous circuit The output voltage for this circuit is: out = / + /4 + 3 /8 + 4 /6 This circuit needs only precision resistors compared with the 5 in the previous design. Power dissipated in the resistors varies by a factor of, compared with 5 in the previous design. There are still some bad points: need precision components the output voltage will usually be a fraction of the input (low noise immunity) Example: if in = 00, then out = 3/ + 0/4 + 0/8 + 3/6 = 7/6 for TTL logic levels. Analog to Digital onversion (AD) Parallel A to D conversion ( Flash Encoder or Flash AD) very fast and very simple method use comparators for the conversion Example: one bit AD using one comparator out = (high) if in > ref out = 0 (low) if in < ref L0: Analog/Digital onversion in ref out 6

7 How many comparators do we need for a given accuracy? Suppose we want to convert an analog number into a bit digital number. For bits there are 4 possible outcomes (00, 0, 0, ), it takes 3 comparators. Example: bit parallel converter in 3 3 ref ref ref A Truth Table in A Output < 3 R R < in < 3 R R < in < R 0 > R 3 Logic gates are needed to implement the truth table: LS = A + A = A( + ) A MS MS = A + A = A( + ) = A There are two problems with this scheme: LS Need lots of comparators: n - for n bit accuracy. If we want part in 000 accuracy (0.%), it takes 0 bits 0 - = 03 comparators! Number of logic gates necessary to code the output is large and the logic gets complicated. L0: Analog/Digital onversion 7

8 ounter AD (staircase method): Good news: only uses one comparator ad news: much more complicated than parallel method start in ref logic control clock in DA counter DA oltage outputs clock pulse # When DA > in the logic circuit stops the clock the counter outputs a binary number which is just the number of clock pulses The DA could be: an integrator a resistor ladder a voltage reference L0: Analog/Digital onversion 8

9 Problems with this system: control logic is complicated (use microprocessors + gates +...) time to digitize depends on in. Example: suppose clock runs at 5 MHz, and you want 0 bit accuracy. 0 bits = 04 clock pulses. an only digitize at 5 MHz/04 ~ 5 khz, which is fairly slow! Successive Approximation AD: ontrol logic is very complicated, but easy to program, like a binary search. onversion time is fast and almost independent of in. full scale Example: 5 bit AD: Steps for converting in into a binary number: turn on MS in DA and compare with in. output = 0 if DA > in (steps,, 5) output = if DA < in (steps, 3) turn on next highest bit, output = if DA > in repeat until least significant bit is checked n comparisons for n bit accuracy staircase approach requires n - comparisons parallel AD requires step, independent of accuracy Time for a 0 bit conversion for the three methods: parallel : success approx. : staircase :0: stop in time L0: Analog/Digital onversion 9

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