Advanced DATASHEET. emmc HS400 I/O Pads. 40nm Technology

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1 Advanced DATASHEET emmc HS400 I/O Pads 40nm Technology Arasan Chip Systems, Inc North First Street, Suite #510 San Jose, CA Ph: Fx: April, 2013 i

2 DISCLAIMER This document is written in good faith with the intent to assist the readers in the use of the product. Circuit diagrams and other information relating to Arasan Chip Systems products are included as a means of illustrating typical applications. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. Information contained in this document is subject to continuous improvements and developments. Arasan Chip Systems products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of Arasan Chip Systems Inc. will be fully at the risk of the customer. Arasan Chip Systems Inc. disclaims and excludes any and all warranties, including without limitation any and all implied warranties of merchantability, fitness for a particular purpose, title, and infringement and the like, and any and all warranties arising from any course or dealing or usage of trade. This document may not be copied, reproduced, or transmitted to others in any manner. Nor may any use of information in this document be made, except for the specific purposes for which it is transmitted to the recipient, without the prior written consent of Arasan Chip Systems, Inc. This specification is subject to change at anytime without notice. Arasan Chip Systems Inc. is not responsible for any errors contained herein. In no event shall Arasan Chip Systems Inc. be liable for any direct, indirect, incidental, special, punitive, or consequential damages; or for lost of data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contract; tort; negligence of Arasan Chip Systems or others; strict liability; breach of warranty; or otherwise; whether or not any remedy of buyers is held to have failed of its essential purpose, and whether or not Arasan Chip Systems Inc. has been advised of the possibility of such damages. Restricted Rights Use, duplication, or disclosure by the Government is subject to restrictions as set forth in FAR and DFAR et seq. or its successor. Copyright Notice No part of this specification may be reproduced in any form or means, without the prior written consent of Arasan Chip Systems, Inc. Questions or comments may be directed to: Arasan Chip Systems, Inc North First Street Suite 510, San Jose, CA Ph: Fx: sales@arasan.com 1

3 CONTENTS 1 INTRODUCTION Overview ARCHITECTURE Functional Block Diagram SIGNAL INTERFACES & ELECTRICAL CHARACTERISTICS Pin Description DC Characteristics DELIVERABLES RELATED PRODUCTS... 8 Tables Table 1: Pin Description... 4 Table 2 : Proprietary Pin Description... 5 Table 3: Truth Table for the IO Pins... 6 Table 4: Recommended Operating Conditions... 6 Table 5: DC Characteristics... 7 Table 6: Drive Strength... 7 Figures Figure 1: emmc HS400 I/O Pad Functional Block Diagram 2 2

4 1 INTRODUCTION 1.1 Overview This data sheet provides basic information about I/O pads specially designed for emmc 5.0 HS400. This IP is designed to optimize I/O performance with a core voltage of 1.1V and I/O voltage of 1.8/3.3V in TSMC 40LP process. 2 ARCHITECTURE 2.1 Functional Block Diagram Figure 1: emmc HS400 I/O Pad Functional Block Diagram 3

5 3 SIGNAL INTERFACES 3.1 Pin Description The below table shows the pin description of the I/O pad. Pins Direction Description VCCQ Supply I/O Supply VCORE Supply Core Supply DR_EN Input Enable for P/P Driver DR_TY[2:0] Input Driver Type DIN Input Data to be transmitted DOUT Output Data Received NSTH[6:0] Input N Strength, can be from calibration circuit PSTH[6:0] Input P Strength, can be from calibration circuit REN Input Pull-up or pull down resistor enable OD_EN Input Enable for Open Drain driver OD_HOST Input 1 for Host and 0 for Device VSSQ Supply I/O Ground GNDC Supply Core Ground PAD I/O I/O Pad Connection PU Input 1 for pull up and 0 for pull down Table 1 - Pin Description 4

6 3.1.2 Other Proprietary Pin Description Apart from the above tables, there are other pins which are used for proprietary purposes and those inputs should be tied to 0 unless otherwise noted. Pins Direction Description ddr_data_i[1:0] Input DDR data, tie to 0 tx_clk_i Input TX Clock, tie to 0 rx_clk_i Input RX Clock, tie to 0 strbin_90_i Input Strobe Clock, tie to 0 ddr_data_en_i Input DDR Data enable sdenable_i Input Tied to 1 always dspeed_i Input Default Speed Mode, tie to 0 ddrmode_i Input DDR Mode, tie to 0 rxflops_datp_o Output DDR RX data EVEN rxflops_datn_o Output DDR RX data ODD hs400flops_datp_o Output HS400 RX data EVEN hs400flops_datn_o Output HS400 RX data ODD Table 2 - Proprietary Pin Description 5

7 3.1.3 The truth table for the I/O pins are shown below. mode DR_EN OD_EN DIN REN PU DOUT PAD PP out x 0 0 PP out x 1 1 I2C out x 0 0 I2C out x 1 1 input 0 0 x 0 x 0 0 input 0 0 x 0 x 1 1 idle 0 0 x Pull Up idle 0 0 x Pull Dn idle 0 0 x 0 x x Z Table 3 - Truth Table for the IO Pins 3.2 DC Characteristics The following tables summarize the DC characteristics and characterization conditions of the emmc HS400 I/O pads Recommended Operating Conditions Parameter Min Nom Max Units VCORE Pre driver voltage V VCCQ Post driver voltage 1.72/ / /3.6 V TJ Junction temperature o C VIMAX Maximum input voltage 3.7 V Table 4 Recommended Operating Conditions 6

8 Parameter Min Max Units VIL Input Low Voltage VSSQ * VCCQ V VIH Input High Voltage 0.625*VCCQ VCCQ +0.3 V II Input Leakage Current 2 µa IOZ Tri-State Output Leakage Current 2 µa VOL Output Low Voltage 0.125* VCCQ V VOH Output High Voltage 0.75* VCCQ V Table 5 DC Characteristics Drive Strength Support The following drive strengths are supported and are programmable. Driver Type Nominal Impedance Relative Driving Capability Remark 0 50 Ohms x1 Default driver type, supports up to 200MHz operation 1 33 Ohms x1.5 Supports up to 200MHz operation Ohms x0.75 The weakest driver that supports up to 200MHz operation Ohms x0.5 For Low noise and low EMI systems, Minimum operating frequency is system dependent ohms x1.2 Supports up to DDR 200MHz operation. Table 6 Drive Strength 7

9 4 DELIVERABLES GDSII database LVS Netlist Physical Abstract Model (LEF) Timing Models Behavioral Models Design Integration Guide Technical Documentation 5 RELATED PRODUCTS emmc 5.0 Device IP emmc 5.0/SD3/SDIO3 Host IP emmc 5./SD3/SDIO3 Hardware Validation Platform 8

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