Single Stage Bipolar Amplifier Topologies

Transcription

1 Single Stage ipolar Amplifier Topologies L 338 Uniersity of Rhode Island, Kingston, RI , U.S.A. There are 3 important single stage amplifier topologies using the bipolar transistor: the common emitter, the common collector (or emitter follower) and the common base, shown in figures 1 through 3. V R 1 R 3 R S 1 R L o s in R 2 R 2 Figure 1. ommon mitter Amplifier. V R 1 R S 1 2 s in R 2 R o Figure 2. ommon ollector Amplifier. RS 1 Q 1 3 V R R R V L S in o R 1 2 R 2 Figure 3. ommon ase Amplifier. 1 Tel: (401) ; fax: (401) ; dais@ele.uri.edu L 338 lectronics I 12 Noember 2009

2 The design of any transistor amplifier starts with setting a stable D operating point. The D operating point of a bipolar transistor can be determined by finding two of the four parameters: (I, I, V, V ). A stable D operating point can be designed by biasing the transistor in such a way that the collector current, I, the base-emitter junction oltage V, and the collector-emitter oltage, V will be insensitie to ariations in the D current gain, β, and temperature, T. Although the three amplifier topologies look different, the D equialent circuit is identical in all 3 cases (if we set R = 0 for the common collector). The D equialent circuit, assuming that the npn transistor is biased in the forward actie mode (e.g. actie mode), is shown in figure 4. The capacitors in each of the amplifier topologies are open circuits at D, thus the circuit elements coupled to the amplifier core with series connected capacitors can be ignored for the D analysis. R I β I 0 R TH V TH V I I R Figure 4. D equialent circuit suitable for simple npn-bipolar amplifier topologies. The parameters are: R TH = R 1 R 2, V TH = ( R2 R 1 R 2 ) and I = βi I 0. It is common for the β term to ary oer a large portion of the range: 100 to 1, 000 for typical bipolar transistors. In order to maintain a stable operating point we will need a biasing scheme which will make I insensitie to ariations in β. There are two KVL relations gien by V TH = I R TH V I (1 β)r (1) and = I R V I (1 β)r (2) If we substitute I = βi I 0 into equation (1), and sole for I, we find I = β (V TH V ) R R TH I 0 (3) (β 1) R R TH (β 1)R R TH 2

3 Notice that the expression for I = βi I 0 contains an independent current source, I 0, shown in figure 4, which is defined as the collector current when the base current is zero. This term represents the leakage current across the base-collector junction. For most applications of Silicon transistors, this term can be ignored (e.g. I = βi ), yielding I = β (V TH V ) (β 1)R R TH (4) If (β 1) R R TH, then I β (V TH V ) = α (V TH V ) (5) (β 1) R R The term α = β, remains ery close to unity een for large ariations in β1 β. Thus, setting (β 1) R R TH guarantees minimal change in the D operating point. The second KVL expression gien by equation (2) can be used to find the parameter V and is gien by V = I R I ( ) 1 1 R (6) β Using this analysis, it is possible to formulate a design procedure which will yield a stable D operating point. The steps are: 1) Select the collector current I. This will also determine V and I. 2) Set = (3 5) V. 3) Set V R, the oltage drop across the resistor, R, to be equal or just slightly lower than V. 4) Set I R1 = (10 100) I. Once these parameters are set, each of the four resistor alues, R 1, R 2, R and R can be found. If we assume that the amplifiers in figures 1 through 3 operate at mid-frequency, The bypass capacitor alues are selected such that the impedance presented in the band of operation is negligible when compared to the resistor alues. This 3

4 means that for the mid-frequency A analysis, all of the bypass capacitors can be replaced by short circuits. Any D oltage source will be set to zero (e.g. ac ground); the supply oltages, for example, are shorted to A ground. The small signal equialent circuit can be found for each topology by replacing the transistor with the A equialent (hybrid-π) model shown in figure 5. 2 r π π g m π r o Figure 5. Small signal, hybrid-π model for the bipolar transistor. Using these assumptions, the mid-frequency, A equialent circuit for each amplifier topology can be drawn. The mid-frequency small signal equialent circuit for the common emitter, common collector and common base amplifier topologies are shown in figures 6 through 8. R i s 1 i o s r in R π π r o R R o g L m π Source Figure 6. ommon mitter Amplifier small signal equialent circuit. R s i 1 π s in R r π π r o R i o o Source Figure 7. ommon ollector Amplifier small signal equialent circuit. R s i 1 r o s R r in π π π R i o o Source Figure 8. ommon ase Amplifier small signal equialent circuit. 2 Note: The hybrid-π model is identical for the npn and pnp transistors. 4

5 The oltage and resistance of the signal source are gien by S and R S, respectiely. The oltage and current at the input terminals of each amplifier topology are labeled in and i 1, respectiely. The resistor, R = R TH = R 1 R 2. The output oltage and current are labeled o and i o, respectiely. It is worth mentioning that an ideal, independent D current source is replaced by an open circuit for the ac analysis; if the current source is not ideal, then the current source resistance is kept in the ac equialent circuit. It is useful to note that all of the small signal equialent circuit model parameters shown in figure 5 are determined from partial deriaties. The transconductance,, is gien by = V [I ] = V [ I S e V V T ] = I V T (7) where I is the current set by the D operating point, V T = kt, T is the q absolute temperature in Kelin, k = [ ] 23 V K and q = V T = 26mV at room temperature (T = 300K). The small signal base-emitter resistance, r π, is defined as r π = V I (8) where V and I are determined from the D operating point. The A parameter, β, can be found from the relation β = I ( I = I V ) ( ) V = r π (9) I where is the transconductance, r π is the small signal base-emitter resistance and I, I and V are determined from the D operating point(for our purposes we hae assumed that there is a single β parameter which is fine for exam 1). The parameter r o is gien by r o = ( ) 1 [I ] V A (10) V I where V A is the early oltage and I is the current set by the D operating point. 5

6 Summarizing, to a first order approximation, we find: = I V T ; β = r π & r o V A I (11) where, r π & r o are the small signal parameters, I is the current set by the D operating point and V A is the early oltage. The small signal parameters for each amplifier topology are: the input impedance, Z in, the oltage gain with respect to V in, A Vin, the oltage gain with respect to V S, A Vs, the current gain, A I, the output impedance, Z o and the power gain, A p. The small signal parameters hae been summarized in Table 1 for the three amplifier topologies described in figures 6 through 8. Note that r o = in the deriation of the common collector and the common base small signal parameters. Topology ommon ommon ommon Small Sig. Param. mitter ollector ase ) Z in r π R R [r π (1 β)r ] R ( rπ 1β A Vin = Vo V in (r o R c ) ( ) A Vs = Vo V s A Zin Vin Z in R S (1β)R r π(1β)r ( ) A Zin Vin Z in R S 1 R ( ) A Zin Vin Z in R S A I A Vin Z in Z o r o R R [R Z A in Vin R ( L R R S r π 1β )] 1 A Vin Z in R A p A Vin 2 Z in A Vin 2 Z in Table 1 Summary of parameters for each amplifier topology. A Vin 2 Z in A good designer must always be aware of the limitations of the circuit models used. It is worth noting that the small signal model is an approximation to a linear circuit. It is a ery good approximation to the actual circuit behaior for low oltage swings in the common-emitter amplifier, for example; howeer, if the output oltage swing becomes too high, the alues of the non-linear terms in the Taylor Approximation used for will no longer be negligible (because i = I i c I will no longer hold and will change with in causing the oltage gain to change as a function of in ). Thus, the amplifier gain will ary with the input signal instead of remaining constant throughout the input signal swing. In the common-collector topology, the negatie output oltage swing will will cause the transistor to go into cutoff if o is too large for a gien I. 6

7 Other Single-Stage ipolar Amplifier Topologies This write up proides an introduction to the D and A analysis performed on simple, single-stage, bipolar amplifiers using the common four resistor biasing scheme. This is used often with single-ended supplies (e.g. positie oltage and ground). There is also the emitter-degenerated common emitter amplifier stage shown in figure 9. In this case the emitter bypass capacitor has been remoed, thus the emitter will no longer be at ac ground for the mid-frequency, small signal analysis. There are also other D biasing schemes which hae not been mentioned. Namely, the self-biased approach can also be used for a single-ended power supply. If there is a dual power supply, that is one with a positie and negatie supply rail (e.g. ±15V, then there is also a simple resistor biasing scheme. These are shown for the common-emitter amplifier in figures 11 and 12. A discussion of the different D bias approaches would not be complete without mentioning current source biasing. A simple example is shown in figure 10 using a non-ideal current source attached at the emitter terminal. I 2 is the D current source and R 2 is the resistance (or output impedance) of the current source. Only R 2 stays in the small signal model. Thus, R used in the resistor biasing shown in figure 9 will be replaced by R 2 in the small signal model when using the biasing approach shown in figure 10. Finally, this has been done for the npn transistor; the analysis for the pnp transistor is quite similar. V V R 1 R 2 R S 1 R L o s in R 2 R R 1 R 2 R S 1 R L o s in R 2 I 2 R 2 Figure 9. mitter-degenerated, ommon mitter Amplifier. Figure 10. ommon mitter Amplifier biased with a non-ideal current source. S R S 1 in R 2 R R 3 o S R S 3 1 in R R 2 o Figure 11. Self-biased ommon mitter Amplifier. V Figure 12. ommon mitter Amplifier biased with dual power supplies. 7