Lecture 4 - Pipelining

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1 CS 152 Computer Architecture and Engineering Lecture 4 - Pipelining Dr. George Michelogiannakis EECS, University of California at Berkeley CRD, Lawrence Berkeley National Laboratory

2 Last time in Lecture 3 Microcoding became less attractive as gap beten RAM and ROM speeds reduced Complex instruction sets difficult to pipeline, so difficult to increase performance as gate count grew Load-Store RISC ISAs designed for efficient pipelined implementations Very similar to vertical microcode Inspired by earlier Cray machines (more on these later) Iron Law explains architecture design space Trade instructions/program, cycles/instruction, and time/cycle 2

3 Why a five stage pipeline? Question of the Day 3

4 An Ideal Pipeline stage 1 stage 2 stage 3 stage 4 All objects go through the same stages No sharing of resources beten any two stages Propagation delay through all pipeline stages is equal The scheduling of an object entering the pipeline is not affected by the objects in other stages These conditions generally hold for industrial assembly lines, but instructions depend on each other! 4

5 To pipeline RISC-V: Pipelined RISC-V First build RISC-V without pipelining with CPI=1 Next, add pipeline registers to reduce cycle time while maintaining CPI=1 5

6 Lecture 3: Unpipelined Datapath for RISC-V PCSel br rind jabs pc+4 RegWriteEn MemWrite WBSel 0x4 Add Add clk PC clk inst Inst. rs1 rs2 rd1 wa wd rd2 GPRs Imm Select ALU Control Br Logic Bcomp? ALU clk rdata Data wdata OpCode WASel ImmSel Op2Sel 6

7 Lecture 3: Hardwired Control Table Opcode ImmSel Op2Sel FuncSel MemWr RFWen WBSel WASel PCSel ALU ALUi LW SW BEQ true BEQ false JAL JALR * Reg Func no yes ALU rd BrType 12 * * no no * * pc+4 IType 12 Imm Op no yes ALU rd pc+4 IType 12 Imm + no yes Mem rd pc+4 BsType 12 Imm + yes no * * pc+4 BrType 12 * * no no * * pc+4 * * * yes PC rd jabs * * * no yes PC rd rind br Op2Sel= Reg / Imm WBSel = ALU / Mem / PC PCSel = pc+4 / br / rind / jabs Correction since L3: J has been removed 7

8 Pipelined Datapath PC 0x4 Add rdata Inst. rs1 rs2 rd1 wa wd rd2 GPRs Imm Select ALU rdata Data wdata fetch phase decode & Reg-fetch phase Clock period can be reduced by dividing the execution of an instruction into multiple cycles t C > max {t IM, t RF, t ALU, t DM, t RW } ( = t DM probably) Hover, CPI will increase unless instructions are pipelined execute phase memory phase write -back phase 8

9 Iron Law of Processor Performance Time = Instructions Cycles Time Program Program * Instruction * Cycle Instructions per program depends on source code, compiler technology, and ISA Cycles per instructions (CPI) depends on ISA and µarchitecture Time per cycle depends upon the µarchitecture and base technology Lecture 2 Lecture 3 Lecture 4 Microarchitecture CPI cycle time Microcoded >1 short Single-cycle unpipelined 1 long Pipelined 1 short 9

10 CPI Examples Microcoded machine 7 cycles 5 cycles 10 cycles Inst 1 Inst 2 Inst 3 Time Unpipelined machine Pipelined machine 3 instructions, 22 cycles, CPI=7.33 Inst 1 Inst 2 Inst 3 Inst 1 Inst 2 Inst 3 3 instructions, 3 cycles, CPI=1 3 instructions, 3 cycles, CPI=1 5-stage pipeline CPI 5!!! 10

11 Technology Assumptions A small amount of very fast memory (caches) backed up by a large, slor memory Fast ALU (at least for integers) Multiported Register files (slor!) Thus, the following timing assumption is reasonable t IM ~= t RF ~= t ALU ~= t DM ~= t RW A 5-stage pipeline will be focus of our detailed design - some commercial designs have over 30 pipeline stages to do an integer add! 11

12 PC 0x4 Add rdata Inst. I-Fetch (IF) 5-Stage Pipelined Execution rs1 rs2 rd1 wa wdrd2 GPRs Imm Select Decode, Reg. Fetch (ID) Execute (EX) rdata Data wdata (MA) time t0 t1 t2 t3 t4 t5 t6 t7.... instruction1 IF 1 ID 1 EX 1 MA 1 WB 1 instruction2 IF 2 ID 2 EX 2 MA 2 WB 2 instruction3 IF 3 ID 3 EX 3 MA 3 WB 3 instruction4 IF 4 ID 4 EX 4 MA 4 WB 4 instruction5 IF 5 ID 5 EX 5 MA 5 WB 5 ALU Write -Back (WB) 12

13 Resources PC 0x4 Add rdata Inst. I-Fetch (IF) 5-Stage Pipelined Execution Resource Usage Diagram rs1 rs2 rd1 ws wdrd2 GPRs Imm Select Decode, Reg. Fetch (ID) time t0 t1 t2 t3 t4 t5 t6 t7.... IF I 1 I 2 I 3 I 4 I 5 ID I 1 I 2 I 3 I 4 I 5 EX I 1 I 2 I 3 I 4 I 5 MA I 1 I 2 I 3 I 4 I 5 WB I 1 I 2 I 3 I 4 I 5 ALU Execute (EX) rdata Data wdata (MA) Write -Back (WB) 13

14 Pipelined Execution: ALU Instructions 0x4 Add PC inst Inst rs1 rs2 rd1 wa wd rd2 GPRs Imm Select A B ALU Y rdata Data wdata R MD1 MD2 Not quite correct! We need an Instruction Reg () for each stage 14

15 Pipelined RISC-V Datapath without jumps F D E M W 0x4 Add RegWriteEn PC inst Inst rs1 rs2 rd1 wa wd rd2 GPRs Imm Select A B ALU Control ALU Y MemWrite rdata Data wdata WBSel R ImmSel Op2Sel MD1 MD2 Control Points Need to Be Connected 15

16 Instructions interact with each other in pipeline An instruction in the pipeline may need a resource being used by another instruction in the pipeline structural hazard An instruction may depend on something produced by an earlier instruction Dependence may be for a data value data hazard Dependence may be for the next instruction s ess control hazard (branches, exceptions) 16

17 Resolving Structural Hazards Structural hazard occurs when two instructions need same hardware resource at same time Can resolve in hardware by stalling ner instruction till older instruction finished with resource A structural hazard can always be avoided by adding more hardware to design E.g., if two instructions both need a port to memory at same time, could avoid hazard by adding second port to memory Our 5-stage pipeline has no structural hazards by design Thanks to RISC-V ISA, which was designed for pipelining 17

18 Data Hazards x4 x1 x1 0x4 Add PC inst Inst rs1 rs2 rd1 wa wd rd2 GPRs Imm Select A B ALU Y rdata Data wdata wdata R MD1 MD2... x1 x x4 x x1 is stale. Oops! 18

19 How Would You Resolve This? What can you do if your project buddy has not completed their part, which you need to start? Three options Wait (stall) Speculate on the value of the deliverable Bypass: ask them for what you need before his/her final deliverable (ask him/her to work harder?) 19

20 Resolving Data Hazards (1) Strategy 1: Wait for the result to be available by freezing earlier pipeline stages interlocks 20

21 Feedback to Resolve Hazards FB 1 FB 2 FB 3 FB 4 stage 1 stage 2 stage 3 stage 4 Later stages provide dependence information to earlier stages which can stall (or kill) instructions Controlling a pipeline in this manner works provided the instruction at stage i+1 can complete without any interference from instructions in stages 1 to i (otherwise deadlocks may occur) 21

22 Interlocks to resolve Data Hazards Stall Condition 0x4 Add bubble PC inst Inst... x1 x x4 x rs1 rs2 rd1 wa wd rd2 GPRs Imm Select A B MD1 ALU Y MD2 rdata Data wdata wdata R 22

23 Stalled Stages and Pipeline Bubbles time t0 t1 t2 t3 t4 t5 t6 t7.... (I 1 ) x1 (x0) + 10 IF 1 ID 1 EX 1 MA 1 WB 1 (I 2 ) x4 (x1) + 17 IF 2 ID 2 ID 2 ID 2 ID 2 EX 2 MA 2 WB 2 (I 3 ) IF 3 IF 3 IF 3 IF 3 ID 3 EX 3 MA 3 WB 3 (I 4 ) (I 5 ) stalled stages IF 4 ID 4 IF 5 EX 4 ID 5 MA 4 EX 5 WB 4 MA 5 WB 5 Resource Usage time t0 t1 t2 t3 t4 t5 t6 t7.... IF I 1 I 2 I 3 I 3 I 3 I 3 I 4 I 5 ID I 1 I 2 I 2 I 2 I 2 I 3 I 4 I 5 EX I I 2 I 3 I 4 I 5 MA I I 2 I 3 I 4 I 5 WB I I 2 I 3 I 4 I 5 - pipeline bubble 23

24 Interlock Control Logic stall C stall wa rs2 rs1? 0x4 Add bubble PC inst Inst rs1 rs2 rd1 wa wd rd2 GPRs Imm Select A B ALU Y rdata Data wdata wdata R Compare the source registers of the instruction in the decode stage with the destination register of the uncommitted instructions. MD1 MD2 24

25 Interlock Control Logic ignoring jumps & branches stall wa C stall rs1 rs2? re1 re2 C dest wa wa C dest 0x4 Add C re bubble PC inst Inst rs1 rs2 rd1 wa wd rd2 GPRs Imm Select Should always stall if an rs field matches some rd? not every instruction writes a register => not every instruction reads a register => re A B MD1 ALU Y MD2 rdata Data wdata R 25

26 Source & Destination Registers func7 rs2 rs1 func3 rd opcode immediate12 rs1 func3 rd opcode imm rs2 rs1 func3 imm Jump Offset[19:0] rd opcode opcode ALU ALUI/LW/JALR SW/Bcond source(s) destination ALU rd <= rs1 func10 rs2 rs1, rs2 rd ALUI rd <= rs1 op imm rs1 rd LW rd <= M [rs1 + imm] rs1 rd SW M [rs1 + imm] <= rs2 rs1, rs2 - Bcond rs1,rs2 rs1, rs2 - true: PC <= PC + imm false: PC <= PC + 4 JAL x1 <= PC, PC <= PC + imm - rd JALR rd <= PC, PC <= rs1 + imm rs1 rd 0 26

27 Deriving the Stall Signal C destws = rd = Case opcode ALU, ALUi, LW, JALR =>on... =>off C re re1 = Case opcode ALU, ALUi, LW, SW, Bcond, JALR JAL =>on =>off re2 = Case opcode ALU, SW, Bcond... =>on ->off C stall stall = ((rs1 D =ws E ). E + (rs1 D =ws M ). M + (rs1 D =ws W ). W ). re1 D + ((rs2 D =ws E ). E + (rs2 D =ws M ). M + (rs2 D =ws W ). W ). re2 D 27

28 Hazards due to Loads & Stores Stall Condition What if x1+7 = x3+5? 0x4 Add bubble PC inst Inst... M[x1+7] <= x2 x4 <= M[x3+5]... rs1 rs2 rd1 wa wd rd2 GPRs Imm Select A B MD1 ALU Y MD2 rdata Data wdata Is there any possible data hazard in this instruction sequence? R 28

29 Load & Store Hazards... M[x1+7] <= x2 x4 <= M[x3+5]... x1+7 = x3+5 => data hazard Hover, the hazard is avoided because our memory system completes writes in one cycle! Load/Store hazards are sometimes resolved in the pipeline and sometimes in the memory system itself. More on this later in the course. 29

30 CS152 Administrivia Quiz 1 on Feb 17 will cover PS1, Lab1, lectures 1-5, and associated readings. 30

31 Resolving Data Hazards (2) Strategy 2: Route data as soon as possible after it is calculated to the earlier pipeline stage bypass 31

32 Bypassing time t0 t1 t2 t3 t4 t5 t6 t7.... (I 1 ) x1 x IF 1 ID 1 EX 1 MA 1 WB 1 (I 2 ) x4 x IF 2 ID 2 ID 2 ID 2 ID 2 EX 2 MA 2 WB 2 (I 3 ) IF 3 IF 3 IF 3 IF 3 ID 3 EX 3 MA 3 (I 4 ) stalled stages IF 4 ID 4 EX 4 (I 5 ) IF 5 ID 5 Each stall or kill introduces a bubble in the pipeline => CPI > 1 A new datapath, i.e., a bypass, can get the data from the output of the ALU to its input time t0 t1 t2 t3 t4 t5 t6 t7.... (I 1 ) x1 x IF 1 ID 1 EX 1 MA 1 WB 1 (I 2 ) x4 x IF 2 ID 2 EX 2 MA 2 WB 2 (I 3 ) IF 3 ID 3 EX 3 MA 3 WB 3 (I 4 ) IF 4 ID 4 EX 4 MA 4 WB 4 (I 5 ) IF 5 ID 5 EX 5 MA 5 WB 5 32

33 stall Adding a Bypass 0x4 Add x4 <= x1... x1 <=... bubble E M W PC inst Inst D rs1 rs2 rd1 wa wd rd2 GPRs Imm Select ASrc A B MD1 ALU Y MD2 rdata Data wdata R... When does this bypass help? (I 1 ) x1 <= x x1 <= M[x0 + 10] JAL 500 (I 2 ) x4 <= x x4 <= x x4 <= x yes no no 33

34 The Bypass Signal Deriving it from the Stall Signal stall = ( ((rs1 D =ws E ). E + (rs1 D =ws M ). M + (rs1 D =ws W ). W ).re1 D +((rs2 D =ws E ). E + (rs2 D =ws M ). M + (rs2 D =ws W ). W ).re2 D ) ws = rd = Case opcode ALU, ALUi, LW,, JAL JALR => on... => off ASrc = (rs1 D =ws E ). E.re1 D Is this correct? No because only ALU and ALUi instructions can benefit from this bypass Split E into two components: -bypass, -stall 34

35 Bypass and Stall Signals Split E into two components: -bypass, -stall -bypass E = Case opcode E ALU, ALUi => on... => off -stall E = Case opcode E LW, JAL, JALR=> on JAL => on... => off ASrc = (rs1 D =ws E ).-bypass E. re1 D stall = ((rs1 D =ws E ).-stall E + (rs1 D =ws M ). M + (rs1 D =ws W ). W ). re1 D +((rs2 D = ws E ). E + (rs2 D = ws M ). M + (rs2 D = ws W ). W ). re2 D 35

36 Fully Bypassed Datapath stall PC for JAL,... 0x4 Add bubble ASrc E M W PC inst Inst Is there still a need for the stall signal? D rs1 rs2 rd1 wa wd rd2 GPRs Imm Select BSrc A B MD1 ALU Y MD2 rdata Data wdata stall = (rs1 D =ws E ). (opcode E =LW E ).(ws E!=0 ).re1 D + (rs2 D =ws E ). (opcode E =LW E ).(ws E!=0 ).re2 D R 36

37 Time Pipeline CPI Examples Inst 1 Inst 2 Inst 3 Measure from when first instruction finishes to when last instruction in sequence finishes. 3 instructions finish in 3 cycles CPI = 3/3 =1 Inst 1 Inst 2 Bubble Inst 3 Inst 1 Bubble 1 Inst 2 Inst Bubble 3 2 Inst 3 3 instructions finish in 4 cycles CPI = 4/3 = instructions finish in 5cycles CPI = 5/3 =

38 Resolving Data Hazards (3) Strategy 3: Speculate on the dependence! Two cases: Guessed correctly do nothing Guessed incorrectly kill and restart. We ll later see examples of this approach in more complex processors. 38

39 Speculation that load value=zero stall PC for JAL,... 0x4 Add bubble ASrc E M W PC inst Inst D rs1 rs2 rd1 wa wd rd2 GPRs Imm Select BSrc Guess_zero 0 A B MD1 ALU Y MD2 rdata Data wdata R Guess_zero= (rs1 D =ws E ). (opcode E =LW E ).(ws E!=0 ).re1 D Also need to add circuitry to remember that this was a guess and flush pipeline if load not zero! Not worth doing in practice why? 39

40 Control Hazards What do need to calculate next PC? For Jumps Opcode, PC and offset For Jump Register Opcode, Register value, and PC For Conditional Branches Opcode, Register (for condition), PC and offset For all other instructions Opcode and PC ( and have to know it s not one of above ) 40

41 PC Calculation Bubbles time t0 t1 t2 t3 t4 t5 t6 t7.... (I 1 ) x1 x IF 1 ID 1 EX 1 MA 1 WB 1 (I 2 ) x3 x IF 2 IF 2 ID 2 EX 2 MA 2 WB 2 (I 3 ) IF 3 IF 3 ID 3 EX 3 MA 3 WB 3 (I 4 ) IF 4 IF 4 ID 4 EX 4 MA 4 WB 4 Resource Usage time t0 t1 t2 t3 t4 t5 t6 t7.... IF I 1 - I 2 - I 3 - I 4 ID I 1 - I 2 - I 3 - I 4 EX I 1 - I 2 - I 3 - I 4 MA I 1 - I 2 - I 3 - I 4 WB I 1 - I 2 - I 3 - I 4 - pipeline bubble 41

42 Speculate next ess is PC+4 PCSrc (pc+4 / jabs / rind/ br) stall Add E M 0x4 Add bubble Jump? I 1 PC 104 inst Inst I 2 I ADD I J 304 I ADD I ADD kill A jump instruction kills (not stalls) the following instruction How? 42

43 Pipelining Jumps PCSrc (pc+4 / jabs / rind/ br) 0x4 Add stall Add bubble To kill a fetched instruction -- Insert a mux before E M Jump? I 21 I 1 PC inst Inst Src D bubble bubble I 2 Any interaction beten stall and jump? I ADD I J 304 I ADD I ADD kill Src D = Case opcode D JAL bubble... IM 43

44 Jump Pipeline Diagrams time t0 t1 t2 t3 t4 t5 t6 t7.... (I 1 ) 096: ADD IF 1 ID 1 EX 1 MA 1 WB 1 (I 2 ) 100: J 304 IF 2 ID 2 EX 2 MA 2 WB 2 (I 3 ) 104: ADD IF (I 4 ) 304: ADD IF 4 ID 4 EX 4 MA 4 WB 4 Resource Usage time t0 t1 t2 t3 t4 t5 t6 t7.... IF I 1 I 2 I 3 I 4 I 5 ID I 1 I 2 - I 4 I 5 EX I 1 I 2 - I 4 I 5 MA I 1 I 2 - I 4 I 5 WB I 1 I 2 - I 4 I 5 - pipeline bubble 44

45 Pipelining Conditional Branches PCSrc (pc+4 / jabs / rind / br) stall Add E M 0x4 Add bubble BEQ? I 1 Taken? Src D PC 104 bubble inst Inst I 2 A ALU Y I ADD I BEQ x1,x I ADD I ADD Branch condition is not known until the execute stage what action should be taken in the decode stage? 45

46 Pipelining Conditional Branches PCSrc (pc+4 / jabs / rind / br) stall? 0x4 Add Add bubble E Bcond? M I 2 I 1 Taken? PC 108 Src D bubble inst Inst I ADD I BEQ x1,x I ADD I ADD I 3 A If the branch is taken - kill the two following instructions - the instruction at the decode stage is not valid stall signal is not valid ALU Y 46

47 Add Pipelining Conditional Branches PCSrc (pc+4/jabs/rind/br) stall 0x4 Add Src E bubble E Bcond? M PC Jump? I 2 I 1 Taken? PC 108 Src D bubble inst Inst I 1: 096 ADD I 2: 100 BEQ x1,x I 3: 104 ADD I 4: 304 ADD I 3 A If the branch is taken - kill the two following instructions - the instruction at the decode stage is not valid stall signal is not valid ALU Y 47

48 Branch Pipeline Diagrams (resolved in execute stage) time t0 t1 t2 t3 t4 t5 t6 t7.... (I 1 ) 096: ADD IF 1 ID 1 EX 1 MA 1 WB 1 (I 2 ) 100: BEQ +200 IF 2 ID 2 EX 2 MA 2 WB 2 (I 3 ) 104: ADD IF 3 ID (I 4 ) 108: IF (I 5 ) 304: ADD IF 5 ID 5 EX 5 MA 5 WB 5 Resource Usage time t0 t1 t2 t3 t4 t5 t6 t7.... IF I 1 I 2 I 3 I 4 I 5 ID I 1 I 2 I 3 - I 5 EX I 1 I I 5 MA I 1 I I 5 WB I 1 I I 5 - pipeline bubble 48

49 Why a five stage pipeline? Question of the Day 49

50 Acknowledgements These slides contain material developed and copyright by: Arvind (MIT) Krste Asanovic (MIT/UCB) Joel Emer (Intel/MIT) James Hoe (CMU) John Kubiatowicz (UCB) David Patterson (UCB) MIT material derived from course UCB material derived from course CS252 50

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