Overview. Features. Layer1+ Layer0+ BG. Layer1 Alpha1 Layer0+BG. Layer1 Alpha1 Layer0 Alpha0 BG

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1 Overview CDC-200 is a fully customizable display controller IP supporting OpenWF display API specification. A number of features can be configured both at synthesis and at run time. The display controller can be adapted to both FPGA systems (limited features, special applications) or for an ASIC (generic feature set, more flexibility.) At compile time, the most important features that can be configured are, (A)RGB formats, number of layers and blending features. The maximum number of (A)RGB layers is only dependent on the bus bandwidth and timing constraints. CDC-200 can support AMBA APB and AHB/AXI as well as the Altera Avalon bus interface. The controller provides a digital RGB signal with video data and signals for horizontal/vertical blank and synchronization as output. To support a large number of displays, resolution and refresh rate can be register controlled. Features Parallel Pixel Output o 24 bit RGB o HSync, VSync, Data enable (polarity configurable) o Serialization logic (e.g. OpenLDI, MIPI DSI) can easily be adapted High Resolutions o Up to 64k x 64k pixels o Maximum resolution can be constrained at synthesis time to save resources o Run-time programmable resolution needs external programmable PLL Multiple Layers (number of layers + features configurable) o Windowing Picture-in-Picture effects Video overlay GUI menu on top of main application o Flexible blending between layers (color = f 1 * color 1 + f 0 * color 0 ) Standard alpha blending (f 1 = alpha; f 2 = 1-alpha) Pre-multiplied alpha layers (f 1 = 1.0; f 2 = 1-alpha) Additional constant alpha (fade in/out of layers) o Per-pixel alpha can be stored in dedicated alpha layers (8 bit alpha) Layer1 Alpha1 Layer0 Alpha0 BG Layer1 Alpha1 Layer0+BG Layer1+ Layer0+ BG

2 Flexible Color Formats o Up to 8 input formats selectable per layer o Available formats fully configurable at synthesis time, e.g.: ARGB8888 ARGB4444 ARGB1555 RGB565 RGBA8888 RGBA4444 RGBA bit grayscale etc. CLUT option o Usage of indexed formats, e.g. 8 bit indexed 8 bit alpha + 8 bit indexed 4 bit alpha + 4 bit indexed o Up to bit color values in CLUT RAM Color Keying o Define transparent color for formats without alpha Gamma Correction o Adapt to display characteristics o Brightness + contrast control o Multiple different implementations selectable (trade-off flexibility vs. resource usage) Dithering o Softer color transitions for displays with less color depth o Different implementations selectable (trade-off flexibility vs. resource usage) Ordered dithering Pseudo random dithering Slave Timing Mode o Sync to video source o Allows video streaming without memory bus load Power Memory blocks controlled by chip select port Clock gating of disabled layers logic + during blanking times Prepared for efficient automatic clock gating

3 Easy Integration Low resource consumption Simple dual clock domain architecture o Bus clock + pixel clock are fully asynchronous High bus latency capable (pixel FIFO depth configurable) Single bus master port (internal arbitration) Adaptors for common bus protocols o ARM AMBA: APB for register access, AHB or AXI for memory bus master access o Altera Avalon as bus adaptors for both register and bus master access o Other bus protocols can be easily adapted Configurability Comprehensive VHDL configuration package for: Configuration of layers Configuration of input pixel formats Enabling and disabling of certain features at synthesis time Configuration of register reset values etc. Constraining the feature set results in a smaller resource foot-print. Resource Usage The actual resource usage of CDC-200 depends largely on the configuration (number of layers, features configured to be available etc.). The following numbers give an indication of the resource usage for a typical configuration using two layers and a 32 bit bus interface. FPGA Resource Usage Logic cells ~3000 logic elements DSP blocks 7 multipliers (8x8) RAM blocks 2 M9K blocks All numbers given for Altera Cyclone III device family Std. Cell ASIC Resource Usage Gate count Memory blocks ~41k NAND2 gate equivalents 2 memory blocks (32x64), simple dual ported (one read port, one write port) with independent read and write clocks

4 Block Diagram Software Drivers TES provides a simple basic driver for register agnostic control of the CDC-200. On top of the basic driver, a Khronos standard OpenWF Display API driver is available. The drivers feature the following characteristics: Plain ANSI-C Code Fully reentrant & thread-safe Minimal OS dependency (HAL part separated) No floating point usage No inline assembler required Small memory footprint Drivers for other APIs can be developed on request.

5 Verification Details A 100% algorithmic equivalent C model is used as reference for the verification of the RTL code. The following test metrics are used: Functional Coverage Code Coverage using Cadence IUS Static Code Checking using Atrenta Spyglass Timing Checks FPGA prototyping Where applicable, the tests automatically adapt according to a changed configuration. Sales & Marketing Contact TES Electronic Solutions GmbH Zettachring 8 Stuttgart, Germany graphics_sales@tesbv.com