Canon LC1290A (Die Markings) 20.2 Mp, 4.1 µm Pixel Size Dual Pixel CMOS AF APS-C CMOS Image Sensor from the Canon EOS-70D(W) DSLR Camera

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1 Canon LC1290A (Die Markings) 20.2 Mp, 4.1 µm Pixel Size Dual Pixel CMOS AF APS-C CMOS Image Sensor from the Canon EOS-70D(W) DSLR Camera Imager Process Review 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel:

2 Imager Process Review Some of the information in this report may be covered by patents, mask, and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. Chipworks Inc all rights reserved. Chipworks and the Chipworks logo are registered trademarks of Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. IPR CYWM Revision 1.0 Published: October 30, 2013

3 Imager Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Camera and Image Sensor 2.2 Package and Die 2.3 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 MOS Transistors, and Poly 3.7 Isolation 3.8 Wells and Substrate 4 Pixel Analysis 4.1 Pixel Overview and Schematic 4.2 Pixel Plan View Analysis 4.3 Pixel Array Cross Section Parallel to Column Out Line 4.4 Pixel Array Cross Section Parallel to Row Select Line 4.5 Color Filters, Lenses, and Dark Pixels 5 Critical Dimensions 5.1 Die and Bond Pad Dimensions 5.2 Dielectric Thicknesses 5.3 Metallization Critical Dimensions 5.4 Via and Contact Dimensions 5.5 MOS Transistor and Poly Dimensions 5.6 LOCOS Isolation 5.7 Well Depths and Die Thickness 5.8 Pixel Horizontal Dimensions 5.9 Pixel Vertical Dimensions

4 Imager Process Review 6 References 7 Statement of Measurement Uncertainty and Scope Variation About Chipworks

5 Overview Overview 1.1 List of Figures 2 Device Overview Canon EOS-70D(W) Front Image Sensor Module on PWB Front Image Sensor Module on PWB Back Package Front Package Back Package X-Ray Plan View Package X-Ray Side View Die Photograph Die Markings Annotated Die Photograph Analysis Sites Die Corner A Die Corner B Die Corner C Die Corner D Bond Pad Pitch Bond Pad Detail Registration Marks Detail Pixel Array Corner A Pixel Array Corner B Pixel Array Corner C Pixel Array Corner D Detailed View of Active Pixel Array 3 Process Analysis General Structure Periphery General Structure Pixel Array Die Thickness Die Edge Die Seal Bond Pad Bond Pad Edge Bond Pad Tilt View Passivation and IMD Passivation TEM IMD 1 in Periphery - SEM PMD SEM PMD in Pixel Array Metal 3, Metal 2, and Metal Metal 3 TEM Metal 2 Pitch Periphery Metal 2 Pixel Array SEM Metal 2 TEM

6 Overview Metal 1 Pitch Periphery Metal 1 Pitch Pixel Array TEM Metal 1 Pixel Array TEM Minimum Pitch Via Minimum Pitch Via Minimum Contacts to Substrate Contact to Poly SEM Contact to Poly Bottom SEM Contact Bottom TEM Contacted Gate Pitch Pixel Array SEM Peripheral MOS Gate SEM Peripheral MOS Gate TEM Sidewall Spacer SEM Sidewall Spacer TEM Peripheral NMOS Transistor Logic Gate Dielectric TEM LOCOS Minimum Width LOCOS Pixel Array SRP Location Peripheral P-Well (P-Well 1) SRP (Location 2) Peripheral N-Well SRP (Location 3) Array P-Well SRP (Location 1) SCM Overview of Peripheral P-Wells SCM Overview of Pixel Array Edge 4 Pixel Analysis Pixel Schematic RGB Bayer Patterned Color Filter Array Microlenses Tilt View Microlenses Plan View Color Filters Plan View Active Pixel to Periphery Transition Top Edge of the Array Active Pixel to Periphery Transition Right Edge of the Array Pixels at Metal Pixels at Via 2/Metal Pixels at Via 1/Metal Pixels at Contact/Poly Pixel at Contact/Poly/Diffusion Pixels at Diffusion Pixel and Transfer Gate at Diffusion Bevel SCM of Pixels Planes of Cross-Sectioning Parallel to Column Out Line Pixel Array Cross-Sectional Overview (A) Transfer Gate Transistor (T1) SEM (A) Transfer Gate (T1) TEM (A) Transfer Gate Edge Facing FD Contact (T1) TEM (A)

7 Overview Transfer Gate Edge Facing Pixel Cathode (T1) SEM (A) Transfer Transistor Gate Dielectric TEM Pixel Array AR 1 TEM (A) SEM of N-Cathode and P-Pinning Layer (B) Overview SEM of N-Cathode and P-Pinning Layer (B) Detail FD (B) Close-up Reset, Source Follower, and Row Select Overview (C) Reset Transistor (T5) Gate Length (C) Source Follower Transistor (T6) Gate Length (C) Row Select Transistor (T7) Gate Length (C) Planes of Cross-Sectioning Parallel to Row Select Line V SS and FD Contact Overview V SS and FD Contacts (D) Detail Transfer Transistor (T1/T2) Gate Widths at T2 Contact (E) Transfer Transistor (T1/T2) Gate Widths at T1 Contact (F) Reset Transistor (T5) Gate Width (G) SCM of N-Cathode and P-Pinning Layer (G) Overview SCM of N-Cathode and P-Pinning Layer (G) Detail Source Follower Transistor (T6) Gate Width (H) Transfer Gate Transistor (T3/T4) Gate Widths at T3 Contact (I) Row Select Transistor (T7) Gate Width (J) Row Select Transistor (T4) Gate Width (G) Pixel Array Center Filters and Microlenses Filters and Microlenses Transition Between Active and Dark Pixels Pixel Array Away from Edge ROW Line Direction Pixel Array to Periphery Transition ROW Line Direction Filters and Microlenses CO Line Direction Transition Between Dark Pixels and Periphery Edge of Color Filter Array Edge of Microlens and Blue Color Filters Overview Edge of Microlens and Blue Color Filters Detail Microlenses Oxide Coating TEM Organic Lens Red Color Filter Blue Color Filter Green Color Filters

8 Overview List of Tables 1 Overview Device Identification Device Summary Process Summary 2 Device Overview Die and Bond Pad Dimensions 3 Process Analysis Measured Dielectric Thicknesses Metallization Thicknesses Metallization Width and Pitch Via and Contact Dimensions Peripheral MOS Transistor and Poly Dimensions LOCOS Critical Dimensions Well Depths 4 Pixel Analysis Pixel Horizontal Dimensions Pixel Vertical Dimensions Pixel Transistor Physical Dimensions 5 Critical Dimensions Die, Bond Pad, and Standard Cell Dimensions Dielectric Thicknesses Metallization Thicknesses Metallization Width and Pitch Via and Contact Dimensions Peripheral MOS Transistor, Capacitor, and Poly Dimensions LOCOS Critical Dimensions Well Depths Pixel Horizontal Dimensions Pixel Vertical Dimensions Pixel Transistor Physical Dimensions

9 About Chipworks About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at Chipworks 1891 Robertson Road, Suite 500 Ottawa, Ontario K2H 5B7 Canada T F Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com

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