High-Speed and Low-Power 2.5D I/O Circuits for Memory-logic-integration by Through-Silicon Interposer

Transcription

1 High-Speed and Low-Power 2.5D I/O Circuits for Memory-logic-integration by Through-Silicon Interposer Jiacheng Wang 1,2, Shunli Ma 1,3, Sai Manoj P D 1, Mingbin Yu 4, Roshan Weerasekera 4, and Hao Yu 1 1 School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 2 ERI@N Interdisciplinary Graduate School, Nanyang Technological University, Singapore 3 State Key Lab of ASIC and System, Fudan University, China 4 Institute of Microelectronics, A*STAR, Singapore

2 Overview Motivation I/O for 2.5D Integration Proposed 2.5D I/O Design Simulation Results Conclusion 2

3 Exa-scale Computing Data at scale to process Many-core server to frequently access memory with needed bandwidth >10Gbps and energy efficiency 1pJ/bit New I/O integration by 3D TSV or 2.5D TSI 3

4 2.5D Integration by TSI Memory/logic integrated on one common substrate by through-silicon interposer (TSI) I/O Traditional 2D integration is non-scalable for latency 3D has high thermal density and poor thermal dissipation 2.5D provides good latency and thermal dissipation 4

5 Memory-logic Integration by 2.5D TSI I/O Logic blocks (cores) on side of one substrate and memory on other, interfaced by 2.5D TSI I/O communication CML or LVDS buffers for T- lines At high-frequencies there will be channel loss How to compensate frequency dependent loss? 5

6 Design of 2.5D I/Os (I) Low-voltage-differential-signal (LVDS) I/O Buffer To improve the margins of eye diagram pre-emphasis is used A digital inverter-chain is used to delay input digital signals with time constant Amplitude pre-emphasis reduces DC gain, but enhances frequency response To achieve low power, the current source of LVDS buffer is controlled to drive about only 350mV peak-to-peak voltage swing at the termination resistor and gain of

7 Design of 2.5D I/Os (II) LVDS I/O Buffer - Operation 7

8 Design of 2.5D I/Os (III) Current-mode-logic (CML) I/O Buffer Two stage CML buffer is designed with pre-amp stage such that preamp stage is connected to input of driving stage Currents through resistor and inductor loads are controlled by input voltage swing of two transistors and their size 8

9 Design of 2.5D I/Os (IV) Current-mode-logic (CML) I/O Buffer CML buffer drives through the microbump which has smaller load and hence NMOS transistors of second stage can be smaller in size There is a high frequency path through inductors when the CML buffer transmits high speed signal To compensate high frequency loss of a 2.5D TSI T-line, inductor loads are designed as cross coupled As such, there is a fast data-pass through inductors when the CML buffer transmits high speed signal 9

10 Simulation Results Setup Designed in UMC 65nm CMOS Process Chips are assembled face down and are attached to microbumps Connected through around 20μm width TSI T-line TSI T-line is by Aluminimum, and dielectric is Silicon dioxide with characteristic impedance of 50 Ohms 10

11 Simulation Results Layout The whole chip area is 550µmx330µm, 60µmx120µm area for LVDS transceiver In CML circuits, the inductors cost most area of the chip, which are 90µm x90µm for each. 11

12 Post Layout Simulation Results LVDS I/O Achieves 360mV peak-to-peak output swing and 563fs cycle-to-cycle jitter with 10GHz bandwidth. Power consumption is only 4.8mW under 1.2V supply, about 0.48pJ/b energy efficiency When transmitted through the TSI, the signal has 30mV loss, but the 2dB amplitude pre-emphasis part protects the performance of high frequency edges. LVDS Output waveform After passing through TSI 12

13 Post Layout Simulation Results CML I/O Buffer Power supply of only 0.6V, with 1.6mA of total current consumption due to amplitude boosted inductors Provides 240mV peak-to-peak differential signal and 453fs jitter with 12.8Gb/s bandwidth After passing through TSI, the peakto-peak voltage reduces to 196mV CML Output waveform After passing through TSI 13

14 Conclusion Two 2.5D I/O circuits are designed for 3mm TSI T-line in UMC 65nm Pre-emphasis is used in the LVDS buffer, and wide-band inductor matching is used in the CML buffer Post layout simulation results show that the proposed LVDS buffer and CML buffer are capable of providing speed at 10Gb/s and 12.8Gb/s with 0.48pJ/bit and 0.075pJ/bit efficiency, respectively 14

15 Thank You! Please send comments to Acknowledgement: funding support from MOE-Tier-2 fund (ARC 5/11) and A*STAR SERC-PSF fund 15