Adiabatic Logic. Yasmine Badr NanoCAD Lab. A major part of the contents is from Reference 1
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1 Adiabatic Logic Yasmine Badr NanoCAD Lab A major part of the contents is from Reference 1 1
2 Terminology Reversible logic: circuits that have one-to-one mapping between vectors of inputs and outputs Adiabatic : from thermodynamics Process in which there is no exchange of heat with the environment 2
3 History Landauer (1961): Logically irreversible operations in a physical computer necessarily dissipate energy Logically reversible operations can be performed without dissipation Later, found that that a gate can work energetically reversible without the need to be logically reversible. 3
4 Adiabetic Circuits Energy reused rather than just dissipated Power advantage 4
5 Conventional CMOS Constant voltage Energy dissipated per transition =CV dd2 /2 Pull up: energy dissipated on PMOS Pull down: charge dissipated via NMOS to ground Energy used only once 5
6 Adiabatic Logic Supply is a power clock (ramp) Pull down path: to power supply 6
7 Adiabatic Logic Energy Dissipation i(t)=c dv/dt =c Vdd/T (Constant Current) Energy during transition time T = I 2 *R*T = R* C 2 * V dd2 /T Equivalent circuit 7
8 CMOS Adiabatic Dissipated energy in pull up and pull down = CV dd 2 Depends on C and Vdd only Dissipated energy in charge and recovery = 2*R* C 2 * V dd2 /T Depends on size of transistor and T as well Slower circuit is charged less energy dissipation T>2RC Adiabatic has less energy dissipation if we assume activity factor of 1 8
9 Adiabatic Logic Families Adiabatic system has: Digital core: adiabatic gates Generator of power clock signals 4-phase power clock for cascaded gates Efficient generation essential for high energy saving factor Two of the most popular Efficient Charge Recovery Logic (ECRL) Positive Feedback Adiabatic Logic (PFAL) 9
10 1-ECRL Inverter Logic implemented using NMOS 2 cross coupled PMOS to store info For a different function e.g. NAND a series connection of 2 NMOS instead of N F, using A and B as input s. 2 parallel transistors, having A and B as inputs instead of N F 1
11 1-ECRL Buffer/Inverter (cont d) Input signal is shifted by 9 degrees w.r.t to the power clock 11
12 1-ECRL Buffer/Inverter (cont d) Power clock ramping up from to Vdd Out follows Power clock >V thp φ 1 12
13 1- ECRL Buffer/Inverter (cont d) Power clock ramping down from Vdd to zero Both inputs are now zero Because preceding stage is now recovering energy Not strictly complementary N1 and N2 off >V thp Discharge path 13
14 1- ECRL Buffer/Inverter (cont d) Φ < V th,p Fraction of energy <V thp = ½ C out V 2 th,p dissipated or reused next cycle according to succeeding input signal Quasi-adiabatic V thp 14
15 2-PFAL Inverter/buffer Consists of: Latch made of 2 crosscoupled inverters Logic function 15
16 ERCL vs PFAL ERCL: less number of transistors PFAL: Functional block parallel to PMOS less equivalent resistance less energy dissipated (R* C 2 * V dd2 /T) 16
17 4-Phase Power clock for Cascade More than 1 power clock used to operate adiabatic system ERCL and PFAL use 4-phase power clock φ-φ3 Because input has to be stable in evaluation phase ERCL and PFAL: 9 phase shift between subsequent phases is obtained 17
18 4-Phase Power clock for Cascade (cont d) 4 Phases: Evaluate (E): outputs are evaluated from stable input signals Hold (H): outputs are kept stable to supply subsequent gate with stable input signal. Recover (R): Energy is recovered Wait (W): for symmetry reasons because symmetric signals are easier to generate 18
19 Power Supply LC circuit Stepwise charging Charging of output to VDD is not done abruptly, but is divided into N steps 19
20 Cons and Pros - Slower than conventional CMOS - Requires special power supply - Area (but we get function and its complement) + Less Power if high switching activity or disconnect system from power supply while idle (sleep transistors) 2
21 References 1. Teichmann, Philip; Adiabatic Logic; Springer; Vitányi, P.; Time, space, and energy in reversible computing; Proceedings of the 2nd conference on Computing frontiers, ACM, 25, Pahlavan,B; Evaluation of Trends in Adiabatic Logic for Low Power Design cts/midterm/pahlavanghanadanskucha.pdf 4. Frank, M; Reversible Computing and Truly Adiabatic Circuits: Truly Adiabatic Circuits: The Next Great Challenge for Digital Engineering; Sanjay Kumar; Design Of Low Power Cmos Cell Structures Based On Adiabatic Switching Principle; Master Thesis; 29 21
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