Keywords: Software Radio Receiver, Software radio receiver, High-speed DDC, OR1200 CPU, SoC. Broad Band ADC

Transcription

1 Advanced Materials Research Online: ISSN: , Vols , pp doi: / Trans Tech Publications, Switzerland Design of a SoC With High-Speed DDC for Software Radio Receiver Jun Deng 1, a, Lintao Liu 2, Yujing Li 1, Xiaozong Huang 1, Xu Huang 1, and Luncai Liu 1 1 Sichuan Institute of Solid-state Circuits, Chongqing,China, Science and Technology on Analog Integrated Circuit Laboratory,Chongqing, China, a dj_richard@126.com Keywords: Software Radio Receiver, Software radio receiver, High-speed DDC, OR1200 CPU, SoC. Abstract. This paper presents a novel scheme for software radio receiver application, which integrates a high-speed digital down converter (DDC) block into a SoC (system on chip) based on OR1200 CPU. The proposed design can transform intermediate frequency (IF) signal to baseband signal and realize the real-time baseband signal processing. The simulation results indicate that the design is capable of accepting data at a 200MHz sample rate and the verification results based on Xilinx FPGA show that the SFDR of DDC can reach to 70.59dBFS.The synthesized results on 0.18um CMOS technology reveal that the maximum clock frequency can reach to 116MHz and the total area is 5.662mm2, and the corresponding power consumption is below 150mW. It should have a good potential for wireless communication applications. Introduction Software radio (SR) is widely used in modern wireless communication systems, duo to the flexibility of software radio over traditional wireless communication systems. The basic idea of SR is to move the analog-to-digital converter (ADC) as close as possible to the RF antenna and a variety of functions are realized by digital signal processing, however, DSP or microprocessor are difficult to process the high-speed data from ADC directly. Digital down converter (DDC) is the main part of the software radio receiver, because which converts the intermediate frequency (IF) signal into digital base-band signal and reduces the sampling rate to facilitate the subsequent signal processing while retaining all the information. The main programs of the structure of software radio receiver depict as follows. One is the implementation based-on ASIC, which lacks flexibility; the general-purpose DSP implementation has excellent programmability, however which requires an efficient algorithm to reduce the computational complexity in order to meet system performance requirements[1]; the present main idea is the combination of FPGA and DSP, However, this scheme needs to consider a number of factors, such as handshaking timing between FPGA and DSP, etc. With the continuous advancement of integrated circuit manufacturing process, SoC(system on chip) has become the development trend of IC design. This paper proposes a novel scheme, which integrates the independent DDC IP, 32-bit RISC CPU and other peripheral IPs into a SoC, as shown in Figure.1. This scheme replaces the combination functions of FPGA and DSP and allows the design of the software radio receiver system more flexible, higher integration and more reliable. antenna SoC RF Broad Band ADC DDC real time / quasi-real time DSP software Fig.1 Proposed scheme of software ratio receiver All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications, (ID: , Pennsylvania State University, University Park, USA-17/05/16,07:24:05)

2 1876 Advanced Designs and Researches for Manufacturing Design of DDC Among an all-digital IF receiver, DDC has become a cornerstone technology in wireless communication systems[2-3]. The main function of DDC is mixing the IF signal from ADC with a digitized cosine for In-phase channel (I-channel) and a digitized sine for the quadrature channel (Q-channel), and down-converting to low-frequency digital baseband signal, then decreasing the sampling rate into an original sampling rate to facilitate the subsequent signal processing. The designed DDC architecture consists of a digital mixer, numerically controlled oscillator (NCO) and digital filter banks. The DDC is divided into I and Q channels, the two data channels share the same NCO unit. The digital filter group was divided into the CIC (cascaded-integrator-comb) filter module, CIC compensation filter modules and the half-band filter module[4]. DDC block diagram is shown in Figure 2. S(n) I CIC Filter Inverse CIC Filter Filter bank HB Filter I(n) Q CIC Filter Inverse CIC Filter HB Filter Q(n) FCW NCO Filter bank Fig.2 Architecture of DDC The NCO consists of a phase accumulator, truncation function and a sine/cosine mapping function, as shown in Figure.3. The phase accumulator is used to receive the normalized Frequency Control Word (FCW), generate an input angle, the frequency accuracy of which is determined by the input of FCW. FCW is obtained by equation (1). f FCW 2 f c N (1) s Where fc is the natural frequency of the NCO output, fs is the sampling frequency, N is the accumulator word length. FCW M phase accumulator M reg θ' M truncation Sin/cos mapping function Fig.3 Structure of NCO Θ sin(2πnf) D cos(2πnf) D Architecture of SoC The proposed SoC system architecture shows in Figure.4.The system takes the 32-bit RISC CPU based-on OpenRISC 1200 as the core of control modules for the entire SoC design. The OR1200 CPU supports IEEE-754 compliant single precision floating point, and contains a MAC unit in order to better support digital signal processing (DSP) applications. All other peripheral modules communicate with CPU through the Wishbone on-chip bus. Wishbone bus is used to connect the master and slave devices and ensured the correct transmission of data between the master and slave devices. The JTAG module is used to download and debug of the bootloader and the application programs; The UART module is used to print debug information as well as the communication transmission between the SoC and external equipment; Memory Controller can be flexible to mount Flash memory, the SSRAM or SDRAM, in order to achieve storage capabilities of the system; DMA module as a master on Wishbone bus can realize a large number of data transfer between the memory and the peripheral such as DDC, and which can also be initiated by CPU for different applications. DDC module is the core processing part of the whole design, in order to meet the Wishbone bus read and write timing requirements, The DDC top module includes an specialized interface unit, which is used to implement the communications between DDC and the Wishbone bus interface. So

3 Advanced Materials Research Vols the DDC module can also be integrated into the other SoC system architecture, just needing to modify the bus timing interface unit. Obviously the DDC has been a reused IP core. DEBUG OpenRISC DMA DDC WISHBONE BUS PLL MEMCTRL UART Other IP HW/SW Co-verification for SoC Fig.4 Architecture of SoC based on OR1200 In order to verify the functionality of the SoC, a board-level hardware verification platform based on Xilinx FPGA has been built. The RF front-end processes the radio frequent signal of 0.5 ~ 4GHz received by antenna then the output ports of the RF provide data whose center frequency locates in 10 ~ 60MHz for ADC. The ADC, whose sampling clock ranges from 50 to 250Mhz, can supply 14-bit signed data in parallel, as well as a 50 ~ 250Mhz synchronous clock signal which will be used as a sampling clock by the follow-up circuits. Due to what ADC sent to the FPGA is the IF data, Personality Module Connectors, which are the High-speed I/O interface on the Xilinx ML510 development board, are adopted to ensure the high-speed data paths between the ADC and the DDC module of the SoC prototype. Board-level verification platform block diagram shows in Figure 5. This platform will realize the hardware and software co-verification, besides this platform can utilize the ChipScope Pro(a EDA tool of the Xilinx, Inc.) to analyze the DDC module further. Results of simulation and verification Fig.5 The HW/SW verification platform based FPGA Hardware for DDC is implemented with Verilog HDL and functional verified by VCS and Debussy. The simulated input carrier of DDC equals 200MHZ and output carrier of DDC is shifted to 10 MHz. Figure.6 shows the waveforms of 3-stage DDC output. Fig.6 Waveforms of 3-stage DDC The main parameters are depicted in Table.1. Tab.1 DDC main parameters description Main Parameters Description Decimation factor 20 Input /output data width 14 output frequency of NCO Programmable Input Clock 200 MHz Output Clock 10 MHz Band Rejection 70dB Signal Bandwidth 2MHz DDC Spurious Free Dynamic Range 70dB

4 1878 Advanced Designs and Researches for Manufacturing With Xilinx ISE software, the bitstream of the SoC downloads into the FPGA, and then bootloader and application programs are downloaded through the SoC JTAG. The clock signal of SoC is set to 100Mhz, and the spectrum of RF input signal of the platform is centered at 1Ghz, the spectrum of the output IF signal of ADC on the platform is centered at 10.02Mhz, and the frequency of synchronous clock from ADC output is 50Mhz.The starting-up and running feedback information from SoC prototype system can be observed through the serial debugging software, and the output of the sampling signals for ADC and DDC modules can be observed and analyzed with ChipScope Pro of Xilinx. As shown in Figure.7, the sampling period of the ChipScope Pro is set to 20ns, the sampling waveform of ADC output includes 5 points at a period approximately, which indicates that the frequency of ADC output is about 10Mhz (T=20ns*5=100ns, the sampling period of ADC output), and the sampling of DDC output includes 2500 points per period, which illustrates that the frequency of DDC output is about 0.02Mhz (T=20ns*2500=50000ns). Consequently, fig.7 demonstrates that DDC of the SoC can work well. Fig.7 Waveform of ADC and DDC : (a) waveform of ADC output;(b) waveform of DDC output. The data, down-converted by DDC, has been exported from the ChipScope analyzer of Xilinx, then analyzed with FFT analyzing software. The spectrum analysis of the DDC output shows in Figure.8, the SFDR of the DDC output is about 70.59dBFS, and the SNR is 67.86dBFS, which meet the demanding parameters required. Fig.8 Spectrum analysis of the DDC output The synthesized results of the proposed SoC architecture on SMIC 0.18um reveals a maximum clock frequency of 116MHz and a total area of 5.662mm2, and the corresponding power consumption is below mw. Conclusions This paper presents a novel scheme for the software ratio receiver application, which integrates the high-speed DDC, the 32-bit RISC CPU with Floating point unit and other peripherals into a SoC, In order to verify the functionality of the SoC,we use the ML510 development board of Xilinx as the FPGA prototyping system to implement board-level hardware verification platform. The results indicate that the SoC is capable of accepting data at a 200MHz sample rate and SFDR of the DDC is about 70dB. This design can be applied in the wireless communication system which is high requirement in speed and scale precision, and have a wide application foreground.

5 Advanced Materials Research Vols References [1] Srikanteswara, S.; Palat, R.C.; Reed, J.H.; et al. An Overview of Configurable Computing Machines for Software Radio Handsets[J]. Communications Magazine, IEEE, 2003(41): [2] G. Zhang, D. Al-Khalili, R. Inkol et al., "A Novel approach to the design of I/Q demodulation filters", Vision, Image and Signal Processing, IEE Proceedings, vol.141, no.3, 1994, pp [3] Reed, J.H. Software radio: a modern approach to radio engineering. Prentice Hall PTR, Upper Saddle River, NJ, 2002:1-21, [4] YuJing Li, LinTao Liu, Xu Huang, et al., "Design and ASIC Implementation of High-Speed DDC",in proc. IEEE international Conference on Digital Manufacturing and Automation (ICDMA,2011),pp

6 Advanced Designs and Researches for Manufacturing / Design of a SoC With High-Speed DDC for Software Radio Receiver /