Packaging Technology 2
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1 2 2.1 Introduction his chapter describes various hip Scale ackages (Ss) from Intel and the wireless products contained inside of them, including examples of the mechanical dimensions, their applications, and other packaging information. his chapter is in two parts: he first part is dedicated to discrete and stacked packages for Intel lash emory and technologies. he second part is dedicated to packages for Intel ersonal Internet lient rchitecture (Intel ) ellular rocessors. ote: lease refer to specific product datasheets for actual package dimensions. hese mechanical dimensions are examples only and actual size may vary depending on product. 2.2 roduct ackages for lash emory ou can choose the package for your application based on various package criteria such as package size, cost, ease-of-use, and life cycle/migration. enerally, ease-of-use and life cycle/migration are important package criteria for the traditional embedded application. ypically, an embedded application design goes through very few subsequent design phases and is intended to have a long application product life. he asy all rid rray (asy ) was the first package designed specifically for embedded applications using an Intel lash emory device. With emergence of the handheld wireless industry, the trend for packaging has moved from the traditional embedded package to the much smaller hip Scale ackage (S) to take advantage of the small form factor. he Very hin rofile ine itch (V-) was introduced in the late '90's as the discrete or monolithic one-die S of choice for wireless applications. s the handheld wireless industry grows and new features are added while the form factor continues to shrink, stacking individual dies into one package has become the new packaging revolution. he Stacked hip Scale ackage (SS) has begun to emerge and the trend has shifted from the iscrete S to the Stacked S (SS). his trend continues and is advancing quickly as silicon and packaging technologies merge to provide smaller form factor packaging solutions such as the Intel Ultra-hin Stacked hip Scale ackage (Intel U-SS). he following sections discuss these packages for flash memory, beginning with the most current as follows: Section 2.2.1, Intel U-SS for lash emory Section 2.2.2, SS for lash emory Section 2.2.3, V- ackage for lash emory Section 2.2.4, asy ackage for lash emory Intel Wireless ommunications and omputing ackage User s uide 2-1
2 2.2.1 Intel U-SS for lash emory he Intel Ultra-hin Stacked hip Scale ackage (Intel U-SS) for flash memory is created by taking a SS and reducing the size through a series of material set changes. hese changes include, for example, thinning or back-grinding the die to 3.0 mil (~75 µm) and reducing the size of the solder balls. he initial Intel U-SS packages use a laminate substrate in a family of products that stack flash and S or S in x16 bus width products. (See igure 2-1, Intel U-SS for lash emory (xample) on page 2-2 and igure 2-2, Intel U-SS Substrate ackage for lash emory (xample) on page 2-3.) uture variations of Intel U-SS for high performance products will stack flash memory and low-power S in x16 and x32 bus width products. igure 2-1. Intel U-SS for lash emory (xample) 0.8 mm all itch aminate 2-2 Intel Wireless ommunications and omputing ackage User s uide
3 igure 2-2. Intel U-SS Substrate ackage for lash emory (xample) 1 Index ark S1 S2 e J J b op View - all own ottom View - all Up 2 1 rawing not to scale. ote: imensions 1, 2, and b are preliminary illimeters Inches imensions Symbol in om ax otes in om ax ackage eight all eight ackage ody hickness all (ead) Width b ackage ody ength ackage ody Width itch e all (ead) ount Seating lane oplanarity orner to all 1 istance long S orner to all 1 istance long S Intel Wireless ommunications and omputing ackage User s uide 2-3
4 2.2.2 SS for lash emory he SS for flash memory takes advantage of multiple application requirements, including combining flash, S, and S into one package as shown in igure 2-3, SS for lash emory (xample) on page 2-4. his type of packaging provides the maximum space savings advantage by eliminating other individual memory packages from the application and stacking them vertically in a single package. lthough the package may have a larger ball pitch compared to the V- package (0.8 mm vs mm), the overall area of the SS is much smaller than the combined area of the separate components. lso, by stacking vertically, a SS package allows higher density in a smaller form factor package. his is accomplished by stacking a low-density die as opposed to using a single largedensity die that consumes more silicon area. While the first SS packages from Intel contained only two dies (i.e., one flash die and one S die) and measured 1.4 mm in profile height, recent SS technology has improved to reduce two stacked dies to 1.2 mm profile height. he total die count has also increased by adding up to four dies while keeping the profile height to only 1.4 mm. here is also a trend to include only one flash die in a SS package, using the same ballout (electrical interface footprint). departure from designing in the traditional V- S for discrete flash-only requirements, this new approach provides a single ballout and a migration path to future stacking when the application requires it. single ballout eliminates the need to redesign the when migrating from a discrete V- package to a SS, and it also allows Os a single ballout for multiple product platforms. igure 2-3. SS for lash emory (xample) Silicon ie 0.8 mm all itch aminate 2-4 Intel Wireless ommunications and omputing ackage User s uide
5 igure 2-4. SS rawing and imensions for lash emory (xample) 1 Index ark S1 S2 e J J b op View - all own ottom View - all Up 2 1 rawing not to scale. illimeters Inches imens ions Symbol in om ax otes in om ax ackage eight all eight ackage ody hickness all (ead) Width b ackage ody ength ackage ody Width itch e all (ead) ount Seating lane oplanarity orner to all 1 istance long S orner to all 1 istance long S Intel Wireless ommunications and omputing ackage User s uide 2-5
6 2.2.3 V- ackage for lash emory he flash memory V- package is a Very hin, ine-pitch all rid rray discrete package. s shown in igure 2-5, V- ackage for lash emory (xample) on page 2-6, it has a 0.75 mm ball pitch and a smaller ball size than the asy package. It is also a low profile package, measuring 1.0 mm maximum package height. It is intended for handheld wireless devices where no additional is included in the package. he package drawing and dimensions are shown in igure 2-6, V- ackage rawing and imensions for lash emory (xample) on page 2-7. igure 2-5. V- ackage for lash emory (xample) Silicon ie aminate 0.75mm all itch 2-6 Intel Wireless ommunications and omputing ackage User s uide
7 igure 2-6. V- ackage rawing and imensions for lash emory (xample) 1 Index ark S1 1 Index ark S2 e b op View - all Side own ottom View - all Side Up 1 2 Side View Seating lane ote: rawing not to scale illimeters Inches imensions Symbol in om ax otes in om ax ackage eight all eight ackage ody hickness all (ead) Width b ackage ody ength (64b, 128b) ackage ody Width (64b, 128b) itch e all (ead) ount Seating lane oplanarity orner to all 1 istance long S orner to all 1 istance long S asy ackage for lash emory he asy package, shown in igure 2-7, asy ackage for lash emory (xample) on page 2-8, was designed to be the Intel lash emory package of choice for embedded applications. While offering a larger ball pitch and ball size compared to other Ss, the asy package also maintains the benefit of smaller size, measuring about one-half the size of the equivalent SO package, with a 1.2 mm profile height. Intel Wireless ommunications and omputing ackage User s uide 2-7
8 nother advantage of the asy package is its constant package size/footprint with respect to memory density upgrades and die shrinks. key element of embedded applications is the need for long product life cycles, from 5 to 7 years, that require the same package size/footprint. herefore, the package size/footprint must remain constant over time, while memory densities increase and die sizes shrink. his attribute is very beneficial because many embedded applications increase in memory density over time to incorporate additional functionality. he package drawing and dimensions are shown in igure 2-8, asy ackage rawing and imensions for lash emory (xample) on page 2-9. igure 2-7. asy ackage for lash emory (xample) Silicon ie arge Solder alls 1.0mm all itch 2-8 Intel Wireless ommunications and omputing ackage User s uide
9 igure 2-8. asy ackage rawing and imensions for lash emory (xample) all 1 orner S 1 all 1 orner S 2 e b op View - lastic ackside omplete Ink ark ot Shown 1 ottom View - all Side Up 2 Seating lane illimeters Inches imensions Symbol in om ax otes in om ax ackage eight all eight ackage ody hickness all (ead) Width b ackage ody Width (64b, 128b, 256b) ackage ody ength (64b, 128b) ackage ody ength (256b) itch [e] all (ead) ount Seating lane oplanarity orner to all 1 istance long (64/128/256b) S orner to all 1 istance long (64/128b) S orner to all 1 istance long (256b) S Intel Wireless ommunications and omputing ackage User s uide 2-9
10 2.3 roduct ackages for Intel ellular rocessors his section discusses the following packages for Intel ersonal Internet lient rchitecture (Intel ) ellular rocessors: Section 2.3.1, Intel olded-ss for Intel ellular rocessors Section 2.3.2, SS for Intel ellular rocessors Section 2.3.3, V- ackage for Intel ellular rocessors Section 2.3.4, ackage for Intel ellular rocessors Intel olded-ss for Intel ellular rocessors he Intel olded Stacked hip Scale ackage (Intel olded-ss) delivers solutions for multiple applications by providing the ability to combine different products in a single footprint. he package is developed by placing memory or other bus interconnects on the top surface. hen a separate package is mounted to these bus interconnects. his permits a high degree of flexibility by allowing products to be manufactured with different memory configurations. or the end user, this single folded package provides high performance products while reducing parts count and board space. he Intel olded-ss technology provides the same density advantages as the SS. xamples of the Intel olded Stacked hip Scale ackage (Intel olded-ss) are shown in: igure 2-10, Intel olded-ss for Intel ellular rocessor (8x11 op xample) on page 2-11 igure 2-11, Intel olded-ss for Intel ellular rocessor (11x13 op xample) on page 2-12 igure 2-9. Intel olded-ss ackage for Intel ellular rocessors (xample) 2-10 Intel Wireless ommunications and omputing ackage User s uide
11 igure Intel olded-ss for Intel ellular rocessor (8x11 op xample) all 1 orner U V W U V W S all 1 orner e S2 op View - ottom ackage all side down Side View b ottom View -ottom ackage all Side Up omplete Ink ark ot Shown 2 1 Seating lane illimeters Inches Symbol in om ax otes in om ax acakge eight all eight ackage ody hickness all (ead) Width b ottom ackage ody Width ottom ackage ody ength op ackage ody Width op ackage ody ength itch [e] all (ead) ount Seating lane oplanarity orner to all 1 istance long S orner to all 1 istance long S ote: nglish units are for reference only ontrolling dimensions: millimeter Intel Wireless ommunications and omputing ackage User s uide 2-11
12 igure Intel olded-ss for Intel ellular rocessor (11x13 op xample) all 1 orner U V W U V W S all 1 orner e S2 op View - ottom ackage all side down Side View b ottom View -ottom ackage all Side Up omplete Ink ark ot Shown 2 1 Seating lane illimeters Inches Symbol in om ax otes in om ax acakge eight all eight ackage ody hickness all (ead) Width b ottom ackage ody Width ottom ackage ody ength op ackage ody Width op ackage ody ength itch [e] all (ead) ount Seating lane oplanarity orner to all 1 istance long S orner to all 1 istance long S ote: nglish units are for reference only ontrolling dimensions: millimeter 2-12 Intel Wireless ommunications and omputing ackage User s uide
13 2.3.2 SS for Intel ellular rocessors he SS takes advantage of multiple application requirements, including combining the processor, S, and S into one package. his package has a 0.65 mm ball pitch and provides a space savings advantage by eliminating other individual memory packages from the application and stacking them vertically in a single package. herefore, the overall area of the SS is much smaller than the combined area of the separate components. n example of a SS package includes igure 2-13, SS (ypical 0.65 itch) rawing for Intel X26X (xample) on page igure SS for Intel ellular rocessors (xample) Silicon ie 0.65 mm all itch aminate Intel Wireless ommunications and omputing ackage User s uide 2-13
14 igure SS (ypical 0.65 itch) rawing for Intel X26X (xample) all 1 orner S 1 all 1 orner U V U V e S2 op View - all side down omplete Ink ark ot Shown b ottom View - all Side Up 1 2 Seating lane illimeters Inches Symbol in om ax otes in om ax acakge eight all eight ackage ody hickness all (ead) Width b ackage ody Width ackage ody ength itch [e] all (ead) ount Seating lane oplanarity orner to all 1 istance long S orner to all 1 istance long S Intel Wireless ommunications and omputing ackage User s uide
15 2.3.3 V- ackage for Intel ellular rocessors he V- package is a very thin, fine pitch discrete package with a reduced ball pitch and small ball size. It is also a low profile package, intended for handheld wireless devices where no additional is included in the package. xamples of V- packages for Intel ellular rocessors include those shown in the following paired figures: igure 2-14, V- ackage (0.50 itch) for Intel ellular rocessors (xample) on page 2-15 and igure 2-15, V- rawing (0.50 itch) for Intel ellular rocessors (xample) on page 2-16 igure 2-16, V- ackage (0.65 itch) for Intel ellular rocessors (xample) on page 2-17 and igure 2-17, V- (0.65 itch) rawing for the Intel X800 rocessor (xample) on page 2-18 igure 2-18, V- ackage (0.50 itch) for Intel ellular rocessors (xample) on page 2-18 and igure 2-19, V- (0.50 itch) rawing for an Intel X-Scale rocessor (xample) on page 2-19 igure V- ackage (0.50 itch) for Intel ellular rocessors (xample) Silicon ie aminate 0.50 mm all itch Intel Wireless ommunications and omputing ackage User s uide 2-15
16 igure V- rawing (0.50 itch) for Intel ellular rocessors (xample) all 1 orner S 1 all 1 orner e S2 b op View - all side down omplete Ink ark ot Shown ottom View - all Side Up 1 2 Seating lane illimeters Inches Symbol in om ax otes in om ax acakge eight all eight ackage ody hickness all (ead) Width b ackage ody Width ackage ody ength itch [e] all (ead) ount Seating lane oplanarity orner to all 1 istance long S orner to all 1 istance long S Intel Wireless ommunications and omputing ackage User s uide
17 igure V- ackage (0.65 itch) for Intel ellular rocessors (xample) Silicon ie aminate 0.65 mm all itch Intel Wireless ommunications and omputing ackage User s uide 2-17
18 igure V- (0.65 itch) rawing for the Intel X800 rocessor (xample) all 1 orner S 1 all 1 orner U U e S2 op View - all side down omplete Ink ark ot Shown b ottom View - all Side Up 2 1 Seating lane illimeters Inches Symbol in om ax otes in om ax acakge eight all eight ackage ody hickness all (ead) Width b ackage ody Width ackage ody ength itch [e] all (ead) ount Seating lane oplanarity orner to all 1 istance long S orner to all 1 istance long S igure V- ackage (0.50 itch) for Intel ellular rocessors (xample) Silicon ie aminate 0.50 mm all itch 2-18 Intel Wireless ommunications and omputing ackage User s uide
19 igure V- (0.50 itch) rawing for an Intel X-Scale rocessor (xample) all 1 orner S 1 all 1 orner S2 J J U V W U V W e b op View - all side down omplete Ink ark ot Shown ottom View - all Side Up 2 1 Seating lane able 2-1. V- imensions for an X-Scale rocessor (xample) illimeters Inches escription Symbol in om ax in om ax otes ackage eight all eight ackage ody hickness all (ead) Width b ackage ody Width ackage ody ength itch [e] all (ead) ount Seating lane oplanarity orner to all 1 istance along S orner to all 1 istance along S Intel Wireless ommunications and omputing ackage User s uide 2-19
20 2.3.4 ackage for Intel ellular rocessors he plastic ball grid array () package is a popular alternative for high I/O devices in the industry. Its advantages over leadframe packages are many. aving no leads to bend, the greatly reduces coplanarity problems and minimizes handling issues, especially during rework. Its pin count can be much higher than leadframes (i.e., 800 vs. 208), limited by package body size and ball pitch requirements. uring reflow the solder balls are self-centering (up to 50% off the pad), thus reducing placement problems during surface mount. ormally, because of the larger ball pitch (typically 1.27 mm) of a over a Q or Q, the overall package and board assembly yields can be better. rom a performance perspective, thermals can be enhanced through center thermal balls and a heat slug embedded in mold cap. lectricals can be improved through package plane layers. he has an improved design-to-production cycle time because it is well understood by the industry. It can also be used in multi-chip module configurations where dies are side-by-side or stacked. igure ackage (1.0 itch) for Intel ellular rocessors (xample) Silicon ie ie aminate 1.0 mm all itch 2-20 Intel Wireless ommunications and omputing ackage User s uide
21 igure rawing for the Intel X255 rocessor (xample) all 1 orner S 1 all 1 orner e S2 b op View - all side down omplete Ink ark ot Shown ottom View - all Side Up 1 2 Seating lane illimeters Inches Symbol in om ax otes in om ax acakge eight all eight ackage ody hickness all (ead) Width b ackage ody Width ackage ody ength itch [e] all (ead) ount Seating lane oplanarity orner to all 1 istance long S orner to all 1 istance long S Intel Wireless ommunications and omputing ackage User s uide 2-21
22 2-22 Intel Wireless ommunications and omputing ackage User s uide
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