128K x 8 HIGH-SPEED CMOS STATIC RAM
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1 128K x 8 HIGH-SPEED CMOS STATIC RAM DECEMBER 2011 FEATURES HIGH SPEED: (IS63/64WV1288DALL/DBLL) High-speed access time: 8, 10, 12, 20 ns Low Active Power: 135 mw (typical) Low Standby Power: 12 µw (typical) CMOS standby LOW POWER: (IS63/64WV1288DALS/DBLS) High-speed access time: 25, 35 ns Low Active Power: 55 mw (typical) Low Standby Power: 12 µw (typical) CMOS standby Single power supply Vdd 1.65V to 2.2V (IS63WV1288DAxx) Vdd 2.4V to 3.6V (IS63/64WV1288DBxx) Multiple center power and ground pins for greater noise immunity Easy memory expansion with CE and OE options CE power-down Fully static operation: no clock or refresh required TTL compatible inputs and outputs Lead-free available DESCRIPTION The ISSI IS63/64WV1288Dxxx is a very high-speed, low power, 131,072-word by 8-bit CMOS static RAM. The IS63/64WV1288DBLL is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 25 µw (typical) with CMOS input levels. The IS63/64WV1288DBLL operates from a single Vdd power supply. The IS63/64WV1288Dxxx is available in 32-pin TSOP (Type II), 32-pin stsop (Type I), 48-Ball minibga (6mm x 8mm), 32-pin SOJ (400-mil) and 32- pin SOJ (300-mil) packages. FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K X 8 MEMORY ARRAY VDD GND I/O0-I/O7 I/O DATA CIRCUIT COLUMN I/O CE OE WE CONTROL CIRCUIT Copyright 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc
2 PIN CONFIGURATION 32-Pin SOJ PIN CONFIGURATION 32-Pin TSOP (Type II) (T) 32-Pin stsop (Type I) (H) A0 A1 A2 A3 CE I/O0 I/O1 VDD GND I/O2 I/O3 WE A4 A5 A6 A A16 A15 A14 A13 OE I/O7 I/O6 GND VDD I/O5 I/O4 A12 A11 A10 A9 A8 A0 A1 A2 A3 CE I/O0 I/O1 VDD GND I/O2 I/O3 WE A4 A5 A6 A A16 A15 A14 A13 OE I/O7 I/O6 GND VDD I/O5 I/O4 A12 A11 A10 A9 A8 PIN DESCRIPTIONS A0-A16 Address Inputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Bidirectional Ports Vdd GND Power Ground PIN CONFIGURATION 48-mini BGA (B) (6 mm x 8 mm) A NC OE A2 A6 A7 NC B C D E F G H I/O 0 NC A1 A5 CE I/O 7 I/O 1 NC A0 A4 NC I/O 6 GND NC NC A3 NC VDD VDD NC NC NC NC GND I/O 2 NC A14 A11 I/O 4 I/O 5 I/O 3 NC A15 A12 WE A8 NC A10 A16 A13 A9 NC 2 Integrated Silicon Solution, Inc.
3 TRUTH TABLE Mode WE CE OE I/O Operation Vdd Current Not Selected X H X High-Z Isb1, Isb2 (Power-down) Output Disabled H L H High-Z Icc1, Icc2 Read H L L Dout Icc1, Icc2 Write L L X Din Icc1, Icc2 ABSOLUTE MAXIMUM RATINGS (1) Symbol Parameter Value Unit Vterm Terminal Voltage with Respect to GND 0.5 to Vdd+0.5 V Tstg Storage Temperature 65 to +150 C Pt Power Dissipation 1.5 W Vdd Vdd Related to GND -0.2 to +3.9 V Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Integrated Silicon Solution, Inc. 3
4 AC TEST CONDITIONS Parameter Unit Unit Unit (2.4V-3.6V) (3.3V + 5%) (1.65V-2.2V) Input Pulse Level 0.4V to Vdd - 0.3V 0.4V to Vdd - 0.3V 0.4V to Vdd - 0.3V Input Rise and Fall Times 1V/ ns 1V/ ns 1V/ ns Input and Output Timing VDD /2 VDD V and Reference Level (VRef) 2 Output Load See Figures 1 and 2 See Figures 1 and 2 See Figures 1 and 2 R1 ( Ω ) R2 ( Ω ) Vtm (V) 3.0V 3.3V 1.8V AC TEST LOADS R1 OUTPUT ZO = 50Ω 50Ω 30 pf Including jig and scope VDD/2 VTM OUTPUT 5 pf Including jig and scope R2 Figure 1. Figure 2. 4 Integrated Silicon Solution, Inc.
5 DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 3.3V + 5% Symbol Parameter Test Conditions Min. Max. Unit Voh Output HIGH Voltage Vdd = Min., Ioh = 4.0 ma 2.4 V Vol Output LOW Voltage Vdd = Min., Iol = 8.0 ma 0.4 V Vih Input HIGH Voltage 2 Vdd V Vil Input LOW Voltage (1) V Ili Input Leakage GND Vin Vdd 1 1 µa Ilo Output Leakage GND Vout Vdd, Outputs Disabled 1 1 µa Note: 1. Vil (min.) = 0.3V DC; Vil (min.) = 2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 2.4V-3.6V Symbol Parameter Test Conditions Min. Max. Unit Voh Output HIGH Voltage Vdd = Min., Ioh = 1.0 ma 1.8 V Vol Output LOW Voltage Vdd = Min., Iol = 1.0 ma 0.4 V Vih Input HIGH Voltage 2.0 Vdd V Vil Input LOW Voltage (1) V Ili Input Leakage GND Vin Vdd 1 1 µa Ilo Output Leakage GND Vout Vdd, Outputs Disabled 1 1 µa Note: 1. Vil (min.) = 0.3V DC; Vil (min.) = 2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Vdd = 1.65V-2.2V Symbol Parameter Test Conditions Vdd Min. Max. Unit Voh Output HIGH Voltage Ioh = -0.1 ma V 1.4 V Vol Output LOW Voltage Iol = 0.1 ma V 0.2 V Vih Input HIGH Voltage V 1.4 Vdd V Vil (1) Input LOW Voltage V V Ili Input Leakage GND Vin Vdd 1 1 µa Ilo Output Leakage GND Vout Vdd, Outputs Disabled 1 1 µa Note: 1. Vil (min.) = 0.3V DC; Vil (min.) = 2.0V AC (pulse width < 10 ns). Not 100% tested. Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested. Integrated Silicon Solution, Inc. 5
6 HIGH SPEED (IS63WV1288DALL/DBLL) OPERATING RANGE (Vdd) (IS63WV1288DALL) Range Ambient Temperature Vdd Speed Commercial 0 C to +70 C 1.65V-2.2V 20ns Industrial 40 C to +85 C 1.65V-2.2V 20ns Automotive 40 C to +125 C 1.65V-2.2V 20ns OPERATING RANGE (Vdd) (IS63WV1288DBLL) (1) Range Ambient Temperature Vdd (8 ns) 1 Vdd (10 ns) 1 Commercial 0 C to +70 C 3.3V + 5% 2.4V-3.6V Industrial 40 C to +85 C 3.3V + 5% 2.4V-3.6V Note: 1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%, the device meets 8ns. OPERATING RANGE (Vdd) (IS64WV1288DBLL) (2) Range Ambient Temperature Vdd (8 ns) 2 Vdd (10 ns) 2 Automotive 40 C to +125 C 3.3V + 5% 2.4V-3.6V Note: 2. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%, the device meets 8ns. POWER SUPPLY CHARACTERISTICS (1) (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit Icc Vdd Dynamic Operating Vdd = Max., Com ma Supply Current Iout = 0 ma, f = fmax Ind CE = Vil Auto. (3) Vin Vdd 0.3V, or typ. (2) Vin 0.4V Isb2 CMOS Standby Vdd = Max., Com µa Current (CMOS Inputs) CE Vdd 0.2V, Ind Vin Vdd 0.2V, or Auto Vin 0.2V, f = 0 typ. (2) 4 4 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25 o C and not 100% tested. 3. For Automotive grade at 15ns, typ. Icc = 38mA, not 100% tested. 6 Integrated Silicon Solution, Inc.
7 LOW POWER (IS63WV1288DALS/DBLS) OPERATING RANGE (Vdd) (IS63WV1288DALS) Range Ambient Temperature Vdd Speed Commercial 0 C to +70 C 1.65V-2.2V 45ns Industrial 40 C to +85 C 1.65V-2.2V 45ns Automotive 40 C to +125 C 1.65V-2.2V 55ns OPERATING RANGE (Vdd) (IS63WV1288DBLS) Range Ambient Temperature Vdd (35 ns) Commercial 0 C to +70 C 2.4V-3.6V Industrial 40 C to +85 C 2.4V-3.6V OPERATING RANGE (Vdd) (IS64WV1288DBLS) Range Ambient Temperature Vdd (35 ns) Automotive 40 C to +125 C 2.4V-3.6V POWER SUPPLY CHARACTERISTICS (1) (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit Icc Vdd Dynamic Operating Vdd = Max., Com ma Supply Current Iout = 0 ma, f = fmax Ind CE = Vil Auto Vin Vdd 0.3V, or typ. (2) 18 Vin 0.4V Isb2 CMOS Standby Vdd = Max., Com µa Current (CMOS Inputs) CE Vdd 0.2V, Ind Vin Vdd 0.2V, or Auto Vin 0.2V, f = 0 typ. (2) 4 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25 o C and not 100% tested. Integrated Silicon Solution, Inc. 7
8 READ CYCLE SWITCHING CHARACTERISTICS (1) (Over Operating Range) -8 ns -10 ns -12 ns Symbol Parameter Min. Max. Min. Max. Min. Max. Unit trc Read Cycle Time ns taa Address Access Time ns toha Output Hold Time ns tace CE Access Time ns tdoe OE Access Time ns tlzoe (2) OE to Low-Z Output ns thzoe (2) OE to High-Z Output ns tlzce (2) CE to Low-Z Output ns thzce (2) CE to High-Z Output ns tpu CE to Power Up Time ns tpd CE to Power Down Time ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V loading specified in Figure Tested with the loading specified in Figure 2. Transition is measured ±500 mv from steady-state voltage. Not 100% tested. READ CYCLE SWITCHING CHARACTERISTICS (1) (Over Operating Range) -20 ns -25 ns -35 ns -45 ns Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit trc Read Cycle Time ns taa Address Access Time ns toha Output Hold Time ns tace CE Access Time ns tdoe OE Access Time ns thzoe (2) OE to High-Z Output ns tlzoe (2) OE to Low-Z Output ns thzce (2 CE to High-Z Output ns tlzce (2) CE to Low-Z Output ns Notes: 1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mv from steady-state voltage. Not 100% tested. 3. Not 100% tested. 8 Integrated Silicon Solution, Inc.
9 AC WAVEFORMS READ CYCLE NO. 1 (1,2) t RC ADDRESS t OHA t AA t OHA DOUT PREVIOUS DATA VALID DATA VALID READ1.eps READ CYCLE NO. 2 (1,3) t RC ADDRESS t AA t OHA OE t DOE t HZOE CE t LZOE t LZCE t ACE t HZCE DOUT HIGH-Z DATA VALID CE_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = Vil. 3. Address is valid prior to or coincident with CE LOW transitions. Integrated Silicon Solution, Inc. 9
10 WRITE CYCLE SWITCHING CHARACTERISTICS (1,3) (Over Operating Range) -8 ns -10 ns -12 ns Symbol Parameter Min. Max. Min. Max. Min. Max. Unit twc Write Cycle Time ns tsce CE to Write End ns taw Address Setup Time to ns Write End tha Address Hold from ns Write End tsa Address Setup Time ns (1) tpwe 1 WE Pulse Width (OE High) ns (2) tpwe 2 WE Pulse Width (OE Low) ns tsd Data Setup to Write End ns thd Data Hold from Write End ns thzwe (2) WE LOW to High-Z Output ns tlzwe (2) WE HIGH to Low-Z Output ns Notes: 1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure Tested with the load in Figure 2. Transition is measured ±500 mv from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. WRITE CYCLE SWITCHING CHARACTERISTICS (1,2) (Over Operating Range) -20 ns -25 ns -35 ns -45ns Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit twc Write Cycle Time ns tsce CE to Write End ns taw Address Setup Time ns to Write End tha Address Hold from Write End ns tsa Address Setup Time ns tpwe1 WE Pulse Width (OE = HIGH) ns tpwe2 WE Pulse Width (OE = LOW) ns tsd Data Setup to Write End ns thd Data Hold from Write End ns thzwe (3) WE LOW to High-Z Output ns tlzwe (3) WE HIGH to Low-Z Output ns Notes: 1. Test conditions for IS61WV6416LL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mv from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 10 Integrated Silicon Solution, Inc.
11 AC WAVEFORMS WRITE CYCLE NO. 1 (1,2 (CE Controlled, OE = HIGH or LOW) t WC ADDRESS VALID ADDRESS t SA t SCE t HA CE WE t AW t PWE1 t PWE2 t HZWE t LZWE DOUT DATA UNDEFINED HIGH-Z t SD t HD DIN DATAIN VALID CE_WR1.eps Integrated Silicon Solution, Inc. 11
12 AC WAVEFORMS WRITE CYCLE NO. 2 (1) (WE Controlled, OE = HIGH during Write Cycle) t WC ADDRESS VALID ADDRESS t HA OE CE LOW WE t AW t PWE1 DOUT t SA DATA UNDEFINED t HZWE HIGH-Z t LZWE t SD t HD DIN DATAIN VALID CE_WR2.eps WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) t WC ADDRESS VALID ADDRESS OE LOW t HA CE LOW WE DOUT tsa DATA UNDEFINED t AW t HZWE t PWE2 HIGH-Z t LZWE t SD t HD DIN DATAIN VALID CE_WR3.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > Vih. 12 Integrated Silicon Solution, Inc.
13 HIGH SPEED (IS63/4WV1288DALL/DBLL) DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V) Symbol Parameter Test Condition Options Min. Typ. (1) Max. Unit Vdr Vdd for Data Retention See Data Retention Waveform V Idr Data Retention Current Vdd = 2.0V, CE Vdd 0.2V Com µa Ind. 55 Auto. 90 tsdr Data Retention Setup Time See Data Retention Waveform 0 ns trdr Recovery Time See Data Retention Waveform trc ns Note 1: Typical values are measured at Vdd = 3.0V, Ta = 25 o C and not 100% tested. DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V) Symbol Parameter Test Condition Options Min. Typ. (1) Max. Unit Vdr Vdd for Data Retention See Data Retention Waveform V Idr Data Retention Current Vdd = 1.2V, CE Vdd 0.2V Com µa Ind. 55 Auto. 90 tsdr Data Retention Setup Time See Data Retention Waveform 0 ns trdr Recovery Time See Data Retention Waveform trc ns Note 1: Typical values are measured at Vdd = 1.8V, Ta = 25 o C and not 100% tested. DATA RETENTION WAVEFORM (CE Controlled) tsdr Data Retention Mode trdr VDD VDR CE GND CE VDD - 0.2V Integrated Silicon Solution, Inc. 13
14 LOW POWER (IS63/4WV1288DALS/DBLS) DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V) Symbol Parameter Test Condition Options Min. Typ. (1) Max. Unit Vdr Vdd for Data Retention See Data Retention Waveform V Idr Data Retention Current Vdd = 2.0V, CE Vdd 0.2V Com µa Ind. 50 Auto. 75 tsdr Data Retention Setup Time See Data Retention Waveform 0 ns trdr Recovery Time See Data Retention Waveform trc ns Note 1: Typical values are measured at Vdd = 3.0V, Ta = 25 o C and not 100% tested. DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V) Symbol Parameter Test Condition Options Min. Typ. (1) Max. Unit Vdr Vdd for Data Retention See Data Retention Waveform V Idr Data Retention Current Vdd = 1.2V, CE Vdd 0.2V Com µa Ind. 50 Auto. 75 tsdr Data Retention Setup Time See Data Retention Waveform 0 ns trdr Recovery Time See Data Retention Waveform trc ns Note 1: Typical values are measured at Vdd = 1.8V, Ta = 25 o C and not 100% tested. DATA RETENTION WAVEFORM (CE Controlled) tsdr Data Retention Mode trdr VDD VDR CE GND CE VDD - 0.2V 14 Integrated Silicon Solution, Inc.
15 ORDERING INFORMATION Industrial Range: 40 C to +85 C Speed (ns) Order Part No. Package 8 IS63WV1288DBLL-8TI 32-pin TSOP (Type II) IS63WV1288DBLL-8TLI 32-pin TSOP (Type II), Lead-free IS63WV1288DBLL-8HI stsop (Type I) (8mm x13.4mm) IS63WV1288DBLL-8HLI stsop (Type I) (8mm x13.4mm), Lead-free IS63WV1288DBLL-8JI 32-pin SOJ (300-mil) IS63WV1288DBLL-8JLI 32-pin SOJ (300-mil), Lead-free 10 IS63WV1288DBLL-10TI 32-pin TSOP (Type II) IS63WV1288DBLL-10TLI 32-pin TSOP (Type II), Lead-free IS63WV1288DBLL-10HI stsop (Type I) (8mm x13.4mm) IS63WV1288DBLL-10HLI stsop (Type I) (8mm x13.4mm), Lead-free IS63WV1288DBLL-10JI 32-pin SOJ (300-mil) IS63WV1288DBLL-10JLI 32-pin SOJ (300-mil), Lead-free IS63WV1288DBLL-10KLI 32-pin SOJ (400-mil), Lead-free Automotive Range (A3): 40 C to +125 C Speed (ns) Order Part No. Package 10(8*) IS64WV1288DBLL-10TA3 32-pin TSOP (Type II) IS64WV1288DBLL-10TLA3 32-pin TSOP (Type II), Lead-free IS64WV1288DBLL-10HA3 stsop (Type I) (8mm x13.4mm) IS64WV1288DBLL-10HLA3 stsop (Type I) (8mm x13.4mm), Lead-free Note: 1. Speed = 8ns for Vdd = 3.3V + 5%. Speed = 10ns for Vdd = 2.4V-3.6V. Integrated Silicon Solution, Inc. 15
16 16 Integrated Silicon Solution, Inc.
17 SEATING PLANE NOTE : 1. Controlling dimension : mm 2. Dimension D and E1 do not include mold protrusion. 3. Dimension b2 does not include dambar protrusion/intrusion. 4. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test. 5. Reference document : JEDEC SPEC MS /19/2007 Integrated Silicon Solution, Inc. 17
18 18 Integrated Silicon Solution, Inc.
19 Integrated Silicon Solution, Inc. 19
20 NOTE : 1. CONTROLLING DIMENSION : MM. 2. Reference document : JEDEC MO-207 Package Outline 08/12/ Integrated Silicon Solution, Inc.
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