Radar signal processing on graphics processors (Nvidia/CUDA)

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1 Radar signal processing on graphics processors (Nvidia/CUDA) Jimmy Pettersson & Ian Wainwright Full master thesis presentation will be held in january

2 CUDA is a framework to access the GPU for non-graphics computing, known as GPGPU computing

3 Outline Why GPGPU? CUDA Hardware CUDA Programming Results OpenCL Final thoughts Questions!

4 Why GPGPU? Theoretical peak performance in GFLOPS

5 Why GPGPU? Theoretical peak performance in GFLOPS GFLOPS

6 Why GPGPU? Theoretical GFLOPS Theoretical Bandwidth GB/s Watt Quadro FX GeForce GTS GeForce GTS AMD/ATI Intel Core i Intel Core i7-820 QM GFLOPS/Watt

7 Why GPGPU? Theoretical GFLOPS Theoretical Bandwidth GB/s GFLOPS / W Watt Quadro FX GeForce GTS GeForce GTS AMD/ATI Intel Core i Intel Core i7-820 QM GFLOPS/Watt

8 CUDA Hardware environment

9 CUDA Hardware environment

10 CUDA Hardware environment On-chip Off-chip

11 CUDA Hardware environment

12 CUDA Hardware environment 24 * 8 * 1.2GHz * 2 = 460 GFLOPS

13 CUDA Hardware environment 24 * 8 * 1.2GHz * 2 = 460 GFLOPS 24 * (16 KB + 16K * 4 B) = 1920 KB instant on-chip memory

14 CUDA Hardware environment

15 CUDA Hardware environment

16 CUDA Hardware environment

17 CUDA programming Programming is done in C with some C++ extensions like templates.

18 CUDA programming Programming is done in C with some C++ extensions like templates. Yields high level programming while still close to the hardware.

19 CUDA programming Code execution: CPU / GPU

20 CUDA programming Threads & Warps

21 CUDA programming Threads & Warps A warp consists of 32 consecutive threads

22 CUDA programming Warp execution ~ SIMD similarities

23 CUDA programming Warps are then grouped into work groups (blocks) for execution:

24 CUDA programming Work group (block) scheduling:

25 CUDA programming Communication within a work group

26 CUDA programming Communication within a work group Managed through fast on-chip shared memory.

27 CUDA programming Communication within a work group Managed through fast on-chip shared memory. Threads can be synchronized in order to avoid read/write dependencies.

28 CUDA programming A CUDA programming example:

29 CUDA programming A CUDA programming example: Space-Time Adaptive Processing (STAP) with covariance matrix estimation.

30 CUDA programming STAP- covariance matrix estimation A sliding volume in a 3D data set.

31 CUDA programming STAP- covariance matrix estimation A sliding volume in a 3D data set. For each doppler we iterate over the range, read more data, and construct a new covariance matrix from the beams.

32 CUDA programming STAP- covariance matrix estimation A sliding volume in a 3D data set. For each doppler we iterate over the range, read more data, and construct a new covariance matrix from the beams.

33 CUDA programming STAP- covariance matrix estimation A sliding volume in a 3D data set. For each doppler we iterate over the range, read more data, and construct a new covariance matrix from the beams. The covariance matrix is given by x*transpose(x)

34 CUDA programming STAP- covariance matrix estimation A sliding volume in a 3D data set. These are summed in each step. A(i,j,r) += A(i,j, r-1) for every 'i' and 'j'

35 CUDA programming STAP- covariance matrix estimation A sliding volume in a 3D data set. And finally normalized at the end of each range.

36 CUDA programming STAP- covariance matrix estimation Difficult to implement in CUDA architecture?

37 CUDA programming STAP- covariance matrix estimation Difficult to implement in CUDA architecture? Nope! The CUDA architecture can parallelize over each doppler channel quite easily!

38 CUDA programming STAP: Difficult to implement in CUDA architecture? Nope! The CUDA architecture can parallelize over each doppler channel quite easily! We assigned work groups over each doppler channel.

39 CUDA programming STAP- covariance matrix estimation We assign one thread per x- element and let it compute one column each of the covariance matrix.

40 CUDA programming STAP- covariance matrix estimation We assign one thread per x- element and let it compute one column each of the covariance matrix.

41 CUDA programming STAP- covariance matrix estimation We assign one thread per x- element and let it compute one column each of the covariance matrix. All the data is stored in on-chip shared memory.

42 CUDA programming STAP- covariance matrix estimation We assign one thread per x- element and let it compute one column each of the covariance matrix. All the data is stored in on-chip shared memory. This is then iterated all over the range and then finally normalized.

43 CUDA programming STAP- covariance matrix estimation We used 2 different data sets. Doppler Range Beams Range blocks MITRE Extended

44 CUDA programming STAP- covariance matrix estimation We used 2 different data sets. Doppler Range Beams Range blocks MITRE Extended The GPU results were benchmarked against a CPU implementation.

45 CUDA programming STAP- covariance matrix estimation We used 2 different data sets. Doppler Range Beams Range blocks MITRE Extended The GPU results were benchmarked against a CPU implementation. Intel core 2 duo at 3 GHz running on one core.

46 CUDA programming STAP- covariance matrix estimation Results for the first implementation

47 CUDA programming STAP- covariance matrix estimation Optimization: Store the matrices in thread local registers instead. The register file is 4 times larger than the on-chip shared memory.

48 CUDA programming STAP, Results: Comparison, shared memory VS register memory.

49 CUDA programming STAP: Conclusions More data and higher arithmetic intensity benefit the GPU tremendously.

50 CUDA programming STAP: Conclusions More data and higher arithmetic intensity benefit the GPU tremendously. The game is to keep the streaming processors fed with data and never have them idle waiting for more.

51 Results Benchmark GFLOPS Speedup(HPEC) Speedup(MKL)

52 Results Benchmark GFLOPS Speedup(HPEC) Speedup(MKL) TDFIR times

53 Results Benchmark GFLOPS Speedup(HPEC) Speedup(MKL) TDFIR times QR times 9 times

54 Results Benchmark GFLOPS Speedup(HPEC) Speedup(MKL) TDFIR times QR times 9 times CT 16 GB/s 100 times

55 Results Benchmark GFLOPS Speedup(HPEC) Speedup(MKL) TDFIR times QR times 9 times CT 16 GB/s 100 times SVD times 3 times

56 Results Benchmark GFLOPS Speedup(HPEC) Speedup(MKL) TDFIR times QR times 9 times CT 16 GB/s 100 times SVD times 3 times CFAR times

57 Results Benchmark GFLOPS Speedup(HPEC) Speedup(MKL) TDFIR times QR times 9 times CT 16 GB/s 100 times SVD times 3 times CFAR times FFT times

58 Results Benchmark GFLOPS Speedup(HPEC) Speedup(MKL) TDFIR times QR times 9 times CT 16 GB/s 100 times SVD times 3 times CFAR times FFT times Benchmark GFLOPS Speedup(SMW) Speedup(MKL)

59 Results Benchmark GFLOPS Speedup(HPEC) Speedup(MKL) TDFIR times QR times 9 times CT 16 GB/s 100 times SVD times 3 times CFAR times FFT times Benchmark GFLOPS Speedup(SMW) Speedup(MKL) STAP: Covariance matrix times

60 Results Benchmark GFLOPS Speedup(HPEC) Speedup(MKL) TDFIR times QR times 9 times CT 16 GB/s 100 times SVD times 3 times CFAR times FFT times Benchmark GFLOPS Speedup(SMW) Speedup(MKL) STAP: Covariance matrix times SAR: Tilted matrix addition 55 GB/s 80 times

61 Results Benchmark GFLOPS Speedup(HPEC) Speedup(MKL) TDFIR times QR times 9 times CT 16 GB/s 100 times SVD times 3 times CFAR times FFT times Benchmark GFLOPS Speedup(SMW) Speedup(MKL) STAP: Covariance matrix times SAR: Tilted matrix addition 55 GB/s 80 times Cubic interpolation times

62 Results Benchmark GFLOPS Speedup(HPEC) Speedup(MKL) TDFIR times QR times 9 times CT 16 GB/s 100 times SVD times 3 times CFAR times FFT times Benchmark GFLOPS Speedup(SMW) Speedup(MKL) STAP: Covariance matrix times SAR: Tilted matrix addition 55 GB/s 80 times Cubic interpolation times Bicubic interpolation times

63 Results Benchmark GFLOPS Speedup(HPEC) Speedup(MKL) TDFIR times QR times 9 times CT 16 GB/s 100 times SVD times 3 times CFAR times FFT times Benchmark GFLOPS Speedup(SMW) Speedup(MKL) STAP: Covariance matrix times SAR: Tilted matrix addition 55 GB/s 80 times Cubic interpolation times Bicubic interpolation times Picture correlation times

64 Results Benchmark GFLOPS Speedup(HPEC) Speedup(MKL) TDFIR times QR times 9 times CT 16 GB/s 100 times SVD times 3 times CFAR times FFT times Benchmark GFLOPS Speedup(SMW) Speedup(MKL) STAP: Covariance matrix times SAR: Tilted matrix addition 55 GB/s 80 times Cubic interpolation times Bicubic interpolation times Picture correlation times These are reasonably big data sets

65 OpenCL New standardized, open, cross platform, heterogeneous API. Aim: Code once, compile on various hardware, such as CPUs, GPUs, Cell Broadband Engine, DSP... Problems: Only AMD / Nvidia GPUs and Cell have supported HW. Still immature CUDA and OpenCL are very similar.

66 What to remember! When to use the GPU: Large data sets and/or have a high arithmetic intensity.

67 What to remember! When to use the GPU: Large data sets and/or have a high arithmetic intensity. When not to use the GPU: The host to device data transfer is a significant part of the computation. Entirely serial computations.

68 What to remember! When to use the GPU: Large data sets and/or have a high arithmetic intensity. When not to use the GPU: The host to device data transfer is a significant part of the computation. Entirely serial computations. Easy: Basically C with good hardware knowledge.

69 What to remember! When to use the GPU: Large data sets and/or have a high arithmetic intensity. When not to use the GPU: The host to device data transfer is a significant part of the computation. Entirely serial computations. Easy: Basically C with good hardware knowledge. Future: New architecture called Fermi in Q brings lots of nice features, such as caches, C++ support, IEEE compliant, and more!

70 Questions! Vi sitter mitt emot projekt-tavlorna vid A-trappan!

71 What typical CUDA code might look like

72 What typical CUDA code might look like // vector addition A[threadIdx.x] = B[threadIdx.x]+C[threadIdx.x];

73 What typical CUDA code might look like // vector addition A[threadIdx.x] = B[threadIdx.x]+C[threadIdx.x]; // A = B.*C - matrix elementwise multiplication int i = threadidx.y + blockidx.y*block_dim_y; int j = threadidx.x + blockidx.x*block_dim_x; A[i][j] = B[i][j]*C[i][j];

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