Cadence PCB Design Solutions Industry leading PCB design solutions
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1 Cadence PCB Design Solutions Industry leading PCB design solutions Unlike other PCB design solutions, Cadence OrCAD and Allegro PCB design suites can grow with future design needs and technology challenges. They provide a feature-rich, fully scalable solution that can be expanded and upgraded as the level of design sophistication grows. Feature Standard Professional Schematic Capture & Data Management OrCAD Capture Schematic Entry OrCAD Capture Market place for Apps, Models, Symbols and more Graphical, flat and hierarchical page editor and Picture block hierarchy Net Groups - Complex bus definition Intelligent PDF creation AutoWire 44,000 Schematic symbols 3D Footprint Viewer Color Components / nets Tcl TK scripting support Online design rule check including custom DRC capability and Waive DRC Forward and back-annotation of properties / pin-and-gate swaps Schematic Part and Library editor Automated data extraction and symbol creation from PDF datasheet OrCAD Library Builder OrCAD Library Builder OrCAD Library Builder Cross-probing and cross-placing FPGA design-in / pin import & export Multiple PCB netlist interfaces SI Topology creation Property editor for pins, components, nets
2 Standard Professional Digi-Key (PartLink App) Component Parametric data directly from web Automated Graphical Design Compare Export ISCF (Intel schematic connectivity format) Import / Export XML Altium, PADS, Eagle CAD Importer (schematic and PCB) Allegro Design Authoring Schematic Entry Component Information System CIS option CIS option New part introduction capability CIS option CIS option Interface to relational database and management systems Database query for part selection and parametric properties CIS option CIS option CIS option CIS option Manage multiple BOM variants CIS option CIS option CIS Database Management Interface (access control and more) Part search and download Digi-Key, FARNELL, FUTURE, MOUSER, ARROW, RS Assign user roles, page responsibilities, and track progress Lock projects / pages for editing or view only Manage and track schematic page and project revisions Symbol level library sharing and revision handling Analog Simulation OrCAD CIP OrCAD CIP CIP OrCAD CIP OrCAD CIP CIP Allegro Team Design Option Allegro Team Design Option Allegro Team Design Option Allegro Team Design Option 33,000 Part Pspice Model Starter Library PSpice AD PSpice AD PSpice AD Multi-core engine support PSpice AD PSpice AD PSpice AD DC sweep, AC sweep, & transient analysis PSpice AD PSpice AD PSpice AD Auto-Convergence Engine PSpice AD PSpice AD PSpice AD Analog behavioral modelling PSpice AD PSpice AD PSpice AD Stimulus editor PSpice AD PSpice AD PSpice AD Model Editor for device characterization PSpice AD PSpice AD PSpice AD Magnetics Part Editor PSpice AD PSpice AD PSpice AD Interactive waveform viewer & analyzer PSpice AD PSpice AD PSpice AD IBIS / DML model support PSpice AD PSpice AD PSpice AD PSpice Modeling apps including: Sources, Transformers, TVS, VCO and Switches Open API for custom analysis and postprocessing Sensitivity: Identifies critical circuit components PSpice AD PSpice AD PSpice AD PSpice AD PSpice AD PSpice AD Advanced Analysis Advanced Analysis Advanced Analysis
3 Standard Professional Optimizer: Optimizes key circuit components Advanced Analysis Advanced Analysis Advanced Analysis Monte Carlo: Analyzes statistical circuit behavior and yield Advanced Analysis Advanced Analysis Advanced Analysis Smoke: Detects component stress Advanced Analysis Advanced Analysis Advanced Analysis Parametric Plotter: Examine solution through nested sweeps SystemC / C++, Verilog A, Verilog AMS Modeling and Analysis Signal Integrity Advanced Analysis Advanced Analysis Advanced Analysis Advanced Analysis Advanced Analysis Advanced Analysis Pre Route Signal Integrity Analysis Graphical topology definition and exploration Interactive waveform viewer Macro modelling support (DML) IBIS 5.0 support IBIS ICM model support Spectre-to-DML HSPICE-to-IBIS Lossy transmission lines Coupled (3 net) simulation Differential pair exploration and simulation Post Route Signal Integrity Analysis Net extraction from PCB Editor Differential Pair Extraction from PCB Editor Coupled (>3 net) exploration and simulation Full SI Analysis and Verification SI SI SI Electrical Rule Check: Impedance discontinuities Electrical Rule Check: Coupling areas with other signals Electrical Rule Check: Phase differences of diff pairs OrCAD Sigrity ERC OrCAD Sigrity ERC OrCAD Sigrity ERC OrCAD Sigrity ERC OrCAD Sigrity ERC OrCAD Sigrity ERC OrCAD Sigrity ERC OrCAD Sigrity ERC OrCAD Sigrity ERC Electrical Rule Check: Number of vias OrCAD Sigrity ERC OrCAD Sigrity ERC OrCAD Sigrity ERC PCB Layout and Interactive Routing Unlimited Database Netlist / Crossplace / Crossprobe Padstack & Footprint Editor Cross Section Editor 3D Visualization / Flipboard Customizable, Automated Drill Legend / NC Output Via-in-Pad Rules, Blind / Buried Via Support Autoplacement / Quickplace / Floorplanner Dynamic Shapes with Real-Time Plowing & Healing
4 Standard Professional 2D Drafting and Dimensioning Multiple UNDO / REDO Gerber 274X, 274D Artwork Output Generation IPC-2581 Export HTML-based Reports DFM DRCs (exposed copper, slivers, pastemask, etc.) Automatic Silkscreen Generation Split Plane Support SKILL (programming language) Runtime, Macro, & Scripting Support Variant Assembly Drawing / Bill-of Material Creation PCB Imports: PADS, P-CAD, Altium, Eagle (Schematic and PCB) Mechanical CAD Interface: IDF 3.0, IDX, DXF, STEP Native 3D Viewer (STEP & Simple Extrusions) MCAD/ECAD Incremental design data exchange (EDMD) Snap Functions (precise drafting of lines /shapes) SameNet Clearance DRC Support Stacked Via Edit, Move Single-sided Design Jumper Support Physical and Spacing rules Class-to-Class Net Spacing rules SameNet Rules Properties & DRC Floorplanning, Autoplace Place by room / by schematic page Dynamic Shapes Scribble Route Snake Routing (Hex Pitch BGA) Multi-line routing Fan-out generators Dynamic pad suppression / unused pad removal Soldermask, Solderpaste checks Component Height Checks Multi-Core Support for Shapes & DRCs DFT: Manual Test prep (test point generation & reuse)
5 Standard Professional Pad Entry / Exit Rules Multi-Cross Section Support (Flex) Zone Placement (Flex) Curve Routing (Flex) Blind / Buried Microvia Stacking, Split, & Merge support Dynamic Cross Hatch and Solid Planes (Flex) Differential Pair Rules Differential pair static phase control rules IPC 7351 Complaint Footprint Creation OrCAD Library Builder OrCAD Library Builder OrCAD Library Builder Automated 3D STEP Model Creation and Alignment OrCAD Library Builder OrCAD Library Builder OrCAD Library Builder Hug Contour Routing (Flex) Segment over void detection Layer set rules Extended Net creation Matched group rules Dynamic shape based filleting, line fattening and trace filleting Dynamic Zone Placement (Flex) Inter-Layer DRC Checks (Flex) Zone Table Chart (Flex) DFT: Auto Test Prep Interactive Delay Tuning Shape based curve fillet support, tapered traces Placement Replication Design For Fabrication (DFF) Checks Region based rules (Rigid-Flex; BGA regions) Constraint Regions Min/Max length constraints Constraint adherence feedback (red, green, yellow) Dynamic heads-up display for critical rules Single-ended Impedance Constraints Group route via pattern Propagation delay rules (Min/Max, Relative)
6 Standard Professional T-Point rules (pin to T-Point) T-Point rules (pin to T-Point) Via array / Shielding Dynamic Differential Pair Phase Control rules Dynamic DFA rules based interactive placement Backdrilling Enhanced Curved Routing Electrical Constraint rule set (ECSets) / Topology Apply Schematic based module reuse Extended (X) net rules Estimated Crosstalk rules Max via count rules Spread lines between anti-pads Offset routing Pin Pair rules Mentor Boardstation Import Dynamic Fillet Support High-Speed rules based autorouting Differential Pair Autorouting, Automatic net shielding Design planning - Create hierarchical Bundles Design planning - Create, Edit Flows Design planning - Assign Flows to Layers Design planning Assign Layers Package Pin Delay (for die-2-die delay) rules Z-Axis delay feedback Advanced Constraints (formulas, relational) Electrical rules (Reflection, Timing, Crosstalk) Unused micro-via removal Design Planning - Plan Spatial Feasibility analysis & feedback Design Planning - Generate Topological Plan Design Planning - Auto-interactive Breakout Technology (AiBT) Design Planning - Convert Topological plan to traces (CLINES) Design Planning - Auto-interactive adjust spacing Backdrilling - Library Driven PCB High Speed Option
7 Standard Professional Auto Interactive Delay Tune (AiDT) Auto Interactive Phase Tune (AiPT) TimingVision advanced timing closure engine Fiber Weave Off-Angle Routing Differential Pair Return Path Vias Tabbed Routing (Intel) High Speed Differential Pair Via Structures (Sigrity Integration) Fabric Weave Routing Single Net and Diff Pair Return Path Via Templates ( HDI Micro-via (spacing, stacking) rules HDI micro-via inset (via-in-pad) rules HDI micro-via stack editing Single Click multiple micro-via instantiation Manufacturing rule support for embedding components Embedded Packaged Components Support for Cavities on inner layers Concurrent Team Design - Layer by Layer partitioning PCB Team Design Option (PA3410) Concurrent Team Design - Functional block partitioning PCB Team Design Option (PA3410) Concurrent Team Design - Team design dashboard PCB Team Design Option (PA3410) Concurrent Team Design - Soft nets PCB Team Design Option (PA3410) Swap pins on a FPGA (based on FPGA rules) in PCB Editor FPGA System Planner (PA8250) Re-optimize pins on a FPGA (using FPGA rules) FPGA System Planner (PA8250) Parameterized RF etch elements Asymmetrical Clearances RF Etch elements editing
8 Standard Professional Bidirectional interface with Agilent ADS Import Agilent ADS schematics into DE HDL Layout-driven RF design creation Flexible Shape Editor Via Array placement on traces, shapes Create intelligent PDF output from Board Design Autorouting 6 Signal Layers at a time (no board layer limit or pin limit) Design Publisher Option (PA1220) Shape-based or Grid routing SMD Fanout Trace Width by Net and Net Classes 45-degree / Memory Pattern Routing Interactive Routing with Shoving and Plowing Interactive Floorplanning Online Design Rule Checking Flip, Rotate, Align, Push, and Move Components Placement Density Analysis High Speed rules based autorouting Min/Max, matched length rules based autorouting Pin-pair rules, Area rules based autorouting Crosstalk controls, parallelism rules based autorouting Differential Pair Autorouting, Automatic net shielding High-speed rules-based autorouting 256 signal layer limit DFM rules-based autorouting Automatic trace spreading ATP generation Layer-specific rules-based autorouting OrCAD Router Auto / Interactive Option EMA Design Automation 225 Tech Park Drive, Rochester, NY USA Tel : (USA) Fax: (USA) info@ema-eda.com Support: support@ema-eda.com Cadence Design Systems enables global electronic design innovation and plays an essential role in the creation of today s electronics. Customers use Cadence software, hardware, IP, and expertise to design and verify today s mobile, cloud, and connectivity applications Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Allegro, PSpice, OrCAD, and SPECCTRA are registered trademarks of Cadence Design Systems, Inc., All rights reserved. EMA Design Automation, the EMA logo, and AutoClustering are trademarks of EMA Design Automation Inc.
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