A Single-Chip Quad-Band GSM/GPRS Transceiver in 0.18µm Standard CMOS. Berkäna Wireless Inc. Campbell, California

Transcription

1 A Single-Chip Quad-Band GSM/GPRS Transceiver in 0.18µm Standard CMOS Berkäna Wireless Inc. Campbell, California

2 Desired Features of Commercial Radios Low Cost Small Form Factor Long Range CMOS Front-end Transceiver PFD Digital Baseband (BB)

3 Presentation Outline GSM/GPRS Implementation Challenges Transceiver Architectural Tradeoffs CMOS Quad-Band GSM/GPRS Transceiver Test Results Conclusions

4 Key Receiver Specifications GSM 900 Blocking Profile AM Blockers -23dBm -33dBm -43dBm -99dBm 76dB f C - 3MHz f C - 1.6MHz f C - 600kHz f C Desired Signal freq Range of the Mobile Near-Far Problem Presence of Nearby Users => Sensitivity < -102dBm => Large Dynamic Range => IIP3 > -17dBm

5 Key Transmitter Specifications TX Noise in RX Band +33dBm Modulation Mask Requirement < -162dBc/Hz - 60dBc Transmit Band 20MHz Spacing Receive Band freq f C 400 khz freq Receive Band Noise at 20MHz offset, PN < -162dBc/Hz Modulation Mask at 400kHz offset requires high linearity and low phase noise ϕ RMS Modulation Accuracy of: < 5 o

6 RX Direct Conversion RF Filter Mixer ADC I BB Q BB I LO Q LO Properties of Direct Conversion Low frequency signal facilitating programmable filters Problematic 1/f, DC offset and IP2 interference

7 Low IF Receiver RF Filter Mixer ADC I BB Q BB I LO Q LO Properties of Low-IF Receivers Less susceptible to low frequency interference Image rejection must be addressed Leverage narrowband signal to facilitate integration

8 Direct Conversion Transmitters I BB Mixer / Modulator RF Filter Power Amp RF Filter Q BB I LO Q LO Properties of Direct Conversion Transmitters Single conversion eliminates IF filter Requires Pre-PA filter for harmonic rejection Wideband modulator noise demands filtering

9 TX Offset Phase-Locked Loop I BB Modulator Loop Filter VCO Power Amp Q BB PFD/CP I L O 1 Q LO1 LO2 PLL frequency translates phase modulated signal PLL transfer function filters mixer spurs and noise More design complexity compared to Direct Conversion Leverage narrowband signal to enable integration

10 Presentation Outline GSM/GPRS Implementation Challenges Transceiver Architectural Tradeoffs CMOS Quad-Band GSM/GPRS Transceiver Test Results Conclusion

11 Quad-Band GSM/GPRS Transceiver PAM Lowband Pre-PA Amp 2 VCO Loop Filter HR Filter Modulator TX IN BB I 2 4 T/R Switch RF Filters Highband Pre-PA Amp M I/Q EGSM LNA Mixers PFD VCO Paper 17.8 Loop Filter I LO PFD R Q LO TX IN BB Q TCXO GSM LNA N/(N+1) DCS LNA PCS LNA I/Q Mixers I Q Complex IF Filter I Q PGA Σ I Q IF LO Low-IF Discrete-Time Processing RX OUT BB I RX OUT BB Q

12 PLL Phase Noise vs. Settling Time N/N+1 Ref. Osc. PFD CP R 1 V C C 1 VCO TX & RX LO Input C 2 Loop Filter Phase 3MHz (dbc/hz) Phase 3MHz MHz t_settle_prechg_off -146 dbc/hz C E E E E E+00 time (sec) PLL Settling Time ( µs)

13 Typical PLL Settling Characteristics V C Range of V C (Post VCO Calibration) ~V dd / 2 T Slew = C 2*V dd /2 I CP time VCO calibration minimizes control voltage range Small charge pump current

14 Principle of Fast Charging PLL V C Range of V C (Post VCO Calibration) ~V dd / 2 T Slew = C 2*V dd /2 I Boost time VCO calibration minimizes control voltage range Small charge pump current

15 PLL Fast-Charge Amplifier V dd /2 V i pc CP V o = V c pc V C R 1 C 1 C 2 VCO Class AB Amplifier pc pc V i I Boost 15mA M Z V o I Boost pc pc C 2

16 Receiver RF and IF Mixer I Channel IF Output LNA Q Channel IF Output Filter PGA 1 st Stage Filter PGA 2 nd Stage Filter PGA 3 rd Stage Filter PGA 4 th Stage Filter PGA 5 th Stage Fully differential signal path Complex Butterworth filter response Receive gain is 100dB in 2dB steps

17 High-Band RF Front End Band Sharing LNA Loads Folded Mixer LOQ Q MIXER OUTPUT IND+ VB1 IND- INP+ VB2 LOI- INP- VB3 LOI+ I MIXER OUTPUT DCS Band PCS Band

18 Receive IF Filter and PGA Stage I Channel Input R 1 C 2 R 2 Next Filter Stage I Channel Output R 1 R 2 C 2 RC R C R C DC Offset Cancellation Algorithm R C Q Channel Input R 1 C 2 R 2 Next Filter Stage Q Channel Output R 1 R 2 C 2 DC Offset Cancellation Algorithm

19 Transmit Output Driver TX OPLL On-chip VCO Level Shifter High Band AmplifierR esd Chip Pad C ac_couple Feedback Path of OPLL 2 Low Band Amplifier R esd Chip Pad C ac_couple Rload Rload V dd Rail-to-Rail Signal Path Mp C ac_couple Ko Push-Pull Driver Mn R LOAD P O = i op2 *R LOAD /2 Minimal Area

20 Principle of the Ko Push-Pull Amp High Input State V i V i V dd Mp i odn VO C ac_couple V o t R LOAD(Effective) t Low Input State i odn V dd t V i i odp V O C ac_couple Z o Mn R LOAD(Effective) r onn r onp ~Z out t

21 Presentation Outline GSM Implementation Challenges Transceiver Architectural Tradeoffs CMOS Quad-Band GSM/GPRS Transceiver Test Results Conclusion

22 Chip Radio Evaluation Board SAW Filters & Matching VC-TCXO Antenna Switch Module Quad-Band Transceiver Power Amp Module

23 PLL Settling Time w/ Fast Charge Amp. V C PLL settling time of 150µs w/o Precharge Amp time

24 Receiver Sensitivity (EGSM900) GPP GSM Spec (-102dBm) Measured EGSM Sensitivity EGSM Channel (ARFCN) Sensitivity (dbm)

25 In-Band Blocker Performance (PCS) db dBm -38 Margin Relative to to 3GPP 3GPP Measured Blocker Level Level GPP Spec for for Blocker Level Input at at Antenna Blocker Offset Frequency (MHz)

26 TX Modulation Mask & Phase Error EGSM900 Modulation Mask EGSM900 RMS Phase Error

27 TX Phase Error at PA Output (PCS) Peak Phase Error 3GPP Required Peak Phase Error RMS Phase Error

28 Receiver Performance Summary Receiver Measurements Noise figure (db) Input IP3 (dbm) Input IP2 (dbm) RX gain (db) Sensitivity at antenna (dbm) RX current (ma) GSM850 /EGSM DCS1800 /PCS

29 Transmitter Performance Summary Transmitter Measurements RMS Phase Error (degrees) Output Modulation Spectrum at 400kHz Offset (dbc) Noise at 20MHz Offset (dbc/hz) Worst Case PLL settling time (µs) Output Power (dbm) Carrier Suppression (dbc) Sideband Suppression (dbc) Current (ma) GSM850 /EGSM DCS1800 /PCS

30 Conclusions Single-Chip CMOS Transceiver Demonstrates Cellular Performance Low Power/Noise Inductorless PA driver Fast Settling PLL Supports GPRS Class 12 Operation State of the Art RX Sensitivity Performance in Standard CMOS