A low offset chopper amplifier with three-stage nested Miller configuration

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1 . RESEARCH PAPER. SCIENCE CHINA Information Sciences June 014, Vol : :7 doi: /s A low offset chopper amplifier with three-stage nested Miller configuration HUANG ZhuoLei 1, WANG WeiBing 1,, JIANG Fan 1 & CHEN DaPeng 1 1 Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 10009, China; Smart Integrated Sensor Engineering Center, Jiangsu Research and Development Center for Internet of Things, Wuxi 14135, China Received January 8, 013; accepted March 7, 013 Abstract A low offset, low noise chopper amplifier for sensor system application is presented. Low 1/f noise is achieved by employing chopper technique, and low offset is achieved by employing residual offset suppression circuit. The open-loop gain is extended using three-stage nested Miller configuration. The chip was implemented in 0.5 µm P3M CMOS process. The amplifier is featured by an open-loop gain of 135 db and a GBW of 3 MHz. The measured offset voltage is 3 µv, and the equivalent input noise power spectrum density at 1 Hz is 96 nv/ Hz. Keywords chopper amplifier, nested Miller configuration, low offset, residual offset suppression, noise power spectrum density Citation Huang Z L, Wang W B, Jiang F, et al. A low offset chopper amplifier with three-stage nested Miller configuration. Sci China Inf Sci, 014, 57: 06404(7), doi: /s Introduction The trend of the integrated circuit is SOC (system on chip), and CMOS is the best process to realize SOC. However, CMOS process has some disadvantages compared to BJT, especially in precise analog circuits. The most common disadvantages faced by CMOS process in precise analog circuits are offset and 1/f noise. The typical corner frequency of 1/f noise is usually larger than 100 khz, and the offset voltage is about 5 mv in common CMOS process. As the emergence of the internet of things, SOC is required to include the sensors to form the smart sensor system. Since the output signal of the sensor is low frequency and low amplitude, the offset and 1/f noise are main challenges for the smart sensor system design [1 3]. Conventional CMOS amplifiers are known for their high 1/f noise and offset, and there are three techniques to reduce 1/f noise and offset: trimming, auto-zeroing and chopper []. Trimming is used not only in CMOS but also in BJT process to reduce offset [4]. The main disadvantage of the trimming technique for CMOS process is that it cannot reduce 1/f noise. Besides, trimming is too expensive compared to auto-zeroing and chopper. Auto-zeroing is a sampling technique and is widely used in Corresponding author ( wangweibing@ime.ac.cn) c Science China Press and Springer-Verlag Berlin Heidelberg 014 info.scichina.com link.springer.com

2 Huang Z L, et al. Sci China Inf Sci June 014 Vol : R1 CH1 CH V in G1 V c R C C4 Figure 1 Residual offset model. imaging circuit as CDS (correlated double samples). In the auto-zero phase the offset and the 1/f noise are sampled, and in the amplification phase they are subtracted from the input signal. Although the principle of the auto-zeroing is simple and this technique is effective in reducing offset and 1/f noise in CMOS amplifier, auto-zeroing circuits suffer from white noise aliasing. It means that the thermal noise of the auto-zeroing circuit increases dramatically due to undersampling of broad-band noise. Chopper is a modulation technique which was first developed by Goldberg in 1948 [5]. The offset and 1/f noise are modulated to high frequency and eliminated later by analog or digital filter. Then the signal is demodulated to baseband which does not contain offset and 1/f noise because of former modulation and filter. Since the chopper technique does not suffer from white noise aliasing and can work in continuous time circuit, it is suitable for sensor readout circuits. Nowadays chopper technique is widely used in the readout circuits of sensors such as infrared detector, pressure sensor and inertial sensors (accelerometer, gyroscope) [1 3,6,7]. Residual offset Although the traditional chopper amplifier can reduce offset, it introduces residual offset because of charge injection. The mismatch of charge injection from clock path to signal path cause residual offset [8]. Figure 1 shows how the residual offset is generated. CH1 and CH are chopper switches, and, C, and C4 are parasitic capacitors of them. G1 is the amplifier. R1 and R are the source resistors. V c is the clock signal. If the parasitic capacitors are identical, there will be no residual offset since the charge injection will affect both signal paths identically. However,, C, and C4 do have certain mismatch when fabrication and residual offset are produced. We will consider the mismatch between and C first. If there is a slight difference between and C, the differential charge will be injected and residual offset is formed [9,10]. This can be expressed by Q inj = (C 1 C )V c. (1) This differential charge will affect the signal paths two times each clock period, and the current caused by differential charge will run through R1 and R. So we can calculate the residual offset voltage caused by the mismatch between and C as V res1 = (R 1 +R )(C 1 C )V c f. () f is the chopper frequency. Eq. () means that the residual offset voltage will be large if the chopper frequency is too high. However the residual offset will also increase if the chopper frequency is too small, as will be analyzed in Section 3. Besides V res1, there is another residual offset V res caused by mismatch between and C4. The residual offset caused by mismatch between and C4 can be expressed by V os = R(C 3 C 4 )V c f. (3) R is the output resistor of amplifier G1. And V os can be equivalent to the input of amplifier G1, which can be expressed by V res = V os A = R(C 3 C 4 )V c f RG m1 = (C 3 C 4 )V c f RG m1. (4)

3 Huang Z L, et al. Sci China Inf Sci June 014 Vol :3 C R1 CH1 R3 CH V in G1 G G3 R R4 V c Figure Principle of chopper amplifier with three-stage nested Miller configuration. V 1 V o1 R3 V X Rid + V A 1 V 1 G4 V V o R4 V Y + V A V 1 1 Figure 3 Simplified chopper amplifier schematic. A is the gain of amplifier G1, and G m1 is the transconductance of the amplifier G1. The total residual offset voltage can be calculated by V res = V res1 +V res. (5) 3 Circuit implementation 3.1 Block diagram We used a circuit to reduce the residual offset voltage. Figure is the principle of chopper amplifier with three-stage nested Miller configuration. G1 is the first stage, G is the second stage and G3 is the third stage. R3 and R4 are the output resistors of the first stage, and R3 equals R4. and C are Miller compensation capacitors. is used to ensure the symmetry of G. G, G3 and C constitute a two-stage Miller compensation operational amplifier. That operational amplifier is used to form an integrator with,, R3 and R4. That integrator is used to filter out the residual offset as a low-pass filter. Since the integrator is an active filter, it does not suffer from the nonlinearity problem. Besides, its circuit is simpler than that of Gm-C filter. The circuit in Figure can be simplified, and the simplified circuit is shown in Figure 3. The first stage is replaced by its Thevenin equivalent circuit. V in = V 1 V. A 1 is the gain of first stage. Rid is the input resistance of the first stage. G4 is the two-stage Miller compensation operational amplifier, which is made up of G, G3 and C. R 3 = R 4, C 1 = C 3. V o1 and V o can be expressed as V 1 V V o1 = A 1, (6) V V 1 V o = A 1. (7)

4 Huang Z L, et al. Sci China Inf Sci June 014 Vol :4 Since the current through and the current through R3 are the same, we have V X 1 C 1S = V X V o1 R 3. (8) Since the current through and the current through R4 are the same, we have 0 V Y 1 C 3S = V Y V o R 4. (9) From (8) and (9), we have V X V Y can be expressed as A is the gain of G4. We can rewrite (10) as From (6), (7) and (1), we have R 3 C 1 S +(V o1 V o ) = (V X V Y )(1 R 3 C 1 S). (10) V X V Y = A 0. (11) R 3 C 1 S = (V o1 V o ). (1) V in = A 1 R 3 C 1 S. (13) Eqs. (), (4) and (5) show that residual offset will increase with increasing chopper frequency. However the chopper frequency cannot be too low according to (13), or the offset cannot be filtered out by the integrator. There will be an optimal frequency for the chopper amplifier to get the lowest offset. 3. The first stage Figure 4 is the first stage schematic. Transistors M1 M11 form a fully differential cascode amplifier. Transistors M1 M15, resistors R1 and R, and the error amplifier form the common mode feedback. In this circuit, the output of the error amplifier is connected to gates of M7 and M8, instead of M9 and M10. That can reduce the output noise. We assume that the noise of the error amplifier is V n, and neglect other noise sources. If the output of the error amplifier is connected to gates of M7 and M8, the output noise of the first stage is 1 g m7g m5 r DS5 r DS3 1+g m7 r DS9 V n, (14) where g m5 and g m7 arethe transconductanceof M5 and M7, r DS3, r DS5 and r DS9 arethe output resistance of M3, M5, and M9. Eq. (14) can be simplified to 1 g m5 r DS5 V n. (15) If the output of the error amplifier is connected to gates of M9 and M10, the output noise of the first stage is g m9 [(g m7 r DS7 r DS9 )//(g m5 r DS5 r DS3 )]V n, (16) where g m5, g m7 and g m9 are the transconductance of M5, M7 and M9, r DS3, r DS5, r DS7 and r DS9 are the output resistance of M3, M5, M7 and M9. Eq. (16) can be simplified to 1 g m9g m5 r DS5 r DS3 V n. (17) By (15) and (17), is much larger than 1. The output resistors of the first stage must be large enough to ensure the gain. Hence the cascode circuit was used to increase the output resistance of the first stage. However the common mode feedback requires a low output resistance to make a sufficient common mode gain. The source followers M14 and

5 Huang Z L, et al. Sci China Inf Sci June 014 Vol :5 V b1 M11 M3 M1 M13 M4 IN+ M1 M IN V b OUT M5 M14 R1 R M6 M15 V b OUT+ M7 V cm Error amplifier M8 V b IN M1 M M3 IN+ M6 C M7 V b3 M9 M10 M4 M5 Figure 4 The first stage schematic. Figure 5 The second and third stages schematic. G3 60 G CH G1 CH1 C Magnitude (db) Phase ( ) Frequency (Hz) Figure 6 The chip photo. Figure 7 Phase and magnitude frequency response of the amplifier. M15 were used to reduce the common mode output resistance. Therefor the transconductance of the first stage is determined by the transconductance of the transistor M1. And the output resistor of the first stage R3 can be expressed by R3 g m7 (r DS1 //r DS9 )r DS7, (18) where r DS1 is the output resistance of M1, r DS7 is the output resistance of M7, and g m7 is the transconductance of M The second stage and the third stage Figure 5 is the second and third stages schematic. Transistors M1 to M5 form the second stage. Transistors M6 and M7 form the third stage. Capacitors are compensation capacitors. The second stage is used to transfer the fully differential signal to single end signal, which is realized by a simple differential pair circuit. The third stage is a single transistor amplification circuit, which is used as an output buffer. 4 Experimental results The chopper amplifier with three-stage nested Miller configuration is fabricated with CSMC 0.5 µm DPTM process. Figure 6 is the chip photo with a chip s core area of 175 µm 70 µm. The power is 1.7 mw at a chopping frequency of 9 khz and supply voltage of 5 V. Figure 7 is the Phase and Magnitude response of the amplifier. The DC gain of the amplifier is 135 db and the GBW

6 Huang Z L, et al. Sci China Inf Sci June 014 Vol :6 V offset (µv) f (khz) Root spectral density (micro-volts/root-herts) Frequency (Hz) Figure 8 Offset voltage at different chopping frequencies. Figure 9 Output noise power spectrum density. Figure 10 Large signal transient response. is 3 MHz. That means the chopper amplifier with three-stage nested Miller configuration can be used in sensor application. The phase margin of the amplifier is 75. The smallest offset voltage of the amplifier is 3 µv at a chopping frequency of 9 khz. Figure 8 is the offset voltage at different frequencies of the amplifier. The offset become smaller as the chopping frequency become larger because of the integrator. Then the offset voltage increases as the chopping frequency increases as indicated by (4). The optimal frequency for the chopper amplifier to get the lowest offset voltage is 9 khz. Figure 9 is the output noise power spectrum density of the amplifier at a chopping frequency of 9 khz, which is measured by Agilent dynamic signal analyzer A. The measured output noise power spectrum density of the amplifier is 9.6 µv/ Hz at 1 Hz, and the closed loop gain of the measured amplifier is set to 40 db, hence the equivalent input noise power spectrum density of the amplifier is 96 nv/ Hz at 1 Hz. Large signal transient behavior of the chopper amplifier with three-stage Miller configuration is shown in Figure 10. Table 1 compares out amplifier to other related configuration amplifiers. In the application of low frequency sensor system, offset voltage and open-loop gain are two key parameters. The offset voltage of the proposed amplifier is low, and the open-loop gain is higher than those of [1,11,1]. The equivalent input noise power spectrum density of the proposed amplifier is lower than that of [6], and it is suitable for the common application of sensor system.

7 Huang Z L, et al. Sci China Inf Sci June 014 Vol :7 Table 1 Main performance of the proposed chopper amplifier and its comparison (ε is the mismatch between chopper frequency and filter center frequency) Open-loop GBW Offset Input Supply Chopping gain (db) (MHz) voltage (µv) noise (nv/ Hz) voltage (V) frequency (khz) Ref. [1] Ref. [6] Ref. [11] ε Ref. [1] This work Conclusion A low offset chopper amplifier with three-stage nested Miller configuration is presented. The offset suppression theory and the circuit detailed design consideration are shown. The chip has been realized in 0.5 µm P3M CMOS process. Experimental results show that the proposed amplifier has low offset voltage and high open-loop gain, because of the three-stage nested Miller configuration. The chopper amplifier in this paper has a simple residual offset suppression circuit, which is suitable for precision application such as sensor readout circuit. Acknowledgements This work was supported by National Science and Technology Major Project of China (Grant No. 011ZX ). References 1 Yin T, Yang H G, Liu K. A low-noise, low-offset chopper amplifier for micro-sensor readout circuit. Chin J Semiconduct, 007, 8: Enz C C, Temes G C. Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization. Proc IEEE, 1996, 84: Chinwuba D E, Johan P V, Xing X Y, et al. A 6.7 nv/ Hz Sub-MHz-1/f-Corner 14 b analog-to-digital interface for rail-to-rail precision voltage sensing. In: Proceedings of International Solid-State Circuits Conference, San Francisco, Laville S, Pontarollo S, Dufaza C, et al. Integrated offset trimming technique. In: Proceedings of the 7th European Solid-State Circuits Conference, Villach, Witte J F, Makinwa K A, Huijsing J H. Dynamic Offset Compensated CMOS Amplifier. Springer, Witte J F, Huijsing J H, Makinwa K A. A current-feedback instrumentation amplifier with 5 µv offset for bidirectional high-side current-sensing. In: Proceedings of International Solid-State Circuits Conference, San Francisco, Hu Y, Sawan M. CMOS front-end amplifier dedicated to monitor very low amplitude signal from implantable sensors. Analog Integr Circuit Signa Process, 00, 33: Enz C C, Vittoz E A, Krummenacher F. A CMOS chopper amplifier. IEEE J Solid-State Circuits, 1987, : Bakker A, Huiijsing J H. High-accuracy CMOS smart temperature sensors. Kluwer, Menolfi C, Huang Q. A chopper modulated instrumentation amplifier with first order low-pass filter and delayed modulation scheme. In: Proceedings of the 5th European Solid-State Circuits Conference, Duisberg, Menolfi C, Huang Q. A low-noise CMOS instrumentation amplifier for thermoelectric infrared detectors. IEEE J Solid-State Circuits, 1997, 3: Wu S T, Lin F, Guo D H, et al. Design of CMOS operating amplifier for eliminating DC offset based on chopper technology. Semiconduct Technol, 003, 8: 60 64

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