Computer Architecture V Practice Mid-Term Exam Questions. 1. Draw the truth table representing the following equations

Transcription

1 Computer Architecture V Practice Mid-Term Exam Questions 1. Draw the truth table representing the following equations a. A B C D a. D = A (B + C) b. C = (A+B) b. A B C Convert each of the following equations into two-level logic formulas in "sum of products" form. Ans. a. E = (A + B) (A+C) b. F = (A + B) (C + D) a. E = A+(B C) b. F = (A C)+(A D)+(B C)+(B D) 3. Draw a single circuit, using OR, AND, and NOT gates, to implement the twolevel logic version of both of the above equations. The circuit should have four inputs (A,B,C,D) and two outputs (E,F).

2 Ans A B C D E F 4. Using AND, OR, and NOT gates, build a 2-input, 4-output decoder. 5. Explain why it is important to use flip-flops rather than latches for registers. In the case where a state element (flip-flop or latch) is connected to combinational logic in the following manner: state element combinational logic

3 it is important that the new value computed by the combinational logic does not change the output of the state element until the falling edge of the clock. Otherwise, the value flowing out of the combinational logic and into the state element, if it were a latch, could end up changing the output of the state element while the clock was still high. If you think about it, this would cause (at least) two different values to flow into the combinational logic in the same clock cycle. 6. Give a formula showing the number of pins on an SRAM chip as a function of its height and width (no, it's not the book). The number of pins required to specify an address is log 2 (height). The number of pins to required to read data from the SRAM is width. Thus, the number of pins required for the address, the read data, and the write data is log 2 (height) +(2 width). Assuming c other pins are needed for write-enable, ground, etc., the formula for the total number of pins is: log 2 (height) +(2 width) + c 7. Explain why a DRAM cell has to be re-written after a read operation. Why does it also have to be refreshed periodically, even if it is not read? Reading from a DRAM cell either discharges the capacitor (if the capacitor held a high charge) or charges the capicitor (if the capacitor held a low charge), thus possibly changing the value represented by the cell. Since capacitors suffer from leakage, the charge dissipates over time. Thus, the cell has to be re-written periodically to retain its value. 8. Suppose a computer has a 24-bit instruction format with the following fields: op: 8 bits ra: 4 bits rb: 4 bits rc: 4 bits rd: 4 bits where the ra, rb, and rc specify the input registers and rd specifies the destination register. a. If there is a single register file, how many registers should there be in that register file? b. How many read-register select lines should the register file have? How many write-register select lines? How many data output lines? a. Since 4 bits are used to specify a register, there should be 16 (i.e. 2 4 )registers. b. Since there are three input registers to the instruction, three read-register select lines are needed, as well as three data output lines. Since there is one destination register, one write-register select line is needed. 9. Suppose the same computer had two forms of an unconditional jump instruction, both also 24 bits long as follows: op: 8 bits address: 16 bits and op: 8bits reg: 4 bits where address is a PC-relative address and reg specifies the register holding the

4 address to jump to (assume registers are 24 bits as well). When can an assembler use the first form of the jump rather than the second form? Be precise in your answer, stating any assumptions you might make. We'll assume that the PC-relative address is in terms of the number of instructions from the current instruction, rather than the number of bytes. Thus, for example, an instruction where the address is given as 108 means to jump to the instruction 108 instructions later than the current one. We'll also assume that half of the legal addresses constitute jumps "back" (i.e. in the negative direction). With this assumption, a 16-bit address gives a total range of possible jumps of 64K (i.e ) instructions - 32K in each direction. Thus, if the programmer writes a jump to a label that is no more than 32K in either direction, the first form of the jump operation could be used. 10. Give the logical formula for the "sum" (i.e. not the "carry") output of a 1-bit adder. sum = (a b c in ) + (a b c in ) + (a b c in ) + (a b c in )

5 11. Draw the logic, using AND, OR, and NOT gates, to compute the sum output of a 1-bit adder. The logic below uses more not gates than necessary, but is drawn so to better show the correspondance with the boolean formula for sum. a b c in sum 12. Suppose a computer designer wanted to implement subtraction directly in an ALU (using borrowing, as done on paper). a. What would be the inputs to a 1-bit "subtractor"? What would be the outputs? Inputs (assuming performing "a - b"): a,b, borrow-in (representing the fact that the previous column in the subtraction had to borrow from column). Outputs: difference, borrow-out b. Implement the logic for one of the outputs of the 1-bit subtractor, it doesn't matter which one. Here are the formulas (where b in is the borrow-in bit): difference = (a b b in ) + (a b b in ) + (a b b in ) + (a b b in ) borrow-out = (a b) + + (a b b in ) + (a b b in ) The logic to implement these is left as an exercise. 13. In class and in the text book, the formulas (involving p,g,c 0, etc.) for a 4-bit carrylookahead adder were given. Write similar formulas for a 4-bit borrow-lookahead subtractor. Note: While this is an interesting question, it's probably too long for a mid-term exam. I might ask a partial version of a question like this, though. The generate term, g, indicates when a column that is being subtracted will definitely need to borrow from the next column, no matter if the previous column borrowed or not. This is the case when a=0 and b=1. Thus, g i = a i b i

6 The propagate term, p, indicates when, if a borrow occurred in the previous column, the current column will require a borrow. This is when a=0 or when b=1. Thus, p i = a i +b i The equations for the borrow-in components are then the same as those for the carryin components for carry-lookahead addition, namely: b 1 = g 0 + (p 0 b 0 ) b 2 = g 1 + (p 1 ( g 0 + (p 0 b 0 ))) b 3 = g 2 + (p 2 ( g 1 + (p 1 ( g 0 + (p 0 b 0 ))))) b 4 = g 3 + (p 3 (g 2 + (p 2 (g 1 + (p 1 ( g 0 + (p 0 b 0 ))))))) 14. For multiplication and division, several of the registers used needed to be shifted. From D flip-flops, build a 4-bit shift register, capable of shifting left or right by one bit. From the outside, the register should look like: data in 4 clock shift left shift right 4 data out write enable You can assume that you are given 1-bit D flip-flops and any other gates you need. When the "shift-left" line is asserted, the bits should shift left. When the "shift-right" line is asserted, the bits should shift right. When the "write enable" line is asserted, the data on the 4-bit "data in" line should be written to the register. When shifting, a 0 should be written into the vacated bit (i.e. this is a logical shift, not an arithmetic shift).

7 Below is one of the bits of the shift register, which should be replicated four times. The things to note are: the output of the flip-flop should be sent to the next lower bit and the next higher bit, as well as to the register output. a multiplexor is used to choose from the data, the line from the next lower bit, and the line from the next higher bit. The multiplexor is controlled by the "shift left" and "shift right" line. If neither is asserted, then the data is sent to the flip flop. If "right" is asserted, then the input from the next higher bit is sent to the flip-flop. If "left is asserted, then the input from the lower bit is sent to the flip-flop. The C input to the flip-flop is asserted only if the clock and either "write", "shift left", or "shift right" is asserted. On the lowest bit, the "from lower bit" line should be deasserted, as should the "from higher bit" on the highest bit. clock write right left data from lower bit right left C D flip-flop Q to lower bit to higher bit from higher bit