30 minutes VHDL design for very fast FIR Filter on low cost FPGA
|
|
|
- Erica Blake
- 7 years ago
- Views:
Transcription
1 30 minutes VHDL design for very fast FIR Filter on low cost FPGA By Edgard GARCIA MVD
2
3 Introduction In this example we will demonstrate the ability of the low cost FPGA family to implement high performance DSP functions even without using dedicated multipliers. Such implementation requires a good understanding of the algorithm It also requires a good knowledge of the FPGA architectures Finally, using the right coding style with the right synthesis tool such as Synplify-Pro/Synplify-Premier and powerful optimization features, very high performance can be achieved.
4 FIR example 60 tap Bandpass 16 bit data 16 bit coefficients 38 bit output Fs = 120 Mhz To be implemented in a low cost FPGA without using dedicated multipliers (3S700A-4 FG400 in this example)
5 FIR example Multiplier/Accumulator Sample in Sample Address Samples D Q 27 CE D Q 27 Coefficient Address Coefficients Using Multiplier Accumulator structure would require working at 10 GHz for a 100-tap, 100 Mhz!!!
6 Full Parallel FIR architecture DIN C0 C1 C2 C3 C4 C5 DOUT Notes : This structure requires N multipliers for a N x Taps FIR Same comment for data registers Summation implemented with an adder tree
7 Adder tree DOUT
8 Using pipeline registers to improve multipliers performance DIN C0 C1 C2 C3 C4 C5 Very easy for the multiplications Pipelining multipliers for free (embedded registers) DOUT
9 Using pipeline registers to improve adder tree performance DOUT A little bit more tedious and expensive for adder tree
10 Resources and performances A 60 tap FIR filter based on this architecture would require the following resources (for 16 bits data and coefficients) 60 x 16 bit registers (for data pipeline) 60 Multipliers (dedicated or not) 59 adders (with registers) Routing delay will adversely affect the performance (due to the nets length in the adder tree) Using symmetry would save 30 multipliers (at the expense of 30 adders) and reduce the size of the adder tree by 50% 60 x 16 bit registers (for data pipeline) = 480 slices 30 x 17 bit pre-adders = 270 slices 30 Multipliers (dedicated or not) > 2000 slices (if slices based) 29 adders (with registers) = 600 slices Total : > slices and a tremendous routing congestion (preventing probably meeting timing constraints)
11 The Transpose FIR structure DIN C5 C4 C3 C2 C1 C DOUT Excellent architecture for medium and high speed filters The adder chain can be easily placed and routed due to the structure of the Xilinx FPGA (arithmetic functions are placed in columns) Multipliers can be pipelined to improve performance The same data being multiplied by all the coefficients, partial results can be used for many multiplications (regardless of symmetry) Very low latency, excellent performance even without using dedicated multipliers
12 Resource estimation 60 Taps, 16 bit data, 16 bit coefficients DIN C5 C4 C3 C2 C1 C DOUT Even considering that the output could need up to 38 bits (typically no more than 34) the adder chain will require 19 slices x 60 = 1140 slices Multipliers can be (and will be) implemented in slices (pipeline registers can be used at no cost) Targeted FPGA family : Spartan3A 4 (lowest speed grade)
13 VHDL source code 60 Taps, 16 bit data, 16 bit coefficients Input register DIN DINR COEF(59) COEF(58) COEF(2) COEF(1) COEF(0) MULT(0) MULT(1) MULT(57) MULT(58) MULT(59) Output register ADD(56) + ADD(57) + ADD(58) + ADD(0) ADD(59) DOUT Coefficients, multiplication results as well as adders will be defined as arrays
14 VHDL source code Entity Just to map input and output registers into IOBs FFs library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_SIGNED.ALL; entity FIR_60_TAPs is Port ( CK : in STD_LOGIC; DIN : in STD_LOGIC_VECTOR (15 downto 0); DOUT : out STD_LOGIC_VECTOR (37 downto 0)); attribute syn_useioff : boolean; attribute syn_useioff of DIN : signal is true; attribute syn_useioff of DOUT : signal is true; end FIR_60_TAPs;
15 VHDL source code Architecture declarations architecture Behavioral of FIR_60_TAPs is signal DINR : std_logic_vector(din'range); type COEFS_TYPE is array(59 downto 0) of std_logic_vector(15 downto 0); constant COEFS : COEFS_TYPE := ( x"ffff",x"ffb3",x"00d6",x"0063",x"fdb1",x"01d9",x"025f",x"fab4", x"0141",x"063b",x"f92d",x"fe5a",x"0825",x"fbe0",x"fccd",x"031e", x"0011",x"0410",x"f766",x"fcc2",x"1730",x"eeb3",x"ea68",x"2dac", x"f57a",x"cd9b",x"3731",x"0dd7",x"b74e",x"2a15",x"2a15",x"b74e", x"0dd7",x"3731",x"cd9b",x"f57a",x"2dac",x"ea68",x"eeb3",x"1730", x"fcc2",x"f766",x"0410",x"0011",x"031e",x"fccd",x"fbe0",x"0825", x"fe5a",x"f92d",x"063b",x"0141",x"fab4",x"025f",x"01d9",x"fdb1", x"0063",x"00d6",x"ffb3",x"ffff"); type MULT_TYPE is array(59 downto 0) of std_logic_vector(31 downto 0); signal MULT : MULT_TYPE; attribute syn_multstyle : string; attribute syn_multstyle of MULT : signal is "logic"; type ADD_TYPE is array(59 downto 0) of std_logic_vector(37 downto 0); signal ADD : ADD_TYPE; constant ZERO : std_logic_vector(37 downto 0) := (others => '0'); Synthesis directive to map the multiplier logic into Slices instead of dedicated multipliers
16 VHDL source code RTL code begin process(ck) begin if CK'event and CK = '1' then DINR <= DIN; for I in 59 downto 0 loop MULT(I) <= DINR * COEFS(59-I); if I = 0 then ADD(I) <= ZERO + MULT(0); else ADD(I) <= MULT(I) + ADD(I-1); end if; end loop; DOUT <= ADD(59); DINR DIN end if; Input register COEF(59) COEF(58) end process; end Behavioral; 0 COEF(2) COEF(1) COEF(0) MULT(0) MULT(1) MULT(57) MULT(58) MULT(59) ADD(58) + ADD(0) ADD(56) ADD(57) Output register ADD(59) DOUT
17 Implementation results Number of Slice Flip Flops: 4,068 out of 11,776 34% Number of 4 input LUTs: 4,450 out of 11,776 37% Number of occupied Slices: 2,660 out of 5,888 45% Number of bonded IOBs: 55 out of % IOB Flip Flops: 54 Constraint Check Worst Case Best Case Timing Slack Achievable Errors NET "CK" PERIOD = ns ns ns 2563 Total REAL time to PAR completion: 1 mins 52 secs Timing errors!!!
18 Timing analysis for a 38 bit adder Timing model for slice based arithmetic functions Tsu = 1.0 ns LUT LUT LUT Total FF to FF delay : Tco = 650 ps Tnet = 2400 ps (assumed) T(first LUT + carry) = 1300 ps Tcarry x 37 = 2960 ps Tsu = 1000 ps Total = 8310 ps LUT Tcarry = 80 ps/bit including routing Tco = 0.65 ns LUT LUT LUT The adder chain must be able to work at 120 Mhz even with a net delay of 2400 ps Tnet =??? T(first LUT + carry) = 1.3 ns (let s assume up to 2.4 ns)
19 Multipliers implementation Multipliers can be implemented on slices by using adders Adders can be pipelined at no FPGA resources cost Manual optimization of the source code would be a time consuming task. Instead, we can use the RETIMING option of Synplify-Pro to do the job, and push the registers where needed to meet performance. Let s modify the source code to add some levels of pipeline on the data bus
20 Adding pipeline registers Input register DIN 3 levels of pipeline (in this example) DINR COEF(59) COEF(58) COEF(2) COEF(1) COEF(0) MULT(0) MULT(1) MULT(57) MULT(58) MULT(59) Output register ADD(58) + ADD(0) ADD(56) ADD(57) ADD(59) DOUT By selecting the RETIMING option in Synplify-Pro, we expect the registers to be pushed inside the multiplier logic in order to improve performance
21 Modifying the VHDL source code Entity library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_SIGNED.ALL; entity FIR_60_TAPs is Generic (N : integer := 3); -- Number of pipe cycles Port ( CK : in STD_LOGIC; DIN : in STD_LOGIC_VECTOR (15 downto 0); DOUT : out STD_LOGIC_VECTOR (37 downto 0)); attribute syn_useioff : boolean; attribute syn_useioff of DIN : signal is true; attribute syn_useioff of DOUT : signal is true; end FIR_60_TAPs;
22 Modifying the VHDL source code Architecture declarations architecture Behavioral of FIR_60_TAPs is signal DINR : std_logic_vector(din'range); type DINS_TYPE is array(n-1 downto 0) of std_logic_vector(din'range); signal DINS : DINS_TYPE; type COEFS_TYPE is array(59 downto 0) of std_logic_vector(15 downto 0); constant COEFS : COEFS_TYPE := ( x"ffff",x"ffb3",x"00d6",x"0063",x"fdb1",x"01d9",x"025f",x"fab4", x"0141",x"063b",x"f92d",x"fe5a",x"0825",x"fbe0",x"fccd",x"031e", x"0011",x"0410",x"f766",x"fcc2",x"1730",x"eeb3",x"ea68",x"2dac", x"f57a",x"cd9b",x"3731",x"0dd7",x"b74e",x"2a15",x"2a15",x"b74e", x"0dd7",x"3731",x"cd9b",x"f57a",x"2dac",x"ea68",x"eeb3",x"1730", x"fcc2",x"f766",x"0410",x"0011",x"031e",x"fccd",x"fbe0",x"0825", x"fe5a",x"f92d",x"063b",x"0141",x"fab4",x"025f",x"01d9",x"fdb1", x"0063",x"00d6",x"ffb3",x"ffff"); type MULT_TYPE is array(59 downto 0) of std_logic_vector(31 downto 0); signal MULT : MULT_TYPE; attribute syn_multstyle : string; attribute syn_multstyle of MULT : signal is "logic"; type ADD_TYPE is array(59 downto 0) of std_logic_vector(37 downto 0); signal ADD : ADD_TYPE; constant ZERO : std_logic_vector(37 downto 0) := (others => '0');
23 Modifying the VHDL source code begin RTL code process(ck) begin if CK'event and CK = '1' then DINR <= DIN; DINS <= DINS(N-2 downto 0) & DINR; for I in 59 downto 0 loop MULT(I) <= DINS(N-1) * COEFS(59-I); if I = 0 then ADD(I) <= ZERO + MULT(0); else ADD(I) <= MULT(I) + ADD(I-1); end if; end loop; Input register DOUT <= ADD(59); DIN end if; DINR COEF(59) COEF(58) end process; end Behavioral; COEF(2) COEF(1) COEF(0) MULT(0) MULT(1) MULT(57) MULT(58) MULT(59) Output register ADD(58) + ADD(0) ADD(56) ADD(57) ADD(59) DOUT
24 Setting up Synplify-Pro synthesis options (ISE environment) 140 Mhz request to have some extra timing margin for routing Retiming option to allow Synplify-Pro to rearrange the Flip-Flops where needed to obtain the required performance
25 Setting up SynplifyPro synthesis options (Synplify-Pro environment) An extra routing delay of 1 ns is used to improve accuracy and match post place-and-route results Retiming option to allow Synplify-Pro to re-arrange the Flip- Flops where needed to obtain the required performance Specify I/O locations All constraints are forward-annotated annotated to Xilinx (.ncf file)
26 Implementation results using Synplify-Pro RETIMING option Number of Slice Flip Flops: 4,158 out of 11,776 36% (4,068 FFs) Number of 4 input LUTs: 4,289 out of 11,776 36% (4,450 LUTs) Number of occupied Slices: 2,426 out of 5,888 43% (2,660 Slices) Number of bonded IOBs: 55 out of % IOB Flip Flops: 54 Almost 10% improvement in slice utilization Constraint Check Worst Case Best Case Timing Timing Slack Achievable Errors Score NET "CK" PERIOD = ns 0.008ns 8.325ns Total REAL time to PAR completion: 1 mins 30 secs 120 Mhz worst case for the lowest speed grade Previous results (no pipe) No more timing errors!!!
27 Conclusion Many improvements are still possible to save additional logic resources (more than 10% of slices) and/or improve timing. Note that the implementation would give similar results with any other Spartan3 family. Much higher performance with Virtex4 or Virtex5 family However, we have seen that by combining a good understanding of the Xilinx FPGA architecture an efficient structure for the FIR implementation (transpose in this case) an efficient coding (less than 10 lines for an N tap filter) appropriate features of Synplify-Pro/ Synplify-Premier such a design can be done in less than 15 minutes, starting from scratch.
28 Conclusion Xilinx FPGA are very well suited for many kind of applications, particularly for DSP design, even when DSP blocks or dedicated multipliers are not available. Synplify-Pro/ Synplify-Premier takes advantage of the powerful Xilinx FPGA architecture User must be aware of the architectures and tools features MVD offers public and on site trainings. VHDL, Xilinx architectures & tools, design methodology, FPGA based DSP, MicroBlaze, PowerPC PDF and source code available at : Corporate => publications => press publications and app notes Sociéte => publications => publications de presse et notes d applications
29 Thank You!
Step : Create Dependency Graph for Data Path Step b: 8-way Addition? So, the data operations are: 8 multiplications one 8-way addition Balanced binary
RTL Design RTL Overview Gate-level design is now rare! design automation is necessary to manage the complexity of modern circuits only library designers use gates automated RTL synthesis is now almost
High-Level Synthesis for FPGA Designs
High-Level Synthesis for FPGA Designs BRINGING BRINGING YOU YOU THE THE NEXT NEXT LEVEL LEVEL IN IN EMBEDDED EMBEDDED DEVELOPMENT DEVELOPMENT Frank de Bont Trainer consultant Cereslaan 10b 5384 VT Heesch
LMS is a simple but powerful algorithm and can be implemented to take advantage of the Lattice FPGA architecture.
February 2012 Introduction Reference Design RD1031 Adaptive algorithms have become a mainstay in DSP. They are used in wide ranging applications including wireless channel estimation, radar guidance systems,
DDS. 16-bit Direct Digital Synthesizer / Periodic waveform generator Rev. 1.4. Key Design Features. Block Diagram. Generic Parameters.
Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core 16-bit signed output samples 32-bit phase accumulator (tuning word) 32-bit phase shift feature Phase resolution of 2π/2
Digital Design with VHDL
Digital Design with VHDL CSE 560M Lecture 5 Shakir James Shakir James 1 Plan for Today Announcement Commentary due Wednesday HW1 assigned today. Begin immediately! Questions VHDL help session Assignment
ECE 3401 Lecture 7. Concurrent Statements & Sequential Statements (Process)
ECE 3401 Lecture 7 Concurrent Statements & Sequential Statements (Process) Concurrent Statements VHDL provides four different types of concurrent statements namely: Signal Assignment Statement Simple Assignment
Implementation of Modified Booth Algorithm (Radix 4) and its Comparison with Booth Algorithm (Radix-2)
Advance in Electronic and Electric Engineering. ISSN 2231-1297, Volume 3, Number 6 (2013), pp. 683-690 Research India Publications http://www.ripublication.com/aeee.htm Implementation of Modified Booth
12. A B C A B C A B C 1 A B C A B C A B C JK-FF NETr
2..,.,.. Flip-Flops :, Flip-Flops, Flip Flop. ( MOD)... -8 8, 7 ( ).. n Flip-Flops. n Flip-Flops : 2 n. 2 n, Modulo. (-5) -4 ( -), (-) - ( -).. / A A A 2 3 4 5 MOD-5 6 MOD-6 7 MOD-7 8 9 / A A A 2 3 4 5
VHDL GUIDELINES FOR SYNTHESIS
VHDL GUIDELINES FOR SYNTHESIS Claudio Talarico For internal use only 1/19 BASICS VHDL VHDL (Very high speed integrated circuit Hardware Description Language) is a hardware description language that allows
VHDL Test Bench Tutorial
University of Pennsylvania Department of Electrical and Systems Engineering ESE171 - Digital Design Laboratory VHDL Test Bench Tutorial Purpose The goal of this tutorial is to demonstrate how to automate
Introduction to Xilinx System Generator Part II. Evan Everett and Michael Wu ELEC 433 - Spring 2013
Introduction to Xilinx System Generator Part II Evan Everett and Michael Wu ELEC 433 - Spring 2013 Outline Introduction to FPGAs and Xilinx System Generator System Generator basics Fixed point data representation
An Open Source Circuit Library with Benchmarking Facilities
An Open Source Circuit Library with Benchmarking Facilities Mariusz Grad and Christian Plessl Paderborn Center for Parallel Computing, University of Paderborn {mariusz.grad christian.plessl}@uni-paderborn.de
LAB #3 VHDL RECOGNITION AND GAL IC PROGRAMMING USING ALL-11 UNIVERSAL PROGRAMMER
LAB #3 VHDL RECOGNITION AND GAL IC PROGRAMMING USING ALL-11 UNIVERSAL PROGRAMMER OBJECTIVES 1. Learn the basic elements of VHDL that are implemented in Warp. 2. Build a simple application using VHDL and
if-then else : 2-1 mux mux: process (A, B, Select) begin if (select= 1 ) then Z <= A; else Z <= B; end if; end process;
if-then else : 2-1 mux mux: process (A, B, Select) begin if (select= 1 ) then Z
Hardware Implementation of the Stone Metamorphic Cipher
International Journal of Computer Science & Network Security VOL.10 No.8, 2010 Hardware Implementation of the Stone Metamorphic Cipher Rabie A. Mahmoud 1, Magdy Saeb 2 1. Department of Mathematics, Faculty
Introduction. Jim Duckworth ECE Department, WPI. VHDL Short Course - Module 1
VHDL Short Course Module 1 Introduction Jim Duckworth ECE Department, WPI Jim Duckworth, WPI 1 Topics Background to VHDL Introduction to language Programmable Logic Devices CPLDs and FPGAs FPGA architecture
Sprites in Block ROM
Sprites in Block ROM 1 Example 37 Sprites in Block ROM In Example 36 we made a sprite by storing the bit map of three initials in a VHDL ROM. To make a larger sprite we could use the Core Generator to
A DA Serial Multiplier Technique based on 32- Tap FIR Filter for Audio Application
A DA Serial Multiplier Technique ased on 32- Tap FIR Filter for Audio Application K Balraj 1, Ashish Raman 2, Dinesh Chand Gupta 3 Department of ECE Department of ECE Department of ECE Dr. B.R. Amedkar
AES (Rijndael) IP-Cores
AES (Rijndael) IP-Cores Encryption/Decryption and Key Expansion Page 1 Revision History Date Version Description 24 February 2006 1.0 Initial draft. 15 March 2006 1.1 Block diagrams added. 26 March 2006
FPGA Implementation of Boolean Neural Networks using UML
FPGA Implementation of Boolean Neural Networks using UML Roman Kohut,, Bernd Steinbach, Dominik Fröhlich Freiberg University of Mining and Technology Institute of Computer Science Freiberg (Sachs), Germany
An Example VHDL Application for the TM-4
An Example VHDL Application for the TM-4 Dave Galloway Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto March 2005 Introduction This document describes a simple
Optimising the resource utilisation in high-speed network intrusion detection systems.
Optimising the resource utilisation in high-speed network intrusion detection systems. Gerald Tripp www.kent.ac.uk Network intrusion detection Network intrusion detection systems are provided to detect
Quartus II Introduction for VHDL Users
Quartus II Introduction for VHDL Users This tutorial presents an introduction to the Quartus II software. It gives a general overview of a typical CAD flow for designing circuits that are implemented by
Digital Systems Design. VGA Video Display Generation
Digital Systems Design Video Signal Generation for the Altera DE Board Dr. D. J. Jackson Lecture 12-1 VGA Video Display Generation A VGA signal contains 5 active signals Two TTL compatible signals for
Vivado Design Suite Tutorial
Vivado Design Suite Tutorial High-Level Synthesis UG871 (v2012.2) August 20, 2012 Notice of Disclaimer The information disclosed to you hereunder (the Materials ) is provided solely for the selection and
Floating Point Fused Add-Subtract and Fused Dot-Product Units
Floating Point Fused Add-Subtract and Fused Dot-Product Units S. Kishor [1], S. P. Prakash [2] PG Scholar (VLSI DESIGN), Department of ECE Bannari Amman Institute of Technology, Sathyamangalam, Tamil Nadu,
A New Paradigm for Synchronous State Machine Design in Verilog
A New Paradigm for Synchronous State Machine Design in Verilog Randy Nuss Copyright 1999 Idea Consulting Introduction Synchronous State Machines are one of the most common building blocks in modern digital
Infinite Impulse Response Filter Structures in Xilinx FPGAs
White Paper: Spartan -3A DSP, Virtex -5/Virtex-4 FPGAs, LogiCOE IP WP330 (v1.2) August 10, 2009 Infinite Impulse esponse Filter Structures in Xilinx FPGAs By: Michael Francis A large percentage of filters
Introduction to Programmable Logic Devices. John Coughlan RAL Technology Department Detector & Electronics Division
Introduction to Programmable Logic Devices John Coughlan RAL Technology Department Detector & Electronics Division PPD Lectures Programmable Logic is Key Underlying Technology. First-Level and High-Level
System Generator for DSP
System Generator for DSP User Guide Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate
High Speed and Efficient 4-Tap FIR Filter Design Using Modified ETA and Multipliers
High Speed and Efficient 4-Tap FIR Filter Design Using Modified ETA and Multipliers Mehta Shantanu Sheetal #1, Vigneswaran T. #2 # School of Electronics Engineering, VIT University Chennai, Tamil Nadu,
40G MACsec Encryption in an FPGA
40G MACsec Encryption in an FPGA Dr Tom Kean, Managing Director, Algotronix Ltd, 130-10 Calton Road, Edinburgh EH8 8JQ United Kingdom Tel: +44 131 556 9242 Email: tom@algotronix.com February 2012 1 MACsec
Clock Data Recovery Design Techniques for E1/T1 Based on Direct Digital Synthesis Author: Paolo Novellini and Giovanni Guasti
Application Note: Virtex and Spartan FPGA Families XAPP868 (v1.0) January 29, 2008 Clock Data ecovery Design Techniques for E1/T1 Based on Direct Digital Synthesis Author: Paolo Novellini and Giovanni
Hardware Implementations of RSA Using Fast Montgomery Multiplications. ECE 645 Prof. Gaj Mike Koontz and Ryon Sumner
Hardware Implementations of RSA Using Fast Montgomery Multiplications ECE 645 Prof. Gaj Mike Koontz and Ryon Sumner Overview Introduction Functional Specifications Implemented Design and Optimizations
SDLC Controller. Documentation. Design File Formats. Verification
January 15, 2004 Product Specification 11 Stonewall Court Woodcliff Lake, NJ 07677 USA Phone: +1-201-391-8300 Fax: +1-201-391-8694 E-mail: info@cast-inc.com URL: www.cast-inc.com Features AllianceCORE
Modeling a GPS Receiver Using SystemC
Modeling a GPS Receiver using SystemC Modeling a GPS Receiver Using SystemC Bernhard Niemann Reiner Büttner Martin Speitel http://www.iis.fhg.de http://www.iis.fhg.de/kursbuch/kurse/systemc.html The e
MATLAB/Simulink Based Hardware/Software Co-Simulation for Designing Using FPGA Configured Soft Processors
MATLAB/Simulink Based Hardware/Software Co-Simulation for Designing Using FPGA Configured Soft Processors Jingzhao Ou and Viktor K. Prasanna Department of Electrical Engineering, University of Southern
FPGAs for High-Performance DSP Applications
White Paper FPGAs for High-Performance DSP Applications This white paper compares the performance of DSP applications in Altera FPGAs with popular DSP processors as well as competitive FPGA offerings.
Implementation and Design of AES S-Box on FPGA
International Journal of Research in Engineering and Science (IJRES) ISSN (Online): 232-9364, ISSN (Print): 232-9356 Volume 3 Issue ǁ Jan. 25 ǁ PP.9-4 Implementation and Design of AES S-Box on FPGA Chandrasekhar
7 Series FPGA Overview
7 Series FPGA Overview 7 Series FPGA Families Maximum Capability Lowest Power and Cost Industry s Best Price/Performance Industry s Highest System Performance Logic Cells Block RAM DSP Slices Peak DSP
VGA video signal generation
A VGA display controller VGA video signal generation A VGA video signal contains 5 active signals: horizontal sync: digital signal, used for synchronisation of the video vertical sync: digital signal,
:DVYHUVWHKWPDQXQWHU %HKDYLRUDO6\QWKHVH" $066FKZHL]$*
![:DVYHUVWHKWPDQXQWHU %HKDYLRUDO6\QWKHVH $066FKZHL]$*](/thumbs/25/4474797.jpg ":DVYHUVWHKWPDQXQWHU %HKDYLRUDO6\QWKHVH $066FKZHL]$*")
:DVYHUVWHKWPDQXQWHU %HKDYLRUDO6\QWKHVH" hehueolfn 57/'HVLJQIORZ 'HVLJQEHLVSLHO %HKDYLRUDO'HVLJQIORZ %HKDYLRUDO%HVFKUHLEXQJ %HKDYLRUDO6\QWKHVH 9RUWHLOHYRQ%HVFKUHLEXQJXQG6\QWKHVH (LQVDW]GHU%HKDYLRUDO6\QWKHVH
Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications
Application Report SBAA094 June 2003 Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications Miroslav Oljaca, Tom Hendrick Data Acquisition Products ABSTRACT
LogiCORE IP AXI Performance Monitor v2.00.a
LogiCORE IP AXI Performance Monitor v2.00.a Product Guide Table of Contents IP Facts Chapter 1: Overview Target Technology................................................................. 9 Applications......................................................................
Using Xilinx ISE for VHDL Based Design
ECE 561 Project 4-1 - Using Xilinx ISE for VHDL Based Design In this project you will learn to create a design module from VHDL code. With Xilinx ISE, you can easily create modules from VHDL code using
Design and FPGA Implementation of a Novel Square Root Evaluator based on Vedic Mathematics
International Journal of Information & Computation Technology. ISSN 0974-2239 Volume 4, Number 15 (2014), pp. 1531-1537 International Research Publications House http://www. irphouse.com Design and FPGA
Lab 1: Introduction to Xilinx ISE Tutorial
Lab 1: Introduction to Xilinx ISE Tutorial This tutorial will introduce the reader to the Xilinx ISE software. Stepby-step instructions will be given to guide the reader through generating a project, creating
Digital Design with Synthesizable VHDL
Digital Design with Synthesizable VHDL Prof. Stephen A. Edwards Columbia University Spring 2012 Combinational Logic in a Dataflow Style Hierarchy: Instantiating Components (entities) Combinational Logic
Modeling Latches and Flip-flops
Lab Workbook Introduction Sequential circuits are digital circuits in which the output depends not only on the present input (like combinatorial circuits), but also on the past sequence of inputs. In effect,
9/14/2011 14.9.2011 8:38
Algorithms and Implementation Platforms for Wireless Communications TLT-9706/ TKT-9636 (Seminar Course) BASICS OF FIELD PROGRAMMABLE GATE ARRAYS Waqar Hussain firstname.lastname@tut.fi Department of Computer
Applications of algorithms for image processing using programmable logic
Applications of algorithms for image processing using programmable logic Presented by: Nikolay Nenov, M. Sc. Ph. D. Student at the Technical University of Sofia E-mail: nenov@mail.bg Research director:
Best Practises for LabVIEW FPGA Design Flow. uk.ni.com ireland.ni.com
Best Practises for LabVIEW FPGA Design Flow 1 Agenda Overall Application Design Flow Host, Real-Time and FPGA LabVIEW FPGA Architecture Development FPGA Design Flow Common FPGA Architectures Testing and
Reconfigurable System-on-Chip Design
Reconfigurable System-on-Chip Design MITCHELL MYJAK Senior Research Engineer Pacific Northwest National Laboratory PNNL-SA-93202 31 January 2013 1 About Me Biography BSEE, University of Portland, 2002
Architekturen und Einsatz von FPGAs mit integrierten Prozessor Kernen. Hans-Joachim Gelke Institute of Embedded Systems Professur für Mikroelektronik
Architekturen und Einsatz von FPGAs mit integrierten Prozessor Kernen Hans-Joachim Gelke Institute of Embedded Systems Professur für Mikroelektronik Contents Überblick: Aufbau moderner FPGA Einblick: Eigenschaften
Source-Synchronous Serialization and Deserialization (up to 1050 Mb/s) Author: NIck Sawyer
Application Note: Spartan-6 FPGAs XAPP1064 (v1.2) November 19, 2013 Source-Synchronous Serialization and Deserialization (up to 1050 Mb/s) Author: NIck Sawyer Summary Spartan -6 devices contain input SerDes
Case Study: Improving FPGA Design Speed with Floorplanning
Case Study: Improving FPGA Design Speed with Floorplanning - An introduction to Xilinx PlanAhead 10.1 by Consultant Kent Salomonsen (kent.salomonsen@teknologisk.dk) Picture this: the RTL is simulating
Design and Implementation of Vending Machine using Verilog HDL
2011 2nd International Conference on Networking and Information Technology IPCSIT vol.17 (2011) (2011) IACSIT Press, Singapore Design and Implementation of Vending Machine using Verilog HDL Muhammad Ali
High-Level Synthesis Tools for Xilinx FPGAs
TM An Independent Evaluation of: High-Level Synthesis Tools for Xilinx FPGAs By the staff of Berkeley Design Technology, Inc Executive Summary In 2009, Berkeley Design Technology Inc. (BDTI), an independent
PROGETTO DI SISTEMI ELETTRONICI DIGITALI. Digital Systems Design. Digital Circuits Advanced Topics
PROGETTO DI SISTEMI ELETTRONICI DIGITALI Digital Systems Design Digital Circuits Advanced Topics 1 Sequential circuit and metastability 2 Sequential circuit - FSM A Sequential circuit contains: Storage
All Programmable Logic. Hans-Joachim Gelke Institute of Embedded Systems. Zürcher Fachhochschule
All Programmable Logic Hans-Joachim Gelke Institute of Embedded Systems Institute of Embedded Systems 31 Assistants 10 Professors 7 Technical Employees 2 Secretaries www.ines.zhaw.ch Research: Education:
Design and Analysis of Parallel AES Encryption and Decryption Algorithm for Multi Processor Arrays
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue, Ver. III (Jan - Feb. 205), PP 0- e-issn: 239 4200, p-issn No. : 239 497 www.iosrjournals.org Design and Analysis of Parallel AES
ON SUITABILITY OF FPGA BASED EVOLVABLE HARDWARE SYSTEMS TO INTEGRATE RECONFIGURABLE CIRCUITS WITH HOST PROCESSING UNIT
216 ON SUITABILITY OF FPGA BASED EVOLVABLE HARDWARE SYSTEMS TO INTEGRATE RECONFIGURABLE CIRCUITS WITH HOST PROCESSING UNIT *P.Nirmalkumar, **J.Raja Paul Perinbam, @S.Ravi and #B.Rajan *Research Scholar,
Digital Design and Synthesis INTRODUCTION
Digital Design and Synthesis INTRODUCTION The advances in digital design owe its progress to 3 factors. First the acceleration at which the CMOS technology has advanced in last few decades and the way
VHDL programmering H2
VHDL programmering H2 VHDL (Very high speed Integrated circuits) Hardware Description Language IEEE standard 1076-1993 Den benytter vi!! Hvornår blev den frigivet som standard første gang?? Ca. 1980!!
Lenguaje VHDL. Diseño de sistemas digitales secuenciales
Lenguaje VHDL Diseño de sistemas digitales secuenciales Flip-Flop D 1 entity d_ff is clk: in std_logic; d: in std_logic; q: out std_logic 2 end d_ff; P3 P1 5 Q D Q Q(t+1) 0 0 0 0 1 0 1 0 1 1 1 1 architecture
System on Chip Platform Based on OpenCores for Telecommunication Applications
System on Chip Platform Based on OpenCores for Telecommunication Applications N. Izeboudjen, K. Kaci, S. Titri, L. Sahli, D. Lazib, F. Louiz, M. Bengherabi, *N. Idirene Centre de Développement des Technologies
Vedicmultiplier for RC6 Encryption Standards Using FPGA
Vedicmultiplier for RC6 Encryption Standards Using FPGA M. Kavitha 1, CH. Rajendra Prasad 2, Dr. Syed Musthak Ahmed 3 Department of ECE, SR Engineering College, Warangal, India 1,2,3 ABSTRACT: This paper
Lab 1: Full Adder 0.0
Lab 1: Full Adder 0.0 Introduction In this lab you will design a simple digital circuit called a full adder. You will then use logic gates to draw a schematic for the circuit. Finally, you will verify
Printed Circuit Board Design with HDL Designer
Printed Circuit Board Design with HDL Designer Tom Winkert Teresa LaFourcade NASNGoddard Space Flight Center 301-286-291 7 NASNGoddard Space Flight Center 301-286-0019 tom.winkert8 nasa.gov teresa. 1.
Polymorphic AES Encryption Implementation
Polymorphic AE Encryption Implementation Ricardo Chaves, Leonel ousa Instituto uperior Técnico / INEC-ID Portugal, Lisbon Email: ricardo.chaves@inesc-id.pt Georgi Kuzmanov, tamatis Vassiliadis Computer
Implementation of Web-Server Using Altera DE2-70 FPGA Development Kit
1 Implementation of Web-Server Using Altera DE2-70 FPGA Development Kit A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENT OF FOR THE DEGREE IN Bachelor of Technology In Electronics and Communication
Design and Implementation of Fast Fourier Transform Algorithm in FPGA
Design and Implementation of Fast Fourier Transform Algorithm in FPGA Adriana Bonilla R., Roberto J. Vega L., Karlo G. Lenzi e Luís G. P. Meloni Abstract This paper shows a design and implementation of
FPGA area allocation for parallel C applications
1 FPGA area allocation for parallel C applications Vlad-Mihai Sima, Elena Moscu Panainte, Koen Bertels Computer Engineering Faculty of Electrical Engineering, Mathematics and Computer Science Delft University
A Compact FPGA Implementation of Triple-DES Encryption System with IP Core Generation and On-Chip Verification
Proceedings of the 2010 International Conference on Industrial Engineering and Operations Management Dhaka, Bangladesh, January 9 10, 2010 A Compact FPGA Implementation of Triple-DES Encryption System
In this example the length of the vector is determined by D length and used for the index variable.
Loops Loop statements are a catagory of control structures that allow you to specify repeating sequences of behavior in a circuit. There are three primary types of loops in VHDL: for loops, while loops,
Multipliers. Introduction
Multipliers Introduction Multipliers play an important role in today s digital signal processing and various other applications. With advances in technology, many researchers have tried and are trying
CPE 462 VHDL: Simulation and Synthesis
CPE 462 VHDL: Simulation and Synthesis Topic #09 - a) Introduction to random numbers in hardware Fortuna was the goddess of fortune and personification of luck in Roman religion. She might bring good luck
USB - FPGA MODULE (PRELIMINARY)
DLP-HS-FPGA LEAD-FREE USB - FPGA MODULE (PRELIMINARY) APPLICATIONS: - Rapid Prototyping - Educational Tool - Industrial / Process Control - Data Acquisition / Processing - Embedded Processor FEATURES:
Cascaded Counters. Page 1 BYU
Cascaded Counters Page 1 Mod-N Counters Generally we are interested in counters that count up to specific count values Not just powers of 2 A mod-n counter has N states Counts from 0 to N-1 then rolls
Asynchronous & Synchronous Reset Design Techniques - Part Deux
Clifford E. Cummings Don Mills Steve Golson Sunburst Design, Inc. LCDM Engineering Trilobyte Systems cliffc@sunburst-design.com mills@lcdm-eng.com sgolson@trilobyte.com ABSTRACT This paper will investigate
LogiCORE IP Block Memory Generator v7.3
LogiCORE IP Block Memory Generator v7.3 Product Guide Table of Contents SECTION I: SUMMARY IP Facts Chapter 1: Overview Feature Summary..................................................................
Getting Started with Embedded System Development using MicroBlaze processor & Spartan-3A FPGAs. MicroBlaze
Getting Started with Embedded System Development using MicroBlaze processor & Spartan-3A FPGAs This tutorial is an introduction to Embedded System development with the MicroBlaze soft processor and low
Introduction to Field Programmable Gate Arrays
Introduction to Field Programmable Gate Arrays Robert Trausmuth Wiener Neustadt University of Applied Sciences Summer 2006 Wiener Neustadt University of Applied Sciences, Austria Robert Trausmuth email:
Architectures and Platforms
Hardware/Software Codesign Arch&Platf. - 1 Architectures and Platforms 1. Architecture Selection: The Basic Trade-Offs 2. General Purpose vs. Application-Specific Processors 3. Processor Specialisation
Xilinx ISE. <Release Version: 10.1i> Tutorial. Department of Electrical and Computer Engineering State University of New York New Paltz
Xilinx ISE Tutorial Department of Electrical and Computer Engineering State University of New York New Paltz Fall 2010 Baback Izadi Starting the ISE Software Start ISE from the
Modeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit
Modeling Sequential Elements with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 4-1 Sequential Circuit Outputs are functions of inputs and present states of storage elements
FPGA Clocking. Clock related issues: distribution generation (frequency synthesis) multiplexing run time programming domain crossing
FPGA Clocking Clock related issues: distribution generation (frequency synthesis) Deskew multiplexing run time programming domain crossing Clock related constraints 100 Clock Distribution Device split
Finite State Machine Design and VHDL Coding Techniques
Finite State Machine Design and VHDL Coding Techniques Iuliana CHIUCHISAN, Alin Dan POTORAC, Adrian GRAUR "Stefan cel Mare" University of Suceava str.universitatii nr.13, RO-720229 Suceava iulia@eed.usv.ro,
2 n. (finite state machines).
. - S,, T FI-FO. ;. 2. ;,,.,, (sequential).. ( )... 3. ; (state) (state variables),.,, (state)..,,..,,. 4. ;. n 2 n., 2 n,, (finite state machines). 5. (feedback).,..,.,,. 6.,,., ( ).. ,.,. 7., ( ).,..,
ECE232: Hardware Organization and Design. Part 3: Verilog Tutorial. http://www.ecs.umass.edu/ece/ece232/ Basic Verilog
ECE232: Hardware Organization and Design Part 3: Verilog Tutorial http://www.ecs.umass.edu/ece/ece232/ Basic Verilog module ();
Design of All Digital FM Receiver Circuit
Design of All Digital FM Receiver Circuit Nursani Rahmatullah March 2005 Table of Contents Table of Contents...i Table of Figures...ii 1. Introduction...1 2. Architecture Description...1 2.1 Phase Detector...1
路 論 Chapter 15 System-Level Physical Design
Introduction to VLSI Circuits and Systems 路 論 Chapter 15 System-Level Physical Design Dept. of Electronic Engineering National Chin-Yi University of Technology Fall 2007 Outline Clocked Flip-flops CMOS
CoProcessor Design for Crypto- Applications using Hyperelliptic Curve Cryptography
CoProcessor Design for Crypto- Applications using Hyperelliptic Curve Cryptography 28. Februar 2008 Alexander Klimm, Oliver Sander, Jürgen Becker Institut für Technik der Informationsverarbeitung Sylvain
Chapter 2 Logic Gates and Introduction to Computer Architecture
Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are
HDL Simulation Framework
PPC-System.mhs CoreGen Dateien.xco HDL-Design.vhd /.v SimGen HDL Wrapper Sim-Modelle.vhd /.v Platgen Coregen XST HDL Simulation Framework RAM Map Netzliste Netzliste Netzliste UNISIM NetGen vcom / vlog.bmm.ngc.ngc.ngc
The Designer's Guide to VHDL
The Designer's Guide to VHDL Third Edition Peter J. Ashenden EDA CONSULTANT, ASHENDEN DESIGNS PTY. LTD. ADJUNCT ASSOCIATE PROFESSOR, ADELAIDE UNIVERSITY AMSTERDAM BOSTON HEIDELBERG LONDON m^^ yj 1 ' NEW
Coding Guidelines for Datapath Synthesis
Coding Guidelines for Datapath Synthesis Reto Zimmermann Synopsys July 2005 Abstract This document summarizes two classes of RTL coding guidelines for the synthesis of datapaths: Guidelines that help achieve
FPGA. AT6000 FPGAs. Application Note AT6000 FPGAs. 3x3 Convolver with Run-Time Reconfigurable Vector Multiplier in Atmel AT6000 FPGAs.
3x3 Convolver with Run-Time Reconfigurable Vector Multiplier in Atmel AT6000 s Introduction Convolution is one of the basic and most common operations in both analog and digital domain signal processing.
Sequential 4-bit Adder Design Report
UNIVERSITY OF WATERLOO Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4-bit Adder Design Report Prepared by: Ian Hung (ixxxxxx), 99XXXXXX Annette Lo (axxxxxx), 99XXXXXX Pamela
Distributed Elastic Switch Architecture for efficient Networks-on-FPGAs
Distributed Elastic Switch Architecture for efficient Networks-on-FPGAs Antoni Roca, Jose Flich Parallel Architectures Group Universitat Politechnica de Valencia (UPV) Valencia, Spain Giorgos Dimitrakopoulos