Digital Systems Laboratory 1 IE5 / WS 2002

Transcription

1 hochschule fu r angewandte wissenschaften FACHBEREICH ELEKTROTECHNIK UND INFORMATIK hamburg university of applied sciences digital and microprocessor systems laboratory Digital Systems Laboratory 1 IE5 / WS 2002 In this course you are going to work out four labs. The topics of the labs relate directly to the corresponding course DS. The digital designs have to be developed and implemented in hardware with XILINX-ISE software tool. The design entry will be performed with VHDL coding. All developments will be implemented with XILINX-CPLD XC95108 hardware. This outline gives information about the recommended reading, the necessary lab preparation, the work library of the development PCs and the final documentation. You will have to work with the following handouts: 1. Lab descriptions which are listed in the table. 2. Instructions to handle XILINX-ISE. This is a red line paper with information about the steps you have to choose for design development. 3. Instructions to work with the VHDL simulator ModelSim XE. 4. Course handout XILINX XC95108 CPLD Device Architecture. Survey to four labs during WS 2002 (please remark the special time scheduling for week 47 to 50): Lab no. Topic 1 Design of a traffic light controller for a pedestrian crossing. Lab goals: Implementation of a finite state machine (FSM) in interconnection with a controlled counter. 2 Design of a controlled 8-bit shift register. Lab goals: Implementation of a parallel-load / serial-parallel converter. 3 Design of an evaluator for a quadratic polynomial. Lab goals: Implementation of a controller/datapath architecture. The datapath design has to follow constrains on hardware resources. 4 Design of an evaluator for a quadratic polynomial based on a controller/datapath architecture with a pipelined datapath structure. Lab goals: Experiences with the timing of a pipelined algorithm. Recommendations for lab preparation! Each lab has to be prepared appropriately in order that you are able to: present a written/drawn concept for the digital circuit or system, present prepared ASM charts and state diagrams, present a VHDL model (compiled *.vhd file on a disk) for the design you have to implement, present a concept for the hardware verification. Important notes which have to be reminded during the labs: Start to login to the lab PC with the local PC name (DIP<number of PC>). You don t need to login with a password. You have to copy your VHDL design files into the work directory C:\Isewrk. You are not allowed to change any existing path or implement any new work directory. With each start of the PC a new work directory c:\isewrk will be created. This prepared work directory contains several useful files (*.ucf; seg7.vhd;*.do). You should not expect that your development results will be available on the PC at the next day. Therefore you should copy basic files (*.vhd; *.do; *.ucf; *.rpt) to your disk Please remember that VHDL filenames and the including entity names should be identically in order to avoid misunderstandings of information yielded by the software tools. You have to choose entity, project, and command file names with less or equal 8 characters, because otherwise design implementation may cause problems. No a, u, o are not allowed for proper operation. During all labs the development results have to be verified by VHDL or timing simulations before design implementation will be tested. You have to edit appropriate *.do command files because design debugging will be more efficient. 1 SWR 02 1

2 Guide through the lab records (write-ups): Each lab has to be accomplished by a documentation. Following parts should be included: You have to explain the development of block diagrams, decision charts, state diagrams, ASM charts, logic functions and VHDL code semantics. The meaning of all VHDL signals and variables have to be made plausible, i. e. with identically named interconnection lines in a speaking block schematic. In order to convince with your lab results you have to add comments on all command files, simulation timings, with which you have tested your design. We also expect comments on all element groups of the schematics or logic equations (comp. *.rpt file: i. e. combinational logic, unexpected latches, flip-flops and three-state drivers). Pinout of the implemented digital circuit. Finish the lab documentation with a schematic of the complete test system (device under test, signal generator and oscilloscope). 2

3 Student group: hochschule fu r angewandte wissenschaften FACHBEREICH ELEKTROTECHNIK UND INFORMATIK hamburg university of applied sciences Professors comment: digital and microprocessor systems laboratory Record editor: Date: Group members: Professor: 1. Lab: Traffic Light Controller The controller for traffic lights at a pedestrian crossing has to be developed. A pedestrian who wants to cross a road has to push a button (PB) at a traffic light sign post. A sequence of light changes gives green or red lights to the pedestrian (PEGR, PDRE) and green, yellow or red lights to the drivers directions (DRGR, DRYE, DRRE). The sequence of traffic light states is described with table 1. The number of cycles of a chosen clock period determines the duration of each state. A sequence controller has to be build up with a synchronous Mealy state machine. The FSM will be switched on State PB Function Cycles DRRE DRYE DRGR PDRE PDGR S0 0 Initial state, waiting S1 was 1 Push button has been pressed, system switched on S2 X Drivers direction yellow S3 X Drivers dir. red S4 X Pedestrians dir. green S5 X Pedestrians dir. red S6 X Drivers dir. red/yellow S7 X Drivers dir. green Table 1: Sequence of traffic light states and number of clock cycles. with the pedestrians push button PB. The duration of each state has to be controlled by a synchronous 5-bit counter (Q[4:0]). Parallel to the next state calculation (Si / Si+1) the counter is reset synchronously by the FSM output CLR. In order to reduce the number of CPLD macrocells a state encoding has to be chosen which is described by the following state diagram. 0xxxx/0 x00100/1 x00001/1 x00100/1 Reset reset 1xxxx/0 x00100/0 x00001/ x01110/ x00001/ x01001/ x11101/ x01110/1 x00001/1 x01001/1 x11101/1 B 5 DRRE DRYE DRGR PDRE PDGR PB Q4 Q3 Q2 Q1 Q0/ CLR 3

4 The development should begin with a block diagram which describes all interfaces of two components. Both components have to be modelled and tested separately. The traffic controller system has to be described then with a structural model which contains instantiations of both components. Template of a structural model with components: -- Template for a structural model entity TRAFFIC_CONTROL is -- external ports. port(reset, CLK, PB : in bit; OUTP : out bit_vector(4 downto 0)); end TRAFFIC_CONTROL; architecture STRUCTURE of TRAFFIC_CONTROL is signal CLR_I: BIT; signal Q_I: BIT_VECTOR(4 downto 0); -- component-declaration: used IC-type component COUNTER_T_C port( CLR, CLK : in BIT ; QOUT : out BIT_VECTOR ); end component; component LIGHT_CONT -- light controller Mealy-FSM port( RESET, PB, CLK : in BIT ; COUNT : in BIT_VECTOR(4 downto 0); CLR : out BIT ; LIGHTS: out bit_vector(4 downto 0)); end component; begin -- component instantiation: socket interfacing INST_1: COUNTER_T_C -- connector of component => internal signal or external interface port map(clr => CLR_I, CLK => CLK, QOUT => Q_I); INST_2: LIGHT_CONT port map(reset => RESET, PB => PB, CLK => CLK, COUNT => Q_I, CLR => CLR_I, LIGHTS => OUTP); end STRUCTURE; Single Steps Develop a 5-bit counter VHDL code with a synchronous reset and symbolic signal delays (after 20 ns) in signal assignments. Counter VHDL simulation. Develop a two-process FSM model VHDL code. FSM VHDL simulation. Develop a structural VHDL model as described above. Synthesis and design implementation. Apply implementation options : Simulation: ModelSim VHDL Timing simulation with ModelSim and check the signal propagation from clock edge to selected outputs. Build up the device under test with an XS-95 board. Connect the control signals to the traffic light model. Measurements of signal propagation delay has to be performed. Documentation VHDL code and a corresponding decision chart. VHDL code and a block diagram. VHDL code and corresponding block diagram. Pin out and comments on logic equations, check the *.rpt file. result print out and comments on worst case signal delays. Hand drawing of used equipment and measured signals. The results have to be explained to the professor or to the technical assistant. 4

5 Student group: hochschule fu r angewandte wissenschaften FACHBEREICH ELEKTROTECHNIK UND INFORMATIK hamburg university of applied sciences Professors comment: digital and microprocessor systems laboratory Record editor: Date: Group members: Professor: 2. Lab: 8-Bit Parallel-Load Shift Register A Johnson counter contains the basic structure of a shift register which is made up by a chain of D-FFs. Beginning with the LSB of a register (a number of D-FFs) each D-FF output can be connected to the data input of the D-FF with next higher weight. This chain of D-FFs includes the ability to shift the bits of the register to the left (LSB to MSB) or to the right (MSB to LSB). For example, a sequence of bits can be converted into a word by shifting the bits into a register and moving the bits along at each clock edge. After a sufficient number of clock edges, namely the number n of D-FFs, the n bits of a word are available as a single word. This is known as serial-in, parallel-out register. During the shift processing all bits which have been stored before will be lost. Applications of shift registers will be found in serial communication interfaces. The receiver input device will clock in a data stream of sequenced bits and a parallel word will be accessed by internal processes. A sender will clock out a parallel stored word over a serial register output. Simple multiply and division operations can be performed by a shift register. A multiplication by two will be done with a shift left by one bit. A VHDL-module which models a shift register type SN74HC166 has to be implemented with a CPLD XC95108 (compare link with TI data sheet pages). Describe the main functionality with a clocked process. The priority of control inputs is described by the data sheet function table. Start with development of a decision chart which resumes following order of input signal checking: 1. Asynchronous and low active clear. 2. Clock edged check of an internal signal which is build up with an ORing of two inputs clock CLK and clock inhibit CLK_INH. 3. Synchronous load with SH_LD_N = Shift enable with SH_LD_N = 1. Shift of serial input SER from LSB to MSB output QH which means shift left. Therefore you should use the label SEL for serial data input. Additional requirements: 1. All 8 register bits should be accessible at the module output. 2. Append a controlled tristate output driver to the all register outputs. The enable signal should be EN. In order to apply a high impedance state the IEEE-library has to be included to the VHDL code (compare counter lab DC I) and the signal type std_logic has to be used. Implementation advice: The shift left operation can be done by taking the lowest (8-1) bits of Q[7:0] and concatenating the serial input bit SEL to the LSB position and assign it to Q[7:0]. Pseudo-random generator (PSRG, compare J. Wakerly: Digital Design; page ): Another shift register or ring counter application that is simple in terms of next state logic is the linear feedback shift register (LFSR). The next state logic is formed by XOR gates. The sequence of states appears to be random. In order to avoid a stop of sequence an appropriate set condition has to be applied and a self correcting circuit has to be connected to the load input. 5

6 Single Steps Develop a shift register VHDL code according to the datasheet. VHDL simulation. Append a tri-state driver process to the shift register VHDL code. VHDL simulation. Develop a LFSR VHDL code with signal feedback from the shift register output. VHDL simulation. Synthesis and design implementation of the shift register with tri-state outputs. Apply implementation options : Simulation: ModelSim VHDL Timing simulation with ModelSim and check the signal propagation from clock edge to selected outputs. Build up the device under test with an XS-95 board. Connect the shift register signals to an external LED device.. Documentation VHDL code and a corresponding decision chart. VHDL code and a block diagram of both components. VHDL code and block diagram. Pin out and comments on logic equations, check the *.rpt file. result print out and comments on worst case signal delays. Hand drawing of used equipment and measured signals. The results have to be explained to the professor or to the technical assistant. 6

7 Student group: hochschule fu r angewandte wissenschaften FACHBEREICH ELEKTROTECHNIK UND INFORMATIK hamburg university of applied sciences Professors comment: digital and microprocessor systems laboratory Record editor: Date: Group members: Professor: 3. Lab: Evaluator for a Quadratic Equation with Constrained Hardware The quadratic polynomial y = ax 2 + bx + c has to be implemented in hardware with constant coefficients a, b and c. Only unsigned numbers for the input variable x and the coefficients a, b and c are available. The 4-bit input x is provided by a loadable pseudo random generator (linear feedback shift register: LFSR) to the datapath which realises the arithmetic operations with 4-bit coefficients. Both components are under control of a FSM. An additional modulo-10 counter will be used by the FSM in order to control a dedicated number of calculations. The design of the datapath has to follow hardware resource constrains: only two multipliers and one adder are available each with two operands. Therefore the calculation of the quadratic polynomial has to be organised with a sequence of arithmetic operations where intermediate results will be registered and reused with the next step. A main aspect of this lab is given by the need to prepare an operator and register sharing which can be supported by multiplexers for operands and register inputs (comp. D. D. Gajski pages ). A synthesizable multiplication operator * is supported for the VHDL signal type unsigned by included libraries: library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; PB X0 CLK RESET CPLD XC95108 FSM LFSR Datapath Counter STOP X Y 7-Segment Display XESS Board Code Converter 7-Segment Display Fig. 1: Black box of the evaluator. X0 loadable 4-bit data to LFSR. PB push button for starting a number of calculations. STOP a new result Y is available. Lab preparation according to the black box in fig. 1: a) Draw a block diagram with interfacing between the FSM controller and all other components: LFSR, datapath and counter. Assign labels to control and status signals and data lines as well with appropriate vector widths. b) Derive an ASM chart which covers arithmetic and counter operations only. Loading of the LFSR with X0 should take place with next state transition when PB is pressed. Develop a signal lifetime table for all intermediate signals and apply a register-signal assignment for register sharing. c) Derive a datapath block diagram with multiplexers for operators and registers inputs respectively. Now the ASM chart can be enhanced with appropriate multiplexer select signal assignments. Vector widths of operands and result values have to be chosen carefully according to a worst case of maximum input values and coefficients < 9. d) With a full view to all control, status and data signals a state diagram for the FSM controller can be drawn. e) Finally the VHDL code for all components and a structural model (top entity) can be designed. 7

8 Single Steps Develop VHDL codes for all components according to the lab preparation steps and apply symbolic signal delays. VHDL simulation of all single components. Combine all VHDL codes (figure 1) in one top entity. VHDL simulation. Comparison of the results with pencil and paper work. Describe the latency of the calculation procedure. Synthesis and design implementation of the complete design entity. Apply implementation options : Simulation: ModelSim VHDL Timing simulation with ModelSim. Build up the device under test with an XS-95 board. Connect the result signal vector y to external 7-segment devices. Documentation VHDL code and all diagrams. Remember consistent signal naming VHDL codes of the structural model. ucf-file, pin out and comments on selected logic equations, check the *.rpt file. result print out and comments on worst case signal delays. Hand drawing of used equipment and measured signals. The results have to be explained to the professor or to the technical assistant. 8

9 Student group: hochschule fu r angewandte wissenschaften FACHBEREICH ELEKTROTECHNIK UND INFORMATIK hamburg university of applied sciences Professors comment: digital and microprocessor systems laboratory Record editor: Date: Group members: Professor: 4. Lab: Evaluator for a Quadratic Equation with a Pipelined Datapath With this design implementation of the evaluator (comp. 3 rd lab) no hardware constrains have to be applied except that operators with two operands should be regarded. The main aim is to have short combinational signal paths in order to increase the maximum applicable clock frequency. Therefore each arithmetic operation is separated from the other by a register stage. A new input value x will be processed through the chain of operations with each clock cycle step by step. The first result value y is available after a dedicated number of clock cycles which is determined by the number of register stages: This is called pipeline filling. But meanwhile the first x value is stepping through the pipeline another new value x is supplied to the pipeline by the LFSR with each clock cycle. As a result we experience a new output value y with each clock cycle as far as the pipeline has been filled. Finally the pipeline has to be flushed when the last x value has entered the pipeline. Lab preparation according to fig. 1 of the 3 rd lab: a) Draw a pipelined datapath structure with appropriate signal vector widths and enable signals for the register stages. b) The block diagram of connected components is nearly the same as with the 3 rd lab except that no select signals are necessary and more enable signals for the bigger number of registers has to be used. c) Develop an ASM chart which describes the enabling of register stages and is made up by three parts: Dedicated number of states for filling the pipeline. A cyclic part for the processing of a filled pipeline. A final part for flushing the pipeline which will be entered when the last input value x has been clocked in. With the first two parts the LFSR has to be enabled all the time and all operators are working concurrently. d) Develop a detailed state diagram for the FSM component which has the same structure as the ASM chart. e) Finally the VHDL code for the datapath component and the FSM can be designed from the scratch. The other parts have just to be modified. Single Steps Develop VHDL codes for all components according to the lab preparation steps and apply symbolic signal delays. VHDL simulation of all single components. Combine all VHDL codes in one top entity. VHDL simulation. Comparison of the results with pencil and paper work. Describe the latency of the calculation procedure. Synthesis and design implementation of the complete design entity. Apply implementation option: Simulation: ModelSim VHDL Timing simulation with ModelSim. Build up the device under test with an XS-95 board. Connect the result signal vector y to external 7-segment devices. Documentation VHDL code and all diagrams. Remember consistent signal naming result print out and comment on functionality. VHDL codes of the structural model. result print out and comment on functionality. *.ucf-file, pin out and comments on selected logic equations, check the *.rpt file. Command file *.do. Simulation result print out and comments on worst case signal delays. Hand drawing of used equipment and measured signals. The results have to be explained to the professor or to the technical assistant. 9

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