Lab 3: VHDL Implementations
|
|
- Dana Wilkinson
- 7 years ago
- Views:
Transcription
1 Lab 3: VHDL Implementations This laboratory will provide you with practice and experience writing VHDL descriptions. Specificially, you will be interfacing to an LCD display and register file (memory). To complete these tasks, you will have to design a counter, register file, and state machine controller. Task 1: Displaying to the LCD Display A digital I/O peripheral board that contains an LCD display can be attached to the Digilab 2E board. For this exercise, write a VHDL state machine that will display your name on the display. (If you are completing this lab in groups of two, then display one name on the top line of the LCD display and the other name on the bottom line.) Starting out Create a new Xilinx project for this lab and create the top-level file with the entity statement shown in Figure L3. The pin assignments for the top-level I/O signals are shown in Figure L3. Handling Global Clock Pins Any time an input or output signal is defined in the top-level entity statement, you must add an I/O Buffer component to it so the compiler will attach the signal to a physical I/O pin on the FPGA. By default, Xilinx automatically adds an I/O Buffer (IOB) to all standard I/O signals and adds a special Global Clock I/O Buffer (GCLKIOB) to all identified clock signals. Alternatively, you can go to Synthesize Properties Xilinx Specific Options and uncheck the Add I/O Buffers option. Of course, unchecking this option will 1
2 2 ENTITY top_level IS PORT ( clock : IN STD_LOGIC; reset_in : IN STD_LOGIC; rs : OUT STD_LOGIC; rw : OUT STD_LOGIC; enable : OUT STD_LOGIC; lcd_data : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END top_level; ARCHITECTURE behavioral OF top_level IS COMPONENT BUFGP PORT ( I : IN STD_LOGIC; O : OUT STD_LOGIC ); END COMPONENT; BEGIN SIGNAL reset : STD_LOGIC; U1: BUFGP PORT MAP ( I => reset_in, O => reset );... END behavioral; Figure L3.1: The top-level entity statement with a skeleton architecture. NET clock LOC = P80; NET reset_in LOC = P77; NET enable LOC = P148; NET rw LOC = P146; NET rs LOC = P145; NET lcd_data<0> LOC = P150; NET lcd_data<1> LOC = P149; NET lcd_data<2> LOC = P152; NET lcd_data<3> LOC = P151; NET lcd_data<4> LOC = P160; NET lcd_data<5> LOC = P154; NET lcd_data<6> LOC = P162; NET lcd_data<7> LOC = P161; Figure L3.2: The pin assignments for the top-level I/O signals. These assume that the Digilab IO2 peripheral board is connected to the Digilab 2E board via connectors C and D.
3 force you to explicitly instantiate an I/O Buffer component for each and every top-level I/O signal. Xilinx Spartan-IIE FPGAs have pins (or pads ) that are specifically designed for clock signals. These pins (pads) are attached to special global clock busses that are designed to be low skew. Because of this, only signals with GCLKIOBs can be assigned to the clock pins, and likewise, only standard I/O signals (with their standard IOBs) can be attached to standard I/O pins. In general, the clock pins should be saved for clock signals since there are a limited number of them. However, in the case of the Digilab 2E board, the single pushbutton on the board is tied to a global clock pin (pin 77). This project uses the pushbutton as a non-clock, reset signal, but the Xilinx synthesizer correctly identifies the reset signal as a standard I/O signal and automatically adds the standard IOB component to it. Now, the Mapper will generate an error, because it can t connect a standard IOB component with a global clock pad (pin). To fix this, the GCLKIOB component must be manually added to the reset signal. Add the BUFGP component as shown in Figure L3. When this component is present, the Synthesizer will use the GCLKIOB component and the Mapper will be able to attach the GCLKIOB component to the global clock pad (pin 77). 3 LCD Device Driver A low-level driver has already been designed to interface directly with the LCD display. Download this file (lcd driver.vhd) from WebCT and add it to your Xilinx project. Create component and port map statements for the device driver. Create internal signals for addr in, data in, write, and ready. All other signals, except clock, should be mapped to the appropriate top-level I/O signal. The clock signal needs to be driven with a 1 MHz clock signal. This can be done by using the CLOCK DIV module (see next section). To write to the LCD display, you must first check the ready signal. When it is High, the display is ready for the next character. Set the addr in signal to the desired position of the character (the top line of the LCD display is mapped to addresses 0x00 to 0x0F and the bottom line is mapped to 0x40 to 0x4F). Set the data in signal to the ASCII value of the character you wish to display. Finally, set the write signal
4 4 High to indicate that the address and data lines are valid. Note that all three of these signals can be set at the same time (i.e., in the same state). Also, be aware that the LCD driver looks for a pulse on the write line, so you must take it Low after each character is written. Using the CLOCK DIV Component A component called CLOCK DIV is provided for your use on WebCT. This component accepts the 50 MHz clock as an input and outputs clock signals at 1 MHz, 100 KHz, 10 KHz, 1 KHz, 100 Hz, 10 Hz, and 1 Hz. For this project, it should be used to obtain the clock signals for the LCD driver, your state machine in Task 2, and the counter in Task 3. You may also find is helpful in generating clocks for future labs. Also, this component can be easily modified to generate any desirable clock period that is a mutliple of 20 ns. Writing the State Machine Write a VHDL description of a state machine that displays your name in the LCD display. For simpliticy, the state machine clock can be the ready signal coming from the lcd driver module, and the reset signal coming from the BUFGP component should reset the state machine. Each state should send one character to the display. After all characters are displayed, go to a done state that outputs a 0 on the write line and stays in the done state. Also, you may need an init state that is your first state and also outputs a 0 on the write line. Driving the write signal is complicated by the fact that the LCD driver requires that it be pulsed High and Low for each character that is written to the driver. One possibility is to have write follow the ready signal when the state machine is not in the init or done states. The concurrent signal assignment for this behavior is write <= 0 WHEN ( (state = init) OR (state = done) ) ELSE ready; When your completed project compiles correctly, ask the TA for the Digilab DIO2 peripheral board and plug it into connectors C and D on your Digilab 2E board. Then apply power to the board and download your design file to the FPGA. Remember to get checked-off by the teaching assistant before continuing!
5 5 Task 2: Changing the State Machine Clock Change your state machine to be clocked by the 1 KHz clock signal supplied by the CLOCK DIV component. To keep the display functioning correctly, you will also need to ensure that the ready signal is High in each state before proceeding to the next state. In Task 1, this condition was assured, because the state machine was clocked by the ready signal so the states only advanced when the ready signal was High. Now, with a constant 1 KHz clock, it is possible (although unlikely with such a slow clock) that the ready signal will not be High when the next rising edge of the clock appears. Additionally, you need to change how the write signal is generated. For this task, it should be assigned with a with...select statement (i.e., like a standard Moore-type output). Keep in mind that the LCD driver requires that the write signal be pulsed High and Low once for each character sent to it. So, each character may need two states in the state machine. During the first state, write is Low (and the ready signal is checked), and during the second state write is High. Compile and download the project. It s behavior should be identical to that of Task 1. Remember to get checked-off by the teaching assistant before continuing!
6 6 Task 3: Scrolling Text The final task is to make your name scroll across the LCD display. Feel free to try your own approach in completing this exercise using VHDL. Following is the outline of one solution, but there are certainly other possibilities. First, create a memory array that holds the character values and treat it like a circular buffer from which the character values can be read. Use the type..is array construct to create an array of 16 8-bit std logic vectors. Then use concurrent signal assignments to assign the appropriate ASCII value to each element of the array to spell out your name. Any blank characters should be filled in with the space character, 0x20. Create a process that implements a 0-15 counter called offset. This process should be clocked on the falling edge of a 1 Hz clock signal, and offset should be defined as an std logic vector(3 downto 0). Finally, change the line that assigns lcd data to use the character array created earlier indexed by (addr in + offset). By truncating the overflow bit in this summation, we can achieve the modulus operation. This trick, of course, only works for mod ing by powers of 2. Remember to get checked-off by the teaching assistant before continuing! Report for Laboratory 3 The report for Laboratory 3 is due at the beginning of the next lab period (Sept. 23). For this report, turn in the following items: 1. Completed Check-off Sheet. 2. Properly documented VHDL code for Task 1 (follow the Format and Style sheet). 3. Properly documented VHDL code for Task 2 (follow the Format and Style sheet). 4. Properly documented VHDL code for Task 3 (follows the Format and Style sheet).
Lab 1: Introduction to Xilinx ISE Tutorial
Lab 1: Introduction to Xilinx ISE Tutorial This tutorial will introduce the reader to the Xilinx ISE software. Stepby-step instructions will be given to guide the reader through generating a project, creating
More informationLAB #3 VHDL RECOGNITION AND GAL IC PROGRAMMING USING ALL-11 UNIVERSAL PROGRAMMER
LAB #3 VHDL RECOGNITION AND GAL IC PROGRAMMING USING ALL-11 UNIVERSAL PROGRAMMER OBJECTIVES 1. Learn the basic elements of VHDL that are implemented in Warp. 2. Build a simple application using VHDL and
More informationTechnical Note. Micron NAND Flash Controller via Xilinx Spartan -3 FPGA. Overview. TN-29-06: NAND Flash Controller on Spartan-3 Overview
Technical Note TN-29-06: NAND Flash Controller on Spartan-3 Overview Micron NAND Flash Controller via Xilinx Spartan -3 FPGA Overview As mobile product capabilities continue to expand, so does the demand
More informationUsing Xilinx ISE for VHDL Based Design
ECE 561 Project 4-1 - Using Xilinx ISE for VHDL Based Design In this project you will learn to create a design module from VHDL code. With Xilinx ISE, you can easily create modules from VHDL code using
More informationRAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition
RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition A Tutorial Approach James O. Hamblen Georgia Institute of Technology Michael D. Furman Georgia Institute of Technology KLUWER ACADEMIC PUBLISHERS Boston
More informationVHDL Test Bench Tutorial
University of Pennsylvania Department of Electrical and Systems Engineering ESE171 - Digital Design Laboratory VHDL Test Bench Tutorial Purpose The goal of this tutorial is to demonstrate how to automate
More informationDDS. 16-bit Direct Digital Synthesizer / Periodic waveform generator Rev. 1.4. Key Design Features. Block Diagram. Generic Parameters.
Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core 16-bit signed output samples 32-bit phase accumulator (tuning word) 32-bit phase shift feature Phase resolution of 2π/2
More informationBelow is a diagram explaining the data packet and the timing related to the mouse clock while receiving a byte from the PS-2 mouse:
PS-2 Mouse: The Protocol: For out mini project we designed a serial port transmitter receiver, which uses the Baud rate protocol. The PS-2 port is similar to the serial port (performs the function of transmitting
More informationTechnical Aspects of Creating and Assessing a Learning Environment in Digital Electronics for High School Students
Session: 2220 Technical Aspects of Creating and Assessing a Learning Environment in Digital Electronics for High School Students Adam S. El-Mansouri, Herbert L. Hess, Kevin M. Buck, Timothy Ewers Microelectronics
More informationDecimal Number (base 10) Binary Number (base 2)
LECTURE 5. BINARY COUNTER Before starting with counters there is some vital information that needs to be understood. The most important is the fact that since the outputs of a digital chip can only be
More informationThe 104 Duke_ACC Machine
The 104 Duke_ACC Machine The goal of the next two lessons is to design and simulate a simple accumulator-based processor. The specifications for this processor and some of the QuartusII design components
More informationDigital Systems Design. VGA Video Display Generation
Digital Systems Design Video Signal Generation for the Altera DE Board Dr. D. J. Jackson Lecture 12-1 VGA Video Display Generation A VGA signal contains 5 active signals Two TTL compatible signals for
More informationModeling Latches and Flip-flops
Lab Workbook Introduction Sequential circuits are digital circuits in which the output depends not only on the present input (like combinatorial circuits), but also on the past sequence of inputs. In effect,
More informationData Acquisition Module with I2C interface «I2C-FLEXEL» User s Guide
Data Acquisition Module with I2C interface «I2C-FLEXEL» User s Guide Sensors LCD Real Time Clock/ Calendar DC Motors Buzzer LED dimming Relay control I2C-FLEXEL PS2 Keyboards Servo Motors IR Remote Control
More informationReading User Data from Configuration PROMs
Application Note: XC18V00, and Platform Flash POMs; Spartan-II, Spartan-3, Virtex, and Virtex-II FPGA Families XAPP694 (v1.1.1) November 19, 2007 eading User Data from Configuration POMs Summary This application
More information8051 MICROCONTROLLER COURSE
8051 MICROCONTROLLER COURSE Objective: 1. Familiarization with different types of Microcontroller 2. To know 8051 microcontroller in detail 3. Programming and Interfacing 8051 microcontroller Prerequisites:
More informationImplementation of Web-Server Using Altera DE2-70 FPGA Development Kit
1 Implementation of Web-Server Using Altera DE2-70 FPGA Development Kit A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENT OF FOR THE DEGREE IN Bachelor of Technology In Electronics and Communication
More informationDesign of Remote Laboratory dedicated to E2LP board for e-learning courses.
Proceedings of the E2LP Workshop Warsaw, 2014, pp. 25 29 DOI: 10.15439/2014F672 ACSIS, Vol. 4 Design of Remote Laboratory dedicated to E2LP board for e-learning courses. Jan Piwiński Email: jpiwinski@piap.pl
More informationRotary Encoder Interface for Spartan-3E Starter Kit
Rotary Encoder Interface for Spartan-3E Starter Kit Ken Chapman Xilinx Ltd 2 th February 26 Rev.2 With thanks to Peter Alfke (Xilinx Inc.) Limitations Limited Warranty and Disclaimer. These designs are
More information150127-Microprocessor & Assembly Language
Chapter 3 Z80 Microprocessor Architecture The Z 80 is one of the most talented 8 bit microprocessors, and many microprocessor-based systems are designed around the Z80. The Z80 microprocessor needs an
More informationEXPERIMENT 8. Flip-Flops and Sequential Circuits
EXPERIMENT 8. Flip-Flops and Sequential Circuits I. Introduction I.a. Objectives The objective of this experiment is to become familiar with the basic operational principles of flip-flops and counters.
More informationPing Pong Game with Touch-screen. March 2012
Ping Pong Game with Touch-screen March 2012 xz2266 Xiang Zhou hz2256 Hao Zheng rz2228 Ran Zheng yc2704 Younggyun Cho Abstract: This project is conducted using the Altera DE2 development board. We are aiming
More informationSerial port interface for microcontroller embedded into integrated power meter
Serial port interface for microcontroller embedded into integrated power meter Mr. Borisav Jovanović, Prof. dr. Predrag Petković, Prof. dr. Milunka Damnjanović, Faculty of Electronic Engineering Nis, Serbia
More informationEC313 - VHDL State Machine Example
EC313 - VHDL State Machine Example One of the best ways to learn how to code is seeing a working example. Below is an example of a Roulette Table Wheel. Essentially Roulette is a game that selects a random
More informationA New Paradigm for Synchronous State Machine Design in Verilog
A New Paradigm for Synchronous State Machine Design in Verilog Randy Nuss Copyright 1999 Idea Consulting Introduction Synchronous State Machines are one of the most common building blocks in modern digital
More informationA Verilog HDL Test Bench Primer Application Note
A Verilog HDL Test Bench Primer Application Note Table of Contents Introduction...1 Overview...1 The Device Under Test (D.U.T.)...1 The Test Bench...1 Instantiations...2 Figure 1- DUT Instantiation...2
More informationif-then else : 2-1 mux mux: process (A, B, Select) begin if (select= 1 ) then Z <= A; else Z <= B; end if; end process;
if-then else : 2-1 mux mux: process (A, B, Select) begin if (select= 1 ) then Z
More informationSKP16C62P Tutorial 1 Software Development Process using HEW. Renesas Technology America Inc.
SKP16C62P Tutorial 1 Software Development Process using HEW Renesas Technology America Inc. 1 Overview The following tutorial is a brief introduction on how to develop and debug programs using HEW (Highperformance
More informationModeling Registers and Counters
Lab Workbook Introduction When several flip-flops are grouped together, with a common clock, to hold related information the resulting circuit is called a register. Just like flip-flops, registers may
More informationIntroduction to the Altera Qsys System Integration Tool. 1 Introduction. For Quartus II 12.0
Introduction to the Altera Qsys System Integration Tool For Quartus II 12.0 1 Introduction This tutorial presents an introduction to Altera s Qsys system inegration tool, which is used to design digital
More information12. A B C A B C A B C 1 A B C A B C A B C JK-FF NETr
2..,.,.. Flip-Flops :, Flip-Flops, Flip Flop. ( MOD)... -8 8, 7 ( ).. n Flip-Flops. n Flip-Flops : 2 n. 2 n, Modulo. (-5) -4 ( -), (-) - ( -).. / A A A 2 3 4 5 MOD-5 6 MOD-6 7 MOD-7 8 9 / A A A 2 3 4 5
More informationCHAPTER 11: Flip Flops
CHAPTER 11: Flip Flops In this chapter, you will be building the part of the circuit that controls the command sequencing. The required circuit must operate the counter and the memory chip. When the teach
More informationDigital Design with VHDL
Digital Design with VHDL CSE 560M Lecture 5 Shakir James Shakir James 1 Plan for Today Announcement Commentary due Wednesday HW1 assigned today. Begin immediately! Questions VHDL help session Assignment
More informationPmod peripheral modules are powered by the host via the interface s power and ground pins.
Digilent Pmod Interface Specification Revision: November 20, 2011 1300 NE Henley Court, Suite 3 Pullman, WA 99163 (509) 334 6306 Voice (509) 334 6300 Fax Introduction The Digilent Pmod interface is used
More informationECE 3401 Lecture 7. Concurrent Statements & Sequential Statements (Process)
ECE 3401 Lecture 7 Concurrent Statements & Sequential Statements (Process) Concurrent Statements VHDL provides four different types of concurrent statements namely: Signal Assignment Statement Simple Assignment
More informationMassachusetts Institute of Technology Department of Electrical Engineering and Computer Science. 6.002 Electronic Circuits Spring 2007
Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.002 Electronic Circuits Spring 2007 Lab 4: Audio Playback System Introduction In this lab, you will construct,
More informationTimer A (0 and 1) and PWM EE3376
Timer A (0 and 1) and PWM EE3376 General Peripheral Programming Model Each peripheral has a range of addresses in the memory map peripheral has base address (i.e. 0x00A0) each register used in the peripheral
More informationLab Experiment 1: The LPC 2148 Education Board
Lab Experiment 1: The LPC 2148 Education Board 1 Introduction The aim of this course ECE 425L is to help you understand and utilize the functionalities of ARM7TDMI LPC2148 microcontroller. To do that,
More informationHD44780U (LCD-II) (Dot Matrix Liquid Crystal Display Controller/Driver)
HD4478U (LCD-II) (Dot Matrix Liquid Crystal Display Controller/Driver) Description The HD4478U dot-matrix liquid crystal display controller and driver LSI displays alphanumerics, Japanese kana characters,
More informationData Cables. Schmitt TTL LABORATORY ELECTRONICS II
Data Cables Data cables link one instrument to another. Signals can attenuate or disperse on long wires. A direct wire works best for short cables of less than 10 ft. A TTL cable connection can use a Schmitt
More informationPLL frequency synthesizer
ANALOG & TELECOMMUNICATION ELECTRONICS LABORATORY EXERCISE 4 Lab 4: PLL frequency synthesizer 1.1 Goal The goals of this lab exercise are: - Verify the behavior of a and of a complete PLL - Find capture
More informationVon der Hardware zur Software in FPGAs mit Embedded Prozessoren. Alexander Hahn Senior Field Application Engineer Lattice Semiconductor
Von der Hardware zur Software in FPGAs mit Embedded Prozessoren Alexander Hahn Senior Field Application Engineer Lattice Semiconductor AGENDA Overview Mico32 Embedded Processor Development Tool Chain HW/SW
More informationUsing Altera MAX Series as Microcontroller I/O Expanders
2014.09.22 Using Altera MAX Series as Microcontroller I/O Expanders AN-265 Subscribe Many microcontroller and microprocessor chips limit the available I/O ports and pins to conserve pin counts and reduce
More informationSerial Communications
Serial Communications 1 Serial Communication Introduction Serial communication buses Asynchronous and synchronous communication UART block diagram UART clock requirements Programming the UARTs Operation
More informationETEC 421 - Digital Controls PIC Lab 10 Pulse Width Modulation
ETEC 421 - Digital Controls PIC Lab 10 Pulse Width Modulation Program Definition: Write a program to control the speed of a dc motor using pulse width modulation. Discussion: The speed of a dc motor is
More informationNHD-0420D3Z-FL-GBW-V3
NHD-0420D3Z-FL-GBW-V3 Serial Liquid Crystal Display Module NHD- Newhaven Display 0420-4 Lines x 20 Characters D3Z- Model F- Transflective L- Yellow/Green LED Backlight G- STN-Gray B- 6:00 Optimal View
More informationGenerating MIF files
Generating MIF files Introduction In order to load our handwritten (or compiler generated) MIPS assembly problems into our instruction ROM, we need a way to assemble them into machine language and then
More informationVGA video signal generation
A VGA display controller VGA video signal generation A VGA video signal contains 5 active signals: horizontal sync: digital signal, used for synchronisation of the video vertical sync: digital signal,
More informationState Machines in VHDL
State Machines in VHDL Implementing state machines in VHDL is fun and easy provided you stick to some fairly well established forms. These styles for state machine coding given here is not intended to
More informationLab 17: Building a 4-Digit 7-Segment LED Decoder
Phys2303 L.A. Bumm [Nexys 1.1.2] Lab 17 (p1) Lab 17: Building a 4-Digit 7-Segment LED Decoder In this lab your will make 4 test circuits, the 4-digit 7-segment decoder, and demonstration circuit using
More informationCNC FOR EDM MACHINE TOOL HARDWARE STRUCTURE. Ioan Lemeni
CNC FOR EDM MACHINE TOOL HARDWARE STRUCTURE Ioan Lemeni Computer and Communication Engineering Department Faculty of Automation, Computers and Electronics University of Craiova 13, A.I. Cuza, Craiova,
More informationJTAG-HS2 Programming Cable for Xilinx FPGAs. Overview. Revised January 22, 2015 This manual applies to the HTAG-HS2 rev. A
1300 Henley Court Pullman, WA 99163 509.334.6306 www.digilentinc.com Programming Cable for Xilinx FPGAs Revised January 22, 2015 This manual applies to the HTAG-HS2 rev. A Overview The Joint Test Action
More informationMultiplexers Two Types + Verilog
Multiplexers Two Types + Verilog ENEE 245: Digital Circuits and ystems Laboratory Lab 7 Objectives The objectives of this laboratory are the following: To become familiar with continuous ments and procedural
More informationQuartus II Introduction for VHDL Users
Quartus II Introduction for VHDL Users This tutorial presents an introduction to the Quartus II software. It gives a general overview of a typical CAD flow for designing circuits that are implemented by
More informationAn Example VHDL Application for the TM-4
An Example VHDL Application for the TM-4 Dave Galloway Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto March 2005 Introduction This document describes a simple
More informationSPI Flash Programming and Hardware Interfacing Using ispvm System
March 2005 Introduction Technical Note TN1081 SRAM-based FPGA devices are volatile and require reconfiguration after power cycles. This requires external configuration data to be held in a non-volatile
More informationLAB #4 Sequential Logic, Latches, Flip-Flops, Shift Registers, and Counters
LAB #4 Sequential Logic, Latches, Flip-Flops, Shift Registers, and Counters LAB OBJECTIVES 1. Introduction to latches and the D type flip-flop 2. Use of actual flip-flops to help you understand sequential
More informationTable 1 below is a complete list of MPTH commands with descriptions. Table 1 : MPTH Commands. Command Name Code Setting Value Description
MPTH: Commands Table 1 below is a complete list of MPTH commands with descriptions. Note: Commands are three bytes long, Command Start Byte (default is 128), Command Code, Setting value. Table 1 : MPTH
More informationLenguaje VHDL. Diseño de sistemas digitales secuenciales
Lenguaje VHDL Diseño de sistemas digitales secuenciales Flip-Flop D 1 entity d_ff is clk: in std_logic; d: in std_logic; q: out std_logic 2 end d_ff; P3 P1 5 Q D Q Q(t+1) 0 0 0 0 1 0 1 0 1 1 1 1 architecture
More informationThe I2C Bus. NXP Semiconductors: UM10204 I2C-bus specification and user manual. 14.10.2010 HAW - Arduino 1
The I2C Bus Introduction The I2C-bus is a de facto world standard that is now implemented in over 1000 different ICs manufactured by more than 50 companies. Additionally, the versatile I2C-bus is used
More informationStep : Create Dependency Graph for Data Path Step b: 8-way Addition? So, the data operations are: 8 multiplications one 8-way addition Balanced binary
RTL Design RTL Overview Gate-level design is now rare! design automation is necessary to manage the complexity of modern circuits only library designers use gates automated RTL synthesis is now almost
More informationKeil C51 Cross Compiler
Keil C51 Cross Compiler ANSI C Compiler Generates fast compact code for the 8051 and it s derivatives Advantages of C over Assembler Do not need to know the microcontroller instruction set Register allocation
More informationPC Base Adapter Daughter Card UART GPIO. Figure 1. ToolStick Development Platform Block Diagram
TOOLSTICK VIRTUAL TOOLS USER S GUIDE RELEVANT DEVICES 1. Introduction The ToolStick development platform consists of a ToolStick Base Adapter and a ToolStick Daughter card. The ToolStick Virtual Tools
More informationice40 Oscillator Usage Guide
April 2015 Technical Note TN1296 Introduction The family, specifically Ultra and UltraLite, features two on-chip oscillators. An ultra-low power 10 khz oscillator is provided for Always-On applications
More informationFINITE STATE MACHINE: PRINCIPLE AND PRACTICE
CHAPTER 10 FINITE STATE MACHINE: PRINCIPLE AND PRACTICE A finite state machine (FSM) is a sequential circuit with random next-state logic. Unlike the regular sequential circuit discussed in Chapters 8
More information8-Bit Flash Microcontroller for Smart Cards. AT89SCXXXXA Summary. Features. Description. Complete datasheet available under NDA
Features Compatible with MCS-51 products On-chip Flash Program Memory Endurance: 1,000 Write/Erase Cycles On-chip EEPROM Data Memory Endurance: 100,000 Write/Erase Cycles 512 x 8-bit RAM ISO 7816 I/O Port
More informationLesson 10: Video-Out Interface
Lesson 10: Video-Out Interface 1. Introduction The Altera University Program provides a number of hardware controllers, called cores, to control the Video Graphics Array (VGA) Digital-to-Analog Converter
More informationAccurate Measurement of the Mains Electricity Frequency
Accurate Measurement of the Mains Electricity Frequency Dogan Ibrahim Near East University, Faculty of Engineering, Lefkosa, TRNC dogan@neu.edu.tr Abstract The frequency of the mains electricity supply
More informationDisturbance Recoder SPCR 8C27. Product Guide
Issued: April 1999 Status: Updated Version: C/26.04.2006 Data subject to change without notice Features Versatile digital disturbance recorder module for recording various phenomena in the electric power
More informationC8051F020 Utilization in an Embedded Digital Design Project Course. Daren R. Wilcox Southern Polytechnic State University Marietta, Georgia
C8051F020 Utilization in an Embedded Digital Design Project Course Daren R. Wilcox Southern Polytechnic State University Marietta, Georgia Abstract In this paper, the utilization of the C8051F020 in an
More informationDKWF121 WF121-A 802.11 B/G/N MODULE EVALUATION BOARD
DKWF121 WF121-A 802.11 B/G/N MODULE EVALUATION BOARD PRELIMINARY DATA SHEET Wednesday, 16 May 2012 Version 0.5 Copyright 2000-2012 Bluegiga Technologies All rights reserved. Bluegiga Technologies assumes
More informationRS-232 Communications Using BobCAD-CAM. RS-232 Introduction
RS-232 Introduction Rs-232 is a method used for transferring programs to and from the CNC machine controller using a serial cable. BobCAD-CAM includes software for both sending and receiving and running
More informationOpen Flow Controller and Switch Datasheet
Open Flow Controller and Switch Datasheet California State University Chico Alan Braithwaite Spring 2013 Block Diagram Figure 1. High Level Block Diagram The project will consist of a network development
More informationDesigning VM2 Application Boards
Designing VM2 Application Boards This document lists some things to consider when designing a custom application board for the VM2 embedded controller. It is intended to complement the VM2 Datasheet. A
More informationHello and welcome to this training module for the STM32L4 Liquid Crystal Display (LCD) controller. This controller can be used in a wide range of
Hello and welcome to this training module for the STM32L4 Liquid Crystal Display (LCD) controller. This controller can be used in a wide range of applications such as home appliances, medical, automotive,
More informationModeling a GPS Receiver Using SystemC
Modeling a GPS Receiver using SystemC Modeling a GPS Receiver Using SystemC Bernhard Niemann Reiner Büttner Martin Speitel http://www.iis.fhg.de http://www.iis.fhg.de/kursbuch/kurse/systemc.html The e
More informationModel 5511 Filler Controller User s Manual Version 1.1 October 2011
Thompson Scale Company WEIGHING SYSTEMS & PACKAGING MACHINERY CONTROLS 2758 Bingle Road Houston, Texas 77055 Phone: 713/932-9071 Fax: 713/932-9379 www.thompsonscale.com Model 5511 Filler Controller User
More informationUSB - FPGA MODULE (PRELIMINARY)
DLP-HS-FPGA LEAD-FREE USB - FPGA MODULE (PRELIMINARY) APPLICATIONS: - Rapid Prototyping - Educational Tool - Industrial / Process Control - Data Acquisition / Processing - Embedded Processor FEATURES:
More informationPrototyping ARM Cortex -A Processors using FPGA platforms
Prototyping ARM Cortex -A Processors using FPGA platforms Brian Sibilsky and Fredrik Brosser April 2016 Page 1 of 17 Contents Introduction... 3 Gating... 4 RAM Implementation... 7 esign Partitioning...
More informationSDLC Controller. Documentation. Design File Formats. Verification
January 15, 2004 Product Specification 11 Stonewall Court Woodcliff Lake, NJ 07677 USA Phone: +1-201-391-8300 Fax: +1-201-391-8694 E-mail: info@cast-inc.com URL: www.cast-inc.com Features AllianceCORE
More informationNo serious hazards are involved in this laboratory experiment, but be careful to connect the components with the proper polarity to avoid damage.
HARDWARE LAB 5/DESIGN PROJECT Finite State Machine Design of a Vending Machine Using Xilinx ISE Project Navigator and Spartan 3E FPGA Development Board with VHDL Acknowledgements: Developed by Bassam Matar,
More informationDEVELOPMENT OF DEVICES AND METHODS FOR PHASE AND AC LINEARITY MEASUREMENTS IN DIGITIZERS
DEVELOPMENT OF DEVICES AND METHODS FOR PHASE AND AC LINEARITY MEASUREMENTS IN DIGITIZERS U. Pogliano, B. Trinchera, G.C. Bosco and D. Serazio INRIM Istituto Nazionale di Ricerca Metrologica Torino (Italia)
More informationQuartus II Introduction Using VHDL Design
Quartus II Introduction Using VHDL Design This tutorial presents an introduction to the Quartus R II CAD system. It gives a general overview of a typical CAD flow for designing circuits that are implemented
More informationBuilding an Embedded Processor System on a Xilinx Zync FPGA (Profiling): A Tutorial
Building an Embedded Processor System on a Xilinx Zync FPGA (Profiling): A Tutorial Embedded Processor Hardware Design January 29 th 2015. VIVADO TUTORIAL 1 Table of Contents Requirements... 3 Part 1:
More informationNTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter
NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential
More informationAfter opening the Programs> Xilinx ISE 8.1i > Project Navigator, you will come to this screen as start-up.
After opening the Programs> Xilinx ISE 8.1i > Project Navigator, you will come to this screen as start-up. Start with a new project. Enter a project name and be sure to select Schematic as the Top-Level
More informationCSE467: Project Phase 1 - Building the Framebuffer, Z-buffer, and Display Interfaces
CSE467: Project Phase 1 - Building the Framebuffer, Z-buffer, and Display Interfaces Vincent Lee, Mark Wyse, Mark Oskin Winter 2015 Design Doc Due Saturday Jan. 24 @ 11:59pm Design Review Due Tuesday Jan.
More informationVHDL GUIDELINES FOR SYNTHESIS
VHDL GUIDELINES FOR SYNTHESIS Claudio Talarico For internal use only 1/19 BASICS VHDL VHDL (Very high speed integrated circuit Hardware Description Language) is a hardware description language that allows
More information4511 MODBUS RTU. Configuration Manual. HART transparent driver. No. 9107MCM100(1328)
4511 MODBUS RTU Configuration Manual HART transparent driver No. 9107MCM100(1328) 9107 CONTENTS Introduction... 3 Modbus basics... 3 Modbus RTU... 3 Supported Function Codes... 3 Modbus Parameters and
More informationMicrotronics technologies Mobile: 99707 90092
For more Project details visit: http://www.projectsof8051.com/rfid-based-attendance-management-system/ Code Project Title 1500 RFid Based Attendance System Synopsis for RFid Based Attendance System 1.
More informationHT1632C 32 8 &24 16 LED Driver
328 &216 LED Driver Features Operating voltage: 2.V~5.5V Multiple LED display 32 ROW /8 COM and 2 ROW & 16 COM Integrated display RAM select 32 ROW & 8 COM for 6 display RAM, or select 2 ROW & 16 COM for
More informationAVR Butterfly Training. Atmel Norway, AVR Applications Group
AVR Butterfly Training Atmel Norway, AVR Applications Group 1 Table of Contents INTRODUCTION...3 GETTING STARTED...4 REQUIRED SOFTWARE AND HARDWARE...4 SETTING UP THE HARDWARE...4 SETTING UP THE SOFTWARE...5
More informationIn-System Programming Design TM. Guidelines for ispjtag Devices. Introduction. Device-specific Connections. isplsi 1000EA Family.
In-System Design TM February 2002 Introduction In-system programming (ISP ) has often been billed as a direct replacement for configuring a device through a programmer. The idea that devices can simply
More informationFinite State Machine Design and VHDL Coding Techniques
Finite State Machine Design and VHDL Coding Techniques Iuliana CHIUCHISAN, Alin Dan POTORAC, Adrian GRAUR "Stefan cel Mare" University of Suceava str.universitatii nr.13, RO-720229 Suceava iulia@eed.usv.ro,
More informationHow to design and implement firmware for embedded systems
How to design and implement firmware for embedded systems Last changes: 17.06.2010 Author: Rico Möckel The very beginning: What should I avoid when implementing firmware for embedded systems? Writing code
More informationFinal Project Example
Final Project Example YM2149 Programmable Sound Generator Emulator PSoC Final Project Example Stephen Hammack Overview The YM2149 (a variant of the AY-3-8910) is a Programmable Sound Generator (PSG) that
More informationPCAN-MicroMod Universal I/O Module with CAN Interface. User Manual. Document version 2.1.0 (2014-01-16)
PCAN-MicroMod Universal I/O Module with CAN Interface User Manual Document version 2.1.0 (2014-01-16) Products taken into account Product Name Part number Model PCAN-MicroMod IPEH-002080 with firmware
More informationEvent counters in NOVA
Case study: how to use the event counters in NOVA? 1 Event counter support NOVA Technical Note 22 Event counters in NOVA Most of the measurement commands, like CV staircase or Record signals (> 1 ms) provide
More information