A 2.5 Gbps SONET STS 48/SDH STM 16 ADD DROP MULTIPLEXER

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1 A 2.5 Gbps SONET STS 48/SDH STM 16 ADD DROP MULTIPLEXER D. Torres, A. Castillo, J. Moreno, J. Vázquez and J. R. Verdín CINVESTAV del IPN Unidad Guadalajara ABSTRACT This paper proposes a flexible architecture for the implementation of an ADM (Add drop multiplexed) for SONET STS 48/SDH STM 16 streams. It can add/drop any combination of four streams, previously configured, SST s/stem s (STS 1, STS 3, STS 3c/STM 1, STS 12/STM 4, STS 12c/STM-4c). The architecture of the system is divided into three parts: the reception module, the transmission module and the configuration and control module. The reception module processes the input stream with the purpose of extracting the desired signal; transmission module provides SONET/SDH stream into the optic fiber once the desired streams have been inserted and the configured and control module accomplish the administration and maintenance operations. The TelecomBus interface used in the ADM allows the future growth communication of this device. This architecture uses the libraries previous developed in CINVESTAV of IPN, Guadalajara, Mexico [6], [7], [8], [9], [10], [11] and [12]. 1. INTRODUCTION SONET (Synchronous Optical Network) is an international standard for the transmission of information at high speed by means of optic fiber [1]. It is used mainly in United States and Canada. SDH (Synchronous Digital Hierarchy) descends from SONET and its structure of transport has been standardized by the ITU-T [2]. It is used in Europe and the rest of the world. This group of standards defines the transmission speeds, formats, interface parameters, multiplexing outlines and the specifications for the OAM&P (Operation, Administration, Maintenance and hence Provisioning) for the high-speed digital transmission. In SONET, the basic stream is the STS-1 (Synchronous Transport Signal level 1) whose transmission speed is Mbps. An STS-N stream is composed by byte interleaving of N STS-1's and its transmission rate is N times the rate of the basic stream. Each SONET STS-N stream is composed of frames with length of 125 µs (8000 frames per second) and each frame can be depicted as an array of 9 rows by 90xN columns, for a total of 810xN bytes. The basic stream of SDH is the STM-1 (Synchronous Transport Module level 1) with a transmission bit rate of Mbps, equivalent to three SONET STS-1 streams. In both SONET and SDH streams of higher order to STS- 1/STM-1, there exists a characteristic in the frames that it is known as concatenation. This is the procedure whereby a multiplicity of Virtual Containers or SPEs is associated one with another, resulting their combined capacity can be used as a single container in which bit sequence integrity is maintained [3]. An ADM (Add Drop Multiplexer) is a network element, corresponding to the line layer that provides access to all or a subset of the signals contained in an STS-N/STM-N signal. The signals are added and/or dropped of the STS-N/STM-N signal. The ADM multiplexer is a line element that only processes SOH/RSOH, LOH/Pointers and MSOH. These devices possess a great quantity of uses, either as intermediate device to consolidate signals of two different places or to implement networks type ring, like the one observed in Fig. 1. Fig. 1 Ring Architecture The presented architecture is focused on the design of an ADM STS-48/STM-16 that can extract/insert a previously configured combination of four streams STS/STM (STS-1, STS-3c/STM-1, STS-12c/STM-4c). In the ADM VT's are not processed (Virtual Tributaries). When the ADM extracts a certain stream, another of the same speed must also be inserted.

2 Main objectives of this work are:?? To specify the general requirements for the design of the network element STS-48/STM16 Add Drop Multiplexer (ADM).?? To propose the design architecture that satisfies the specification of requirements.?? To realize the verification plan to guarantee the operation of the device. In Fig. 4 can be observed the blocks that conform the design. Fig. 4 General Functional Diagram of the ADM 2. SYSTEM MODULES Due to the ability of the ADM of processing SONET streams as well as SDH streams, it must have a configuration system in order to be able to select the operation way, as well as another group of parameters. To carry out the extraction/insertion of lower order SONET/SDH streams to STS-48/STM-16 is necessary to use the multiplexing hierarchy that is shown in Fig. 2 and Fig. 3. Fig. 2 SONET Multiplexing Hierarchy The architecture of the ADM was designed based on the ANSI [1] and ITU-T [2] recommendations. The design blocks are:?? Interface.?? OAM.?? Processor and Generator of TOH/SOH.?? Switching element Interface This module establishes the communication between the device and the external world, in order to configure and supervise some signals of the device. Among the components of this module are:?? Microprocessor of 8/16 bits manages and configures the ADM by means of a hierarchical system of interruptions.?? An external reference clock will be used in case of a detection of the loss of clock in the incoming STS- 48/STM-16 signal of the ADM.?? TelecomBus is a standard for data transmission among diverse devices. This interface can be used for growing in the future OAM Module This module stores information for the operation, maintenance, and administration of the system. The maintenance functions are the detection of faults, which are carried out by means of the supervising of the alarm signals contained in the SONET/SDH frames, likewise, takes charge of generating the pertinent alarm signals in the frames to transmit. The administration functions allow configuring the diverse modes of operation of the system Processor and Generator of TOH/SOH In this module, the functions of the appropriate processing and generation are accomplished for the SONET/SDH signals. Among the functions that are carried out are:?? Frame alignment.?? Generation and processing of pointers.?? Descrambler.?? Module of Extraction/Insertion of streams SONET/SDH. Fig. 3 SDH Multiplexing Hierarchy 2.4. Switching Module In this module it is done the demultiplexing/multiplexing of the incoming/outgoing signals, in order to decompose it in the diverse signals of lower speed so that they can be

3 extracted, as well as to assemble the remaining signals with the new signals inserted for their transmission. This module also has a switching element, which carries out the connection between the input streams and output streams Extraction/Insertion of SONET/SDH Streams Module This module works with the switching element in order to carry out the extraction/insertion of the desired streams, respecting the original frame structure (STS-48/STM-16). A combination of four streams at the following rates: STS-1, STS-3c/STM-1, STS-12c/STM-4c can be extracted/inserted. 3. SYSTEM ARCHITECTURE In Fig. 5, it can be observed the architecture of the design of the ADM STS-48/STM-16. The architecture consists of the following blocks:?? Frame alignment.?? Processing of SOH/ROSH.?? Demultiplexing to streams STS 12/STM 4.?? Extraction of voice and data channels of SOH/RSOH.?? Processing of LOH/MSOH.?? Extraction of voice and data channels of LOH/MSOH.?? Switching Element.?? Insertion of voice and data channels of LOH/MSOH.?? Insertion of LOH/MSOH.?? Insertion of voice and data channels of SOH/RSOH.?? Multiplexing to stream STS 48/STM 16.?? Generation of SOH/ROSH.?? Insertion of A1, A2, J0.?? OAM and Configuration.?? Microprocessor Interface.?? Serial Interface.?? Add/Drop Streams. This architecture proposes the use of a data bus of 32 bits in the input of the frame alignment. This supposes the previous use of an element that carries out the conversion of the serial stream STS-48/STM-16 ( Mbps) to a parallel stream of 32 bits (77.76 MHz). This bus is used in the first three blocks of the architecture, being the third the one that carries out the division in four buses of 8 bits, transporting each one of them a stream STS-12/STM-4. An inverse process is carried out in the transmission section. The streams of lower order, that will be extracted/inserted, use an 8 bits data bus. This device can be configured to only carry out the regeneration function. In this operation way, it is only processed/generated the overhead section/regeneration and the rest of the modules work in transparent way Frame Alignment When the SONET/SDH stream enters to this block, it is supposed that an external device has already done clock recovery. The objectives of this block are:?? Alignment of the streams by means of the synchronization bytes A1 and A2, incoming from the signals STS-48/STM-16.?? Detection of J0 trace.?? Calculation of B1 parity byte, corresponding to the SOH/RSOH.?? Alarm detection.?? Descrambling. The function of alignment of the frame is important because it is very probable that the bytes are shifted some bits and do not correspond to those of an exactly SONET/SDH frame. On the other hand, the even parity calculation of the section/regeneration layer reports the detected errors during the transmission of the SONET/SDH frame Detection of Alarms In this sub block the main regenerator section alarms are detected to the SONET/SDH stream like: loss of signal (LOS), out of frame (OOF), loss of frame (LOF), loss of clock (LOC) Descrambler This sub block carries out the descrambling on the SONET/SDH frame, excluding the first line of the SOH/RSOH. This process is carried out using a generating polynomial according to [2] (see Fig. 5) Processing of SOH/RSOH This block carries out the following functions:?? To compare the B1 byte calculated previously, with the B1 byte of the incoming frame, for error control.?? To provide an output pulse that indicates the qualification of the alarm AIS-L, this pulse will be active, when a LOS, LOF or a signal provided by the microprocessor is detected.

4 Fig. 5 Fig. 5 System Architecture?? To process the J0 byte to determine if the appearance is stable or unstable or if it existed inequality or equality (mismatch or match) in the appearance of J0.?? The J0 byte can be in 6 different modes Demultiplexing to STS 12/STM 4 Streams This block will be demultiplexing of the incoming signal in four signals STS 12/STM 4. The input data bus of 32 bits is demultiplexed in four buses of 8 bits, where each one corresponds to an STS 12/STM 4stream (See Fig. 5) Extraction of Voice and Data Channels of SOH/RSOH This block carries out the extraction of the voice channel E1, the voice/data channel F1 and the data channels D1, D2 and D3. The information contained in these bytes is transmitted to the OAM module, which takes charge of their administration. It is important to emphasize that although this process is carried out in the four streams STS-12/STM-4, only the bytes extracted in the first one are valid (this process also occurs in 3.5, 3.6, 3.8 and 3.10). See Fig Processing of LOH/MSOH This block consists of four sub blocks. Each one corresponds to one STS-12/STM-4 stream. It is necessary to emphasize that only in the first stream the K1, K2, S1, M0/M1 bytes are processed; while the B2 byte is processed in all the streams. This block has the following functions:?? B2 Processing. This sub block calculates the even parity of each stream. The B2 bytes are extracted and compared with the calculation of the parity that was carried out in the previous frame to obtain the number of detected errors in the transmission. The sum of the errors on all the valid streams is stored in a register.?? K1, K2 Processing. These bytes are extracted and transmitted to the OAM module to manage the APS (Automatic Protection Switch).?? Processing of the Byte S1. This sub block extracts this byte and sends it to the OAM block. This byte indicates the state of the clock and the synchronization of the network.?? Extraction of the M1 Byte. This byte comes from the previous line element and it contains the number of detected errors in the previous transmitted frame. This is made with the purpose of taking the pertinent

5 measures in case the number of errors is bigger than the one allowed (see Fig. 5) Extraction of Voice and Data Channels of LOH/MSOH This block extracts the voice channel E2 and the data channels D4-D12. The information contained in these bytes is transmitted to the OAM module, which takes charge of their administration (see Fig. 5) Switching Element This block accomplishes the extraction/insertion of the SONET/SDH streams. This module has four ports for the extraction and four ports for the insertions, which are 8 bit buses, each one. For each one of these ports it can be extracted/inserted a stream of the type STS-1, STS- 3c/STM-1 or STS-12c/STM-4c. To be able to carry out the extraction/insertion of the streams of lower order, a configuration register is needed and it contains the necessary information on the streams that will be extracted/inserted. The input to this module is the four streams STS-12/STM-4. With the information contained in the configuration register, the signals of low order are extracted/inserted to each one of the incoming streams. For each one extracted stream another of same rate should be inserted. Outputs of this module are four STS-12/STM-4 streams again. The extraction and insertion streams are passed through a bus of 8 bits independently of the frame type. For this, the bus can work at different rates. Because each insertion stream was generated with a different clock, it is necessary to use a MSA - Multiplex Section Adaptation-, which works with two different clocks (see Fig. 5) Insertion of Voice and Data Channels of LOH/MSOH This block inserts of the voice channel E2 and the channels of data D4-D12. The information that is inserted in these channels comes from the OAM module, which carries out the insertion by means of a register, which contains information coming from the serial interface or from the parallel interface manipulated by the microprocessor (see Fig. 5) Insertion of LOH/MSOH This block consists of four sub blocks, which are used to process each STS-12/STM-4 stream. Bytes K1, K2, S1, M0/M1 are inserted only in the first stream; while the B2 byte is inserted in all the streams. This block has the following functions:?? B2 insertion. To calculate the even parity of each stream without SOH/RSOH. This value is inserted in the following frame.?? K1, K2 insertion. These bytes are inserted from the OAM module and take the information corresponding to the APS (Automatic Protection Switch).?? Insertion of S1. To insert this byte from the OAM block and indicates the state of the clock and the synchronization of the network.?? Insertion of the M1 byte. This byte comes from de OAM module and contains the number of errors of the received frame (see Fig. 5) Insertion of Voice and Data Channels of SOH/RSOH This block carries out the insertion of the voice channel E1, of the voice/data channel F1 and of the data channels D1, D2 and D3. The information contained in these channels comes from the OAM module, which carries out the insertion by means of a register, which contains information coming from the serial interface or from the microprocessor (see Fig. 5) Multiplexing to STS 48/STM 16 Stream This block will multiplex the incoming four STS 12/STM 4 signals in STS 48/STM 16 stream. The output bus of this block has a length of 32 bits (see Fig. 5) Generation of SOH/RSOH This block carries out the following functions:?? Insertion of the B1 byte corresponding to the previous frame.?? Scrambling of the SONET/SDH frame excluding the first row of the SOH/RSOH (see Fig. 5) Insertion of A1, A2, J0 In this block the bytes A1, A2, J0 are inserted for the frame alignment. J0 comes from the OAM module and it can be configured of six different ways. Once the frame is complete, the calculation of the even parity (B1) is carried out and it is the value inserted according to section 3.12, for the next frame (see Fig. 5) OAM and Configuration

6 It carries out the operation, administration and maintenance functions of the system. This block works with some modules in order to update the diverse registers of the system. Also, it has other functions, which are:?? To supervise the data and the alarms that can be presented in the processing of the frames.?? To supervise the processing of the bytes K1 and K2 for the automatic protection switching (APS).?? To manage the M0/M1 byte, for the exchange of information of control of errors with another network element.?? To manage the synchronization byte S1.?? To configure the operation mode of the J0 byte for its extraction / insertion.?? To carry out the configuration in the way of insert of the voice and data channels.?? To manage the configuration of the extraction/insertion streams of the device (see Fig. 5) Microprocessor Interface This block serves as interface between the ADM and a microprocessor of 8/16 bits. This interface allows the communication among the elements of the system, namely, with the OAM and the microprocessor, in order to carry out diverse functions like the attention of the interruptions generated by the device. These interruptions could be in a hierarchical order and they indicate diverse important events inside the processing, such as detection of beginning of a frame, loss of frame, detection/generation of alarms, etc (see Fig. 5) Serial Interface This block is a serial port of the ADM for communication with the exterior. By means of this port can be carried out the extraction/insertion of the voice and data channels corresponding to the SOH/RSOH and LOH/MSOH. Also the communication between two network elements for the byte M0/M1 can be accomplished by means of this interface (Fig. 5) Add/Drop Streams In this block the adaptation of the extraction/insertion streams is made. This process is applied in each one of the four input and output ports, being its rate according to the type of extraction/insertion streams. The operations carried out for the insertion correspond to those described in the following blocks:?? 3.1 Frame alignment.?? 3.2 Processing of SOH/ROSH.?? 3.4 Extraction of voice and data channels of SOH/RSOH.?? 3.5 Processing of LOH/MSOH.?? 3.6 Extraction of voice and data channels of LOH/MSOH. In the same way the operations for the extraction of streams are carried out like in the blocks:?? 3.8 Insertion of voice and data channels of LOH/MSOH.?? 3.9 Insertion of LOH/MSOH.?? 3.10 Insertion of voice and data channels of SOH/RSOH.?? 3.12 Generation of SOH/ROSH.?? 3.13 Insertion of A1, A2, J0 (see Fig. 5). 4. VERIFICATION In order to be able to carry out a verification of the device ADM, it has loopbacks that allow the manipulation of data stream on certain blocks. In this way, it is possible to move the data through specific areas that are desired to verification. The verification plan proposed for the STS-48/STM- 16ADM can be divided into the general verification plan and the verification plan by blocks. The general verification plan contains the following tests:?? Insertion of a STS-48c/STM-16c stream, to verify the operation of the ADM as regenerator.?? Operation without extraction and insertion streams of lower order, in order to check that the incoming stream STS-48/STM-16 is similar to the outgoing one.?? Verification tests in specific blocks by means of loopback functions.?? Operation of the device under diverse combinations of streams, using different valid rates (for the extraction/insertion). The verification plan for the blocks is the following Frame Alignment Verification?? Detection of Alarms: In the detection of alarms a SONET/SDH frame is introduced with the purpose of being able to detect OOF (out of frame), LOF (lost of frame), LOS (lost of signal), LOC (lost of clock), etc.?? Frame Alignment: In this sub block, it is verified that the frame is aligned, by means the A1, A2 bytes. This block verifies the indication of the byte J0. Besides, it carries out the verification of the calculation of B1.?? Descrambler: The verification is carried out making this operation on a frame, for later to accomplish the

7 inverse operation and finally to compare the output frame with the input frame Processing of SOH/RSOH Verification?? SOH/RSOH: For this block, it is verified that: J0 has been detected, the processing of the byte B1 begins with the values by default after the reset, the bit and block counters carry out the function of accumulating the errors. It is also verified the rollover (overflow) in the counters Demultiplexing to STS 12/STM 4 Streams Verification?? Demultiplexing: For this block they are carried out the tests to guarantee a correct operation, being aided of the inverse operation (multiplexing), to verify that it is fulfilled the SONET/SDH multiplexing hierarchy on the input and output frame Extraction of SOH/RSOH Voice and Data Channels Verification?? Extraction: For this block, it is verified the correct extraction of the communication bytes (D1-D3), E1 and F Processing of LOH/MSOH Verification?? LOH/MSOH: The verification for this sub block is the corresponding to the line/multiplex layer, where the filtering of the K1 and K2 (APS) bytes is verified, the filtering of the S1 byte and the extraction of the M1 byte must be stored in a register.?? Processing of B2, M1: In this sub block is carried out the verification of the calculation of the even parity on the previous frame excepting the SOH/RSOH and this way to check the comparison with the byte B2 to be able to detect the number of errors. In this block the detection of the number of bits errors is also verified by frame, bits errors during one second, errors for block, and block errors in one second. In this block also is verified that the byte M1 accumulates the errors detected by the byte B Extraction of Voice and Data Channels of LOH/MSOH Verification?? It must be verified the correct extraction of the voice channel E2 and the data channels D4-D Switching Element Verification?? Switching Element. To verify that extracted/inserted frames correspond to those specified in the configuration register.?? Adaptation of Clocks. To verify the correct synchronization between the main clock and the clocks of the extraction/insertion streams Insertion of Voice and Data Channels of LOH/MSOH Verification?? It must be verified the correct insertion of the voice channel E2 and the data channels D4-D Insertion of LOH/MSOH Verification?? LOH/MSOH: The verification for this block is the corresponding to the insertion of the bytes of the line/multiplexing layer (B2, S1, M1, K1 and K2).?? Byte B2: It must be verified that the calculation of the even parity of the frame without SOH/RSOH is correct Insertion of Voice and Data Channels of SOH/RSOH Verification?? It must be verified the correct insertion of the voice channel E1, the voice/data channel F1 and the data channels D1 D Multiplexing to STS 48/STM 16 Stream Verification?? Multiplexing: In the block of multiplexing, the tests are carried out to verify that the multiplexing of the different streams is correct Generation of SOH/RSOH Verification?? Scrambler: In the scrambler sub block, the verification is carried out making this operation on a frame, for later to carry out the inverse operation and this way to compare the outgoing frame with the incoming frame.?? Insertion of B1: This section verifies the correct insertion of the byte B1 corresponding to the last frame Insertion of A1, A2, J0 Verification?? Insertion of A1, A2, J0: In this block, it is verified that A1, A2, J0 are inserted correctly, as well as that the byte J0 corresponds to the operation mode given by the module OAM.

8 ?? Calculation of B1. Besides, it must verify that the calculation of the even parity over the whole frame is made correctly OAM and Configuration Verification?? Alarms. This sub block verifies the alarm signals detecting. As well as it must be verified that this section is able to interpret the bytes K1 and K2 for the automatic switching of protection (APS).?? M0/M1 and S1 Bytes. It is verified that the extraction/insertion of the M0/M1 byte corresponds to the correct network element. Also it must verify that the synchronization byte S1 is the desired.?? J0 byte. It is verified that the extraction/insertion of the J0 byte corresponds to the configured operation mode.?? Voice and Data Channels. It is verified that the bytes correspond with the configured voice and data channels.?? Configuration. It is verified that the extraction/insertion streams are the given by the configuration register Microprocessor Interface Verification?? It is verified that the data inserted through this interface is read correctly Serial Interface Verification?? It is verified that the data inserted through this interface is read correctly Add/Drop Module Verification?? It must verify that the add/drop streams are correct. Due to that this block is formed by previous specified blocks, the tests are the same for each one of them. 5. CONCLUSIONS The specification, design and verification of a highly integrated network element, e.g. an ADM with hundreds thousands gates, is today a big challenge. The proposed architecture for the ADM is focused on SONET STS-48/SDH STM-16 streams (2.5Gbps). It reuses some components, which were designed and tested in our Center. This architecture has been designed with techniques to allow an exhaustive testing process. It can be considered integrated of two main subsystems and the configuration and control module. It has the capability to extract/insert a combination of four SONET/SDH streams of the type STS-1, STS- 3c/STM-1, STS-12c/STM-4c. The first subsystem is the reception part and it carried out the decomposing of the incoming signal (STS- 48/STM-16) in four signals STS-12/STM-4. Each one of these signals is processed in order to determine if it is a valid stream that can be extracted, or if it is necessary to carry out an additional demultiplexing. The same process is carried out with the signals of lower order that go arising. The second subsystem of the device is the transmission part. In this direction, the process carries out a multiplexing of the valid streams, which build a signal STS-48/STM-16. The ADM has an interface for a microprocessor of 8/16 bits, which will carry out the control on the OAM functions of the system. 6. REFERENCES [1] American National Standard for telecommunications, Digital Hierarchy Optical Interface rates and formats specification, ANSI T1.105, [2] International Telecommunication Union, ITU T G.707 Network Node Interface for the Digital Synchronous Hierarchy, March 1996 [3] International Telecommunication Union, ITU T G.780 Vocabulary of terms for synchronous digital hierarchy (SDH) networks and equipment, June 1999 [4] Ming Chwan Chow, Understanding SONET/SDH Standards and Applications, 1995 [5] Goralski Walter, SONET A Guide to Synchronous Optical Network, 1997 [6] A.Redondo, J.Maldonado, L.Aburto, S.Medina, D.Torres y M.E.Guzmán, Desarrollo de una librería básica de componentes para el diseño de elementos de red SDH/SONET para señales STM 1/STS 3c/3xSTS 1, ROC&C [7] Aburto, L., POH Processor, Master s Thesis in development, CINVESTAV of IPN Guadalajara, Mex. [8] Aguirre, C., RSOH Processor, Master s Thesis in development, CINVESTAV of IPN Guadalajara, Mex. [9] Medina, S., Frame Alignment, Master s Thesis in development, CINVESTAV of IPN Guadalajara, Mex. [10] Maldonado, J., Pointer Tracker Processor, Master s Thesis in development, CINVESTAV of IPN Guadalajara, Mex. [11] Nanni, H., Multiplex Section Adaptation, Master s Thesis in development, CINVESTAV of IPN Guadalajara, Mex. [12] Redondo, A., MSOH Processor, Master s Thesis in development, CINVESTAV of IPN Guadalajara, Mex. [13] [14]