Cortex -M3. Technical Reference Manual. Revision: r1p1. Copyright 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337E

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2 Cortex-M3 Technical Reference Manual Copyright 2005, 2006 ARM Limited. All rights reserved. Release Information Change History Date Issue Confidentiality Change 15 December 2005 A Confidential First Release 13 January 2006 B Non-Confidential Confidentiality status amended 10 May 2006 C Non-Confidential First Release for r1p0 27 September 2006 D Non-Confidential First Release for r1p1 13 June 2007 E Non-Confidential Minor update with no technical changes Proprietary Notice Words and logos marked with or are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM Limited in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product. Confidentiality Status This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to. Product Status The information in this document is Final (information on a developed product). Web Address ii Copyright 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337E

3 Contents Cortex-M3 Technical Reference Manual Preface About this manual... xviii Feedback... xxiii Chapter 1 Chapter 2 Introduction 1.1 About the processor Components, hierarchy, and implementation Configurable options Execution pipeline stages Prefetch Unit Branch target forwarding Store buffers Instruction set summary Product revisions Programmer s Model 2.1 About the programmer s model Privileged access and user access Registers Data types Memory formats Instruction set ARM DDI 0337E Copyright 2005, 2006 ARM Limited. All rights reserved. iii

4 Contents Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 System Control 3.1 Summary of processor registers Memory Map 4.1 About the memory map Bit-banding ROM memory table Exceptions 5.1 About the exception model Exception types Exception priority Privilege and stacks Pre-emption Tail-chaining Late-arriving Exit Resets Exception control transfer Setting up multiple stacks Abort model Activation levels Flowcharts Clocking and Resets 6.1 Clocking Resets Cortex-M3 reset modes Power Management 7.1 About power management System power management Nested Vectored Interrupt Controller 8.1 About the NVIC NVIC programmer s model Level versus pulse interrupts Memory Protection Unit 9.1 About the MPU MPU programmer s model MPU access permissions MPU aborts Updating an MPU region Interrupts and updating the MPU iv Copyright 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337E

5 Contents Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Core Debug 10.1 About core debug Core debug registers Core debug access example Using application registers in core debug System Debug 11.1 About system debug System debug access System debug programmer s model FPB DWT ITM AHB-AP Debug Port 12.1 About the DP Trace Port Interface Unit 13.1 About the TPIU TPIU registers Serial wire output connection Bus Interface 14.1 About bus interfaces AMBA 3 compliance ICode bus interface DCode bus interface System interface Unifying the code buses External private peripheral interface Access alignment Unaligned accesses that cross regions Bit-band accesses Write buffer Memory attributes AHB timing characteristics Embedded Trace Macrocell 15.1 About the ETM Data tracing ETM resources Trace output ETM architecture ETM programmer s model ARM DDI 0337E Copyright 2005, 2006 ARM Limited. All rights reserved. v

6 Contents Chapter 16 Chapter 17 Chapter 18 Chapter 19 Appendix A Embedded Trace Macrocell Interface 16.1 About the ETM interface CPU ETM interface port descriptions Branch status interface AHB Trace Macrocell Interface 17.1 About the AHB trace macrocell interface CPU AHB trace macrocell interface port descriptions Instruction Timing 18.1 About instruction timing Processor instruction timings Load-store timings AC Characteristics 19.1 Processor timing parameters Processor timing parameters Signal Descriptions A.1 Clocks... A-2 A.2 Resets... A-3 A.3 Miscellaneous... A-4 A.4 Interrupt interface... A-6 A.5 ICode interface... A-7 A.6 DCode interface... A-8 A.7 System bus interface... A-9 A.8 Private Peripheral Bus interface... A-10 A.9 ITM interface... A-11 A.10 AHB-AP interface... A-12 A.11 ETM interface... A-13 A.12 AHB Trace Macrocell interface... A-15 A.13 Test interface... A-16 Glossary vi Copyright 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337E

7 List of Tables Cortex-M3 Technical Reference Manual Change History... ii Table bit Cortex-M3 instruction summary Table bit Cortex-M3 instruction summary Table 2-1 Application Program Status Register bit assignments Table 2-2 Interrupt Program Status Register bit assignments Table 2-3 Bit functions of the EPSR Table 2-4 Nonsupported Thumb instructions Table 2-5 Supported Thumb-2 instructions Table 3-1 NVIC registers Table 3-2 Core debug registers Table 3-3 Flash patch register summary Table 3-4 DWT register summary Table 3-5 ITM register summary Table 3-6 AHB-AP register summary Table 3-7 Summary of Debug interface port registers Table 3-8 MPU registers Table 3-9 TPIU registers Table 3-10 ETM registers Table 4-1 Memory interfaces Table 4-2 Memory region permissions Table 4-3 ROM table Table 5-1 Exception types Table 5-2 Priority-based actions of exceptions ARM DDI 0337E Copyright 2005, 2006 ARM Limited. All rights reserved. vii

8 List of Tables Table 5-3 Priority grouping Table 5-4 Exception entry steps Table 5-5 Exception exit steps Table 5-6 Exception return behavior Table 5-7 Reset actions Table 5-8 Reset boot-up behavior Table 5-9 Transferring to exception processing Table 5-10 Faults Table 5-11 Debug faults Table 5-12 Fault status and fault address registers Table 5-13 Privilege and stack of different activation levels Table 5-14 Exception transitions Table 5-15 Exception subtype transitions Table 6-1 Cortex-M3 processor clocks Table 6-2 Cortex-M3 macrocell clocks Table 6-3 Reset inputs Table 6-4 Reset modes Table 7-1 Supported sleep modes Table 8-1 NVIC registers Table 8-2 Interrupt Controller Type Register bit assignments Table 8-3 SysTick Control and Status Register bit assignments Table 8-4 SysTick Reload Value Register bit assignments Table 8-5 SysTick Current Value Register bit assignments Table 8-6 SysTick Calibration Value Register bit assignments Table 8-7 Interrupt Set-Enable Register bit assignments Table 8-8 Interrupt Clear-Enable Register bit assignments Table 8-9 Interrupt Set-Pending Register bit assignments Table 8-10 Interrupt Clear-Pending Registers bit assignments Table 8-11 Active Bit Register bit assignments Table 8-12 Interrupt Priority Registers 0-31 bit assignments Table 8-13 CPUID Base Register bit assignments Table 8-14 Interrupt Control State Register bit assignments Table 8-15 Vector Table Offset Register bit assignments Table 8-16 Application Interrupt and Reset Control Register bit assignments Table 8-17 System Control Register bit assignments Table 8-18 Configuration Control Register bit assignments Table 8-19 System Handler Priority Registers bit assignments Table 8-20 System Handler Control and State Register bit assignments Table 8-21 Memory Manage Fault Status Register bit assignments Table 8-22 Bus Fault Status Register bit assignments Table 8-23 Usage Fault Status Register bit assignments Table 8-24 Hard Fault Status Register bit assignments Table 8-25 Debug Fault Status Register bit assignments Table 8-26 Memory Manage Fault Address Register bit assignments Table 8-27 Bus Fault Address Register bit assignments Table 8-28 Auxiliary Fault Status Register bit assignments Table 8-29 Software Trigger Interrupt Register bit assignments viii Copyright 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337E

9 List of Tables Table 9-1 MPU registers Table 9-2 MPU Type Register bit assignments Table 9-3 MPU Control Register bit assignments Table 9-4 MPU Region Number Register bit assignments Table 9-5 MPU Region Base Address Register bit assignments Table 9-6 MPU Region Attribute and Size Register bit assignments Table 9-7 MPU protection region size field Table 9-8 TEX, C, B encoding Table 9-9 Cache policy for memory attribute encoding Table 9-10 AP encoding Table 9-11 XN encoding Table 10-1 Core debug registers Table 10-2 Debug Halting Control and Status Register Table 10-3 Debug Core Register Selector Register Table 10-4 Debug Exception and Monitor Control Register Table 10-5 Application registers for use in core debug Table 11-1 FPB register summary Table 11-2 Flash Patch Control Register bit assignments Table 11-3 COMP mapping Table 11-4 Flash Patch Remap Register bit assignments Table 11-5 Flash Patch Comparator Registers bit assignments Table 11-6 DWT register summary Table 11-7 DWT Control Register bit assignments Table 11-8 DWT Current PC Sampler Cycle Count Register bit assignments Table 11-9 DWT CPI Count Register bit assignments Table DWT Exception Overhead Count Register bit assignments Table DWT Sleep Count Register bit assignments Table DWT LSU Count Register bit assignments Table DWT Fold Count Register bit assignments Table DWT Program Counter Sample Register bit assignments Table DWT Comparator Registers 0-3 bit assignments Table DWT Mask Registers 0-3 bit assignments Table Bit functions of DWT Function Registers Table Settings for DWT Function Registers Table ITM register summary Table ITM Trace Enable Register bit assignments Table ITM Trace Privilege Register bit assignments Table ITM Trace Control Register bit assignments Table ITM Integration Write Register bit assignments Table ITM Integration Read Register bit assignments Table ITM Integration Mode Control Register bit assignments Table ITM Lock Access Register bit assignments Table ITM Lock Status Register bit assignments Table AHB-AP register summary Table AHB-AP Control and Status Word Register bit assignments Table AHB-AP Transfer Address Register bit assignments Table AHB-AP Data Read/Write Register bit assignments ARM DDI 0337E Copyright 2005, 2006 ARM Limited. All rights reserved. ix

10 List of Tables Table AHB-AP Banked Data Register bit assignments Table AHB-AP Debug ROM Address Register bit assignments Table AHB-AP ID Register bit assignments Table 13-1 Trace out port signals Table 13-2 ATB port signals Table 13-3 Miscellaneous configuration inputs Table 13-4 TPIU registers Table 13-5 Async Clock Prescaler Register bit assignments Table 13-6 Selected Pin Protocol Register bit assignments Table 13-7 Formatter and Flush Status Register bit assignments Table 13-8 Formatter and Flush Control Register bit assignments Table 13-9 Integration Test Register-ITATBCTR2 bit assignments Table Integration Test Register-ITATBCTR0 bit assignments Table 14-1 Instruction fetches Table 14-2 Bus mapper unaligned accesses Table 14-3 Memory attributes Table 14-4 Interface timing characteristics Table 15-1 ETM core interface inputs and outputs Table 15-2 Miscellaneous configuration inputs Table 15-3 Trace port signals Table 15-4 Other signals Table 15-5 Clocks and resets Table 15-6 APB interface signals Table 15-7 Cortex-M3 resources Table 15-8 Exception tracing mapping Table 15-9 ETM registers Table 16-1 ETM interface ports Table 16-2 Branch status signal function Table 16-3 Example of an opcode sequence Table 17-1 AHB interface ports Table 18-1 Instruction timings Table 19-1 Miscellaneous input ports timing parameters Table 19-2 Interrupt input ports timing parameters Table 19-3 AHB input ports timing parameters Table 19-4 PPB input port timing parameters Table 19-5 Debug input ports timing parameters Table 19-6 Test input ports timing parameters Table 19-7 ETM input port timing parameters Table 19-8 Miscellaneous output ports timing parameters Table 19-9 AHB output ports timing parameters Table PPB output ports timing parameters Table Debug interface output ports timing parameters Table ETM interface output ports timing parameters Table HTM interface output ports timing parameters Table Test output ports timing parameters Table A-1 Clock signals... A-2 Table A-2 Reset signals... A-3 x Copyright 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337E

11 List of Tables Table A-3 Miscellaneous signals... A-4 Table A-4 Interrupt interface... A-6 Table A-5 ICode interface... A-7 Table A-6 DCode interface... A-8 Table A-7 System bus interface... A-9 Table A-8 Private Peripheral Bus interface... A-10 Table A-9 ITM interface... A-11 Table A-10 AHB-AP interface... A-12 Table A-11 ETM interface... A-13 Table A-12 HTM interface... A-15 Table A-13 Test interface... A-16 ARM DDI 0337E Copyright 2005, 2006 ARM Limited. All rights reserved. xi

13 List of Figures Cortex-M3 Technical Reference Manual Key to timing diagram conventions... xxi Figure 1-1 Cortex-M3 block diagram Figure 1-2 Cortex-M3 pipeline stages Figure 2-1 Processor register set Figure 2-2 Application Program Status Register bit assignments Figure 2-3 Interrupt Program Status Register bit assignments Figure 2-4 Execution Program Status Register Figure 2-5 Little-endian and big-endian memory formats Figure 4-1 Processor memory map Figure 4-2 Bit-band mapping Figure 5-1 Stack contents after a pre-emption Figure 5-2 Exception entry timing Figure 5-3 Tail-chaining timing Figure 5-4 Late-arriving exception timing Figure 5-5 Exception exit timing Figure 5-6 Interrupt handling flowchart Figure 5-7 Pre-emption flowchart Figure 5-8 Return from interrupt flowchart Figure 6-1 Reset signals Figure 6-2 Power-on reset Figure 6-3 Internal reset synchronization Figure 7-1 SLEEPING power control example Figure 7-2 SLEEPDEEP power control example ARM DDI 0337E Copyright 2005, 2006 ARM Limited. All rights reserved. xiii

14 List of Figures Figure 8-1 Interrupt Controller Type Register bit assignments Figure 8-2 SysTick Control and Status Register bit assignments Figure 8-3 SysTick Reload Value Register bit assignments Figure 8-4 SysTick Current Value Register bit assignments Figure 8-5 SysTick Calibration Value Register bit assignments Figure 8-6 Interrupt Priority Registers 0-31 bit assignments Figure 8-7 CPUID Base Register bit assignments Figure 8-8 Interrupt Control State Register bit assignments Figure 8-9 Vector Table Offset Register bit assignments Figure 8-10 Application Interrupt and Reset Control Register bit assignments Figure 8-11 System Control Register bit assignments Figure 8-12 Configuration Control Register bit assignments Figure 8-13 System Handler Priority Registers bit assignments Figure 8-14 System Handler Control and State Register bit assignments Figure 8-15 Configurable Fault Status Registers bit assignments Figure 8-16 Memory Manage Fault Register bit assignments Figure 8-17 Bus Fault Status Register bit assignments Figure 8-18 Usage Fault Status Register bit assignments Figure 8-19 Hard Fault Status Register bit assignments Figure 8-20 Debug Fault Status Register bit assignments Figure 8-21 Software Trigger Interrupt Register bit assignments Figure 9-1 MPU Type Register bit assignments Figure 9-2 MPU Control Register bit assignments Figure 9-3 MPU Region Number Register bit assignments Figure 9-4 MPU Region Base Address Register bit assignments Figure 9-5 MPU Region Attribute and Size Register bit assignments Figure 10-1 Debug Halting Control and Status Register format Figure 10-2 Debug Core Register Selector Register format Figure 10-3 Debug Exception and Monitor Control Register format Figure 11-1 System debug access block diagram Figure 11-2 Flash Patch Control Register bit assignments Figure 11-3 Flash Patch Remap Register bit assignments Figure 11-4 Flash Patch Comparator Registers bit assignments Figure 11-5 DWT Control Register bit assignments Figure 11-6 DWT CPI Count Register bit assignments Figure 11-7 DWT Exception Overhead Count Register bit assignments Figure 11-8 DWT Sleep Count Register bit assignments Figure 11-9 DWT LSU Count Register bit assignments Figure DWT Fold Count Register bit assignments Figure DWT Mask Registers 0-3 bit assignments Figure DWT Function Registers 0-3 bit assignments Figure ITM Trace Privilege Register bit assignments Figure ITM Trace Control Register bit assignments Figure ITM Integration Write Register bit assignments Figure ITM Integration Read Register bit assignments Figure ITM Integration Mode Control bit assignments Figure ITM Lock Status Register bit assignments xiv Copyright 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337E

15 List of Figures Figure AHB-AP Control and Status Word Register Figure AHB-AP ID Register Figure 13-1 Block diagram of the TPIU (non-etm version) Figure 13-2 Block diagram of the TPIU (ETM version) Figure 13-3 Supported Sync Port Size Register bit assignments Figure 13-4 Async Clock Prescaler Register bit assignments Figure 13-5 Selected Pin Protocol Register bit assignments Figure 13-6 Formatter and Flush Status Register bit assignments Figure 13-7 Formatter and Flush Control Register bit assignments Figure 13-8 Integration Test Register-ITATBCTR2 bit assignments Figure 13-9 Integration Test Register-ITATBCTR0 bit assignments Figure Dedicated pin used for TRACESWO Figure SWO shared with TRACEPORT Figure SWO shared with JTAG-TDO Figure 14-1 ICode/DCode multiplexer Figure 15-1 ETM block diagram Figure 15-2 Return from exception packet encoding Figure 15-3 Exception encoding for branch packet Figure 16-1 Conditional branch backwards not taken Figure 16-2 Conditional branch backwards taken Figure 16-3 Conditional branch forwards not taken Figure 16-4 Conditional branch forwards taken Figure 16-5 Unconditional branch without pipeline stalls Figure 16-6 Unconditional branch with pipeline stalls Figure 16-7 Unconditional branch in execute aligned Figure 16-8 Unconditional branch in execute unaligned Figure 16-9 Example of an opcode sequence ARM DDI 0337E Copyright 2005, 2006 ARM Limited. All rights reserved. xv

17 Preface This preface introduces the Cortex-M3 Technical Reference Manual (TRM). It contains the following sections: About this manual on page xviii Feedback on page xxiii. ARM DDI 0337E Copyright 2005, 2006 ARM Limited. All rights reserved. xvii

18 Preface About this manual This is the TRM for the Cortex-M3 processor. Product revision status The rnpn identifier indicates the revision status of the product described in this manual, where: rn Identifies the major revision of the product. pn Identifies the minor revision or modification status of the product. Intended audience This manual is written to help system designers, system integrators, and verification engineers who are implementing a System-on-Chip (SoC) device based on the Cortex-M3 processor. Using this manual This manual is organized into the following chapters: Chapter 1 Introduction Read this chapter to learn about the components of the processor, and about the processor instruction set. Chapter 2 Programmer s Model Read this chapter to learn about the processor register set, modes of operation, and other information for programming the processor. Chapter 3 System Control Read this chapter to learn about the registers and programmer s model for system control. Chapter 4 Memory Map Read this chapter to learn about the processor memory map and bit-banding feature. Chapter 5 Exceptions Read this chapter to learn about the processor exception model. Chapter 6 Clocking and Resets Read this chapter to learn about the processor clocking and resets. xviii Copyright 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337E

19 Preface Chapter 7 Power Management Read this chapter to learn about the processor power management and power saving. Chapter 8 Nested Vectored Interrupt Controller Read this chapter to learn about the processor interrupt processing and control. Chapter 9 Memory Protection Unit Read this chapter to learn about the processor Memory Protection Unit (MPU). Chapter 10 Core Debug Read this chapter to learn about debugging and testing the processor core. Chapter 11 System Debug Read this chapter to learn about the processor system debug components. Chapter 12 Debug Port Read this chapter to learn about the processor debug port, and the Serial Wire JTAG Debug Port (SWJ-DP) and Serial Wire Debug Port (SW-DP). Chapter 13 Trace Port Interface Unit Read this chapter to learn about the processor Trace Port Interface Unit (TPIU). Chapter 14 Bus Interface Read this chapter to learn about the processor bus interfaces. Chapter 15 Embedded Trace Macrocell Read this chapter to learn about the processor Embedded Trace Macrocell (ETM). Chapter 16 Embedded Trace Macrocell Interface Read this chapter to learn about the processor ETM interface. Chapter 17 AHB Trace Macrocell Interface Read this chapter to learn about the processor Advanced High-performance Bus (AHB) trace macrocell interface. Chapter 18 Instruction Timing Read this chapter to learn about the processor instruction timing and clock cycles. ARM DDI 0337E Copyright 2005, 2006 ARM Limited. All rights reserved. xix

20 Preface Chapter 19 AC Characteristics Read this chapter to learn about the processor ac characteristics. Appendix A Signal Descriptions Read this appendix for a summary of processor signals. Conventions Conventions that this manual can use are described in: Typographical Timing diagrams on page xxi Signals on page xxi Numbering on page xxii. Typographical The typographical conventions are: italic bold monospace monospace monospace italic monospace bold Highlights important notes, introduces special terminology, denotes internal cross-references, and citations. Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate. Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code. Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name. Denotes arguments to monospace text where the argument is to be replaced by a specific value. Denotes language keywords when used outside example code. < and > Angle brackets enclose replaceable terms for assembler syntax where they appear in code or code fragments. They appear in normal font in running text. For example: MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2> The Opcode_2 value selects which register is accessed. xx Copyright 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337E

21 Preface Timing diagrams The figure named Key to timing diagram conventions explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams. Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation. Clock HIGH to LOW Transient HIGH/LOW to HIGH Bus stable Bus to high impedance Bus change High impedance to stable bus Key to timing diagram conventions Signals The signal conventions are: Signal level Lower-case n Prefix H Prefix P The level of an asserted signal depends on whether the signal is active-high or active-low. Asserted means HIGH for active-high signals and LOW for active-low signals. Denotes an active-low signal. Denotes Advanced High-performance Bus (AHB) signals. Denotes Advanced Peripheral Bus (APB) signals. ARM DDI 0337E Copyright 2005, 2006 ARM Limited. All rights reserved. xxi

22 Preface Numbering The numbering convention is: <size in bits>'<base><number> This is a Verilog method of abbreviating constant numbers. For example: 'h7b4 is an unsized hexadecimal value. 'o7654 is an unsized octal value. 8'd9 is an eight-bit wide decimal value of 9. 8'h3F is an eight-bit wide hexadecimal value of 0x3F. This is equivalent to b 'b1111 is an eight-bit wide binary value of b Further reading This section lists publications by ARM Limited and by third parties. ARM Limited periodically provides updates and corrections to its documentation. See for current errata sheets, addenda, and the ARM Limited Frequently Asked Questions list. ARM publications This manual contains information that is specific to the Cortex-M3 processor. See the following documents for other relevant information: ARM Architecture Reference Manual (ARM DDI 0100) ARM Architecture Reference Manual, Thumb-2 Supplement (ARM DDI 0308) ARMv7-M Architecture Reference Manual (ARM DDI 0403) ARM AMBA 3 AHB-Lite Protocol (v1.0) (ARM IHI 0033) ARM CoreSight Components Technical Reference Manual (ARM DDI 0314) ARM Debug Interface v5, Architecture Specification (ARM IHI 0031) ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0014). Other publications This section lists relevant documents published by third parties: IEEE Standard, Test Access Port and Boundary-Scan Architecture specification (JTAG). xxii Copyright 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337E

23 Preface Feedback ARM Limited welcomes feedback both on the Cortex-M3 processor, and on the documentation. Feedback on the Cortex-M3 processor If you have any comments or suggestions about this product, contact your supplier giving: the product name a concise explanation of your comments. Feedback on this manual If you have any comments on this manual, send to errata@arm.com giving: the title the number the page number(s) to which your comments refer a concise explanation of your comments. ARM Limited also welcomes general suggestions for additions and improvements. ARM DDI 0337E Copyright 2005, 2006 ARM Limited. All rights reserved. xxiii