CHEMICAL WET ETCHING OF SILICON WAFERS FROM A MIXTURE OF CONCENTRATED ACIDS

Transcription

1 Advanced Materials Research Vols (2011) pp Online available since 2011/Jun/30 at (2011) Trans Tech Publications, Switzerland doi: / CHEMICAL WET ETCHING OF SILICON WAFERS FROM A MIXTURE OF CONCENTRATED ACIDS M. R. Ismail 1, W. J. Basirun 2 Department of Chemistry, Faculty of Science, University of Malaya, Lembah Pantai, Kuala Lumpur 50603, Malaysia. E mail 1 : mo_riis@yahoo.ca; E mail 2 : wjeffreyb@yahoo.com KEYWORDS: Silicon warpage, Sub-surface damage, Wafer thinning, Wet etching ABSTRACT Warpage on the backside of silicon wafer after thinning process is examined. The thinning process includes back-grinding (BG) and wet chemical etching (WCE). Results of wafer warpage were compared to sub-surface damage from Transmission Electron Microscopy (TEM) analysis and showed that sub-surface damage on the backside of the silicon 100 would induce high wafer warpage, and reduced wafer strength. Further studies from surface roughness and topography of each surface finish is obtained by Atomic Force Microscopy (AFM) and SEM show that low surface roughness is in accordance with smooth surface condition, which comes after the wet etching process. INTRODUCTION Semiconductor industries are driving towards miniaturization, multifunctional and high density packages, especially for portable electronic devices. One of the important steps to achieve this is the silicon wafer thinning, which is the main subject of this paper. The key technology enabler of wafer thinning is the back-grinding process (BG) where the backside of the silicon wafer is mechanically grinded to the required thickness. This process is widely applied in assembly industries due to its low cost and time efficiency and remains as the most preferred thinning method for silicon wafers [1]. Despite the positive outlook, there is a negative aspect of mechanical grinding which is the presence of warp when the silicon is thinned down. Mechanical abrasion and heat during the BG process will induce damage on the wafer surface that can lead to crack propagation, growth and fracture [2]. It has been experimentally shown that the amount of silicon damage is closely related to the wafer warpage [3]. The warpage is not desirable for thin wafers and therefore it is important to further understand and control the surface damage from the grinding process. The increased wafer diameter over thickness ratio makes the wafers more sensitive to warpage [4]. As mentioned earlier, heat, which is produced from BG process can also lead to wafer warpage [5, 6]. Most conventional BG process use a two step method, which is the rough grinding and fine grinding [3, 8, 9]. The rough grinding is where a significant amount (around 90%) of silicon material is removed by this step. An abrasive grinding wheel, typically grit was used to rapidly thin the wafer, but this greatly damage the wafer sub-surface [3, 9]. The second step is the fine grinding process which uses utilizes abrasive wheel of typically grit, where the wafer is thinned down to the required thickness and to remove most of the damage from the rough grinding process. A cross section of the sub-surface damage due to mechanical BG described by the Hadamovsky model consists of a polysilicon zone at the top, followed by a cracked zone, a All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of TTP, (ID: /07/11,14:01:18)

2 1028 Advances in Materials and Processing Technologies II transition zone and a crystal dislocation zone at the bottom [7]. Measurements using Raman Spectroscopy gave a cross-sectional profile of the sub-surface which consists of an amorphous layer on top, followed by a polycrystalline layer, elastically strained crystalline layer and bulk crystalline silicon at the bottom [3]. Here cross sections of the wafers were taken using Transmission Electron Microscopy, to examine the effects of BG and Wet Chemical Etching (WCE) processes. This is important for checking the damage depth induced by them on the wafer backside surface. (WCE) is a simple method which can be performed on the wafers to reduce the surface roughness from the BG process. Among the chemicals which have been long used in the WCE process are KOH, Hydrofluoric acid (HF), Tetramethyl Ammonium Hydroxide (TMAH) and Ethylene Diamine Pyrocatechol (EDP), but improvements have been made in the chemical compositions and conditions of the WCE [10,11,13]. 2. EXPERIMENTAL METHODS Bare silicon wafers of 20 cm in diameter and mm thick with front surface with crystal orientation of <100> were used in this study. For the mechanical BG, of the rough grinding step, the abrasive diamond wheels with grit size mesh 320 were used, while the wheels with mesh 1500 grit size were employed in the fine grinding step. After the BG process, the wafers undergo the surface damage removal by chemical wet etching at a standard removal rate. The end thickness of wafers from BG process only was 185 µm while for wafers undergoing stress relief process was 150 µm. The grinding conditions are listed in Table 1. Grinding Parameter Coarse grinding Fine grinding Grit size Chuck speed [rpm] Spindle speed [rpm] Feed-rate [µm/s] Table 1 Grinding parameter used in the current study (machine model DISCO DFG8540) To completely remove the damage layer and to relieve stress of the wafers, WCE can be done on the grinded wafers. In this work, a combination of HNO 3, HF, H 2 SO 4 and H 3 PO 4 was used in the WCE process. The conditions for the WCE are tabulated in Table 2. Process parameter Chemical wet etch Chemicals HNO 3, HF, H 2 SO 4, H 3 PO 4 Etch rate [µm/s] 0.69 Method Spin etch Table 2 Stress relief process (WE) parameter (machine model SEZ 203 spin processor) The spin etch using the combination of acids was performed using SEZ Spin Processor. The surface roughness measurements were performed using Atomic Focus Microscopy (AFM) Nanoscope model D3000. Average surface roughness (R a ) was collected over the entire measured array and it was usually used as surface finish roughness parameter. For each sample, the results of surface finish are presented in the 3D view and roughness analysis showing surface topography of each sample. Damage depth characterizations for samples of both processes were done using FEI Tecnai F20 Transmission Electron Microscopy (TEM). Backside of each sample was deposited with 200 nm titanium (Ti) as a protective layer to check the thickness of the damage depth. The captured images were saved and the length of damage depth was measured using Digital Image Processing

3 Advanced Materials Research Vols System 2.6 (DIPS 2.6) software. The SEM instrument used was from Leica S 440 Scanning Electron Microscope. The measurement of wafer warpage from both processes was done using Automatic Wafer Geometry Gauge MX VR. Wafer thickness was controlled and warp was measured automatically. 3. RESULTS AND DISCUSSION 3.1. Chemical etch, wafer warpage and damage depth The mixtures of acid used in the chemical etch process have different roles. The HNO 3 oxidizes the silicon surface to silicon dioxide. Si (s) + 4HNO 3 (aq) SiO 2 (s) + 4NO 2 (aq) + 2H 2 O (aq) (1) The HF strips the oxide layer to form bare silicon surface and further etches the silicon surface to give a smoother surface as can be seen in equations 2 and 3. SiO 2 (s) + 12HF (aq) + 4e - Si (s) + 2H 2 O (aq) + 12F - (aq) + 8H + (aq) (2) Si (s) + 6HF (aq) + 2e - [SiF 6 ] 2- (aq) + 3H 2 (g) (3) Gas bubbles were also observed during the process. Figure 1 and 2 are Transmission Electron Microscopy (TEM) cross-section images of the backside of the silicon 100 from both processes. BG process left deeper backside sub-surface damage with visible micro-crack of 0.30 µm under TEM as shown in Figure 1, compared to after the WCE process with no visible micro-crack as can be seen in Figure 2. Figure 1 (left): TEM image of wafer back side micro-crack after BG process, top layer is titanium Wafer warpage is highly influenced by the type of back processing implemented during the thinning process. The average wafer warpage is 220 µm after the BG process and 18 µm after the WCE process. The wafer warpage was higher after the BG process than after the WCE process. This is driven by the high mechanical stress from the BG process onto the backside of the wafer, which utilizes abrasive diamond particles to take out most of the wafer thickness. The BG process leaves severe backside sub-surface damage in forms of micro-cracks. These micro-cracks contribute

4 1030 Advances in Materials and Processing Technologies II to higher wafer warpage. The WCE process is implemented to remove the micro-cracks left from the BG process, and can lead to lower wafer warpage. Other results of WCE as stress removal was reported where warpage increased with oxidation to about 100 µm and decreased to about 24 µm using H 3 PO 4 in the chemical etching process [14]. Figure 2 (right): TEM image of wafer back side after WCE process, top layer is titanium The warp of the silicon can be increased by the depth of the sub-surface damage of the micro-cracks. It can be suggested that the depth of the damage projection induces stress on the wafer surface and in order to compensate the stress, the wafer is warped. Therefore, the deeper the backside damage, the higher the wafer needs to warp to relieve the stress from the damage Effect of wafer back processing towards surface roughness (R a ) and surface topography Surface roughness of wafer backside was also influenced by the wafer thinning methods used. For example R a values with range of 10 nm 300 nm were reported from the mechanical grinding process which utilizes a wide range of grinding wheel grit size and cutting speed [12]. Figure 3 and Figure 4 show the surface roughness (R a ) of wafer backside after BG and WCE process. The result indicates there is a rise in surface roughness after BG process with R a value of 0.18 nm. In contrast, WCE process provides low surface roughness, R a of 0.11 nm due to smooth surface finish produced on the wafer backside. Other workers have also used a mixture of HF, HNO 3, CH 3 COOH which gave R a of nm and R a of 0.55 nm with HF alone [9]. AFM results in Figure 3 and Figure 4 show different surface finish from the two thinning processes. Fig. 3 AFM image after back-grinding process, R a = 0.18 nm

5 Advanced Materials Research Vols Figures 5 and 6 shows the SEM images of the silicon surface from the BG and WCE processes respectively. It can be seen that the surface of the silicon after the WCE process is smoother that after the BG process. Fig. 4 AFM image after the wet chemical etch, Ra = 0.11 nm Fig 5 SEM image after the BG process Fig 6 SEM image after the WCE process

6 1032 Advances in Materials and Processing Technologies II 4. CONCLUSION From the TEM, back-grinding process induced deep wafer sub-surface damage of the silicon wafer. It was also found that there is a direct correlation between wafer warpage and backside wafer sub-surface damage depth where deep sub-surface damage depth contributes to higher wafer warpage. Wet chemical etching using a mixture of acids is able to remove most of the sub-surface damage and lowers the wafer warpage. AFM confirmed that a lower surface roughness can be achieved through the chemical etching process by using a combination of HNO 3, H 2 SO 4, H 3 PO 4 and HF acids after the back-grinding process. Hence a lower surface roughness value also correlates well with a lower value of wafer warpage after the chemical etching process. Acknowledgment The authors would like to thank the Malaysian Government agency, MOSTI, for funding with project number IRPA PR0075/ RERERENCES [1] M.K. Grief, J.A. Steele Jr, 19th IEEE/CPMT Electronics Manufacturing Technology Symposium, (1996), [2] J.J. Young, A.P. Malshe, W.D. Brown, T. Lenihan, D. Albert, V. Ozguz, SPIE Proc. International Conf. High Density Interconnect and Systems Packaging, Santa Clara CA US, 4428, (2001), [3] J. Chen, I. De Wolf I., Semicon. Sci. and Tech., 18, (2003), [4] B. Leroy, C. Plougonven, J. Electrochem. Soc., 127 (4) (1980), [5] H. Lu, D. Yang, L. Li, Z. Ye, D. Que, Physica Status Solidi A, 169 (2) (1998), [6] A. E. Widmer, W. Rehwald, J. Electrochem. Soc., 133 (11) (1980), [7] H.F. Hadamovsky, Ed, Werkstoffe der Halbleitertechnik, Deutscher Verlag fur Grundstoffechnik, Leipzig, (1990), [in German]. [8] N.R. Draney, J.J. Liu, T. Jiang, IEEE Workshop on Microelectronics and Electron Devices, (2004), [9] B.H. Yeung, V. Hause, T.Y. Lee, IEEE Trans. Adv. Packaging, 23 (3) (2000), [10] M. Reiche, G. Wagner, Adv. Packaging, 12 (3) (2003), [11] L. Wu, J. Chan, C.S. Hsiao, IEEE Proceedings 53rd Electronic Components and Technology Conference, (2003), [12] D. Paehler, D. Schneider, M. Herben, Microelectronics Eng., 84 (2003), [13] H.D. Chiou, Y. Chen, R. W. Carpenter, J. Leong, J. Electrochem. Soc. 141 (7) (1994), [14] S. A. Jang, I. S. Yeo, Y. B. Kim, B. J. Cho, S. K. Lee, Electrochem. Solid State Lett., 1 (1) (1998),

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