GaN Industrial Offer for Multipurpose Power MMIC Design G. CALLET

Transcription

1 GaN Industrial Offer for Multipurpose Power MMIC Design G. CALLET

2 Outline UMS Foundry position Gallium Nitride processes at UMS Foundry service Global presentation Foundry offers Foundry process flow Additional Services Ulm Design tools and support Current Design Kit GH25-10 Upcoming Design Kit enhancement UMS available GaN products Qualification and Roadmap Villebon 2

3 UMS Foundry position All our processes are used for producing UMS Products Low noise processes are also able to provide medium power Very homogeneous on wafer ITAR free 3

4 GaN at UMS 2 GaN on SiC main processes GH50 & GH25: GH50: Packaged products only Qualified Process 500nm gate length Frequency range: DC 6 GHz Very High breakdown voltage: V bds > 200V Power density: 5W/mm Design Kit for packaged dies available on ADS Example: CHK040A: 6x8x250µm Power bare o V ds =50V, I ds =350mA o Freq: GHz o Pout > 46.5dBm o PAE > 48% Complete Selection Guide available at

5 GaN at UMS GH25: MMIC process open in Foundry early access mode 250nm gate length On 4-inch SiC wafer Frequency range: DC 20 GHz V ds = 30V as standard Recommended Operating Value I dss = 850 ma/mm as average value Very High breakdown voltage: V bds > 120V Power density: 10GHz in CW Mode Design Kit available for ADS : NL model for Hot FET L model for noise FET NL model for Cold-FET NL model for diodes (Scalables models for passives and active elements) Qualification in progress 5

6 Why a GaN foundry offer Strong R&D partnerchips with III-VLab and IAF since 10 years Strong supports from MoDs and National Administrations Strong collaboration with preferred Design Center: MEC, UM-Services, IAF, First GaN implementation in UMS from 2005 Availability for MMIC design As for GaAs qualified processes, UMS commits to open GaN GH25 process in foundry mode once qualification is completed for the markets: Defense, Space (VSAT) Telecom Other new opportunities: TWT, instrumentation, electronics GaN is the next step after GaAs offer towards High Power 6

7 The foundry service at UMS Provide access to proprietary technologies as a service. Customer design, UMS design rules and models Delivery of PCM qualified wafers : for prototyping (NRE) for fully owned production (ASIC). Additional services offered : 100% measurement (DC, RF, Power, noise) Dicing, sorting. Visual inspection. Packaging for volume. Ulm facility - Germany Ulm Villebon facility - France Production and delivery of PCM qualified wafers in quantities (ASICs). Villebon 7

8 3 Foundry offers Standard processes Stable and qualified technology Accurate simulation models Spread data Guaranteed processing time Fixed services with all in depth options Early access mode For advanced process Limited model support Available process variation Early access to advanced processes for R&D purpose Current GH25 offer MPW Mode Multi Customer runs Low budget Limited support Chips dimensions imposed by UMS Dates on UMS web 8

9 How the service is provided Customer support during selection of technology. Training at UMS (2/3-day foundry course). Supply of PDK by /ftp for easy and interactive use. Customer support during design phase (consulting). Design Rule Checking (DRC) and Foundry Design Review meeting. Processing + MMIC characterization. Delivery of diced/undiced wafers or chips either on film or in packing. 9

10 Foundry course 2-day sessions are organized for new customers, allowing a first contact between customers and UMS Services. These two days bring an UMS inside image, and give us a feedback from customers. Customer oriented items are reviewed : Technologies and design rules. Design examples (LNA, Power amplifier, mixer) and tricks. CAD tools and electrical models. Discussions and demo with Agilent CAD support engineers. Reliability. Packaging & Measurement capabilities for production. A third day for extra-support can be managed for specific request 10

11 PCM Process Control Monitor Purpose: the PCM is a set of devices for critical technological parameter measurement for process control: detect process drifts determine the cause of drifts for wafer inspection: reject out of specification wafers provide a guarantee of the wafer quality to the customer Location: minimum 20 sites per 4" wafer in general, one PCM site per tile -> an empty space must be reserved for the PCM placement Measurement: the PCM pattern is measured 3 times during the process after boron implantation: active layer, isolation, ohmic contact after air-bridge: previous + FET + interconnects end of process: previous + via-holes 11

12 Back-end services Automatic equipment On-chip individual identification Dedicated Probecards prototyping 8 vector analyzers up to 110GHz, Custom probecards for on-wafer measurements 3-port equipment up to 20GHz 2 noise test benches 2 to 40GHz Mixer and VCO bench from L band to 77GHz DC stations, DC probe cards manufacturing service 3 power stations up to 40GHz in CW or pulsed mode Cleanroom for production measurement Automated visual inspection tools 12

13 Foundry Lot tracking tool on UMS website: 13

14 Design Kit GH ADS Scalable models for passive elements Scalable and multi-bias models for active devices New PDK now available (v3.1) compatible ADS2009/2013 Nonlinear transistor model Nonlinear models for switch applications (cold-fet model). 2 configurations available, parallel and series Nonlinear model for GaN-based diodes Passive elements: Inductors Capacitors TaN resistors HRW resistors (high-resistivity) Via-holes Macro layout for active and passive components User Guide 14

15 NL Hot-FET model 2 topologies available for power applications V1S: GD=2.7µm, GS=0.8µm, Recommended V DS bias = 30 V V9S: GD=1.7µm, GS=0.8µm, Recommended V DS bias = 25 V (less power but improved power gain) Model validation range Number of gate fingers (N): fingers Gate finger width (Wu): 30 µm to 150 µm Frequency: DC - 30 GHz Drain voltage bias V DS : 15V to 30V Drain current bias I DS : around 100mA/mm Back-side temperature: 25 C Additional model features Evaluation of the channel temperature T J =T Backside + R Th *P dissipated, with R Th depending on T Backside Intrinsic quantities available: intrinsic Gate, Drain and Source voltages, channel source current, gate diode currents 3-ports model available through Via parameter (transistors without via-holes) 15

16 Power comparison for 8x100 at 13 GHz (3 samples) Freq: 13 GHz CW conditions I d0 = 100 ma/mm V ds0 = 22.5 V Sim. = Meas.= Source Impedance: 50 Ohm Load Impedances for max Pout 16

17 Linear Noise model 2 topologies available V9S: GD=1.7µm, GS=0.8µm V1S: GD=2.7µm, GS=0.8µm Model validation range Number of gate fingers (N): fingers Gate finger width (Wu): 30 µm to 100 µm Frequency: DC - 30 GHz Drain voltage bias V DS : from 10V to 20V Drain current bias I DS : 50 to 150 ma/mm Back-side temperature: 25 C Additional model features 3-ports model available through Via parameter (transistors without via-holes) 17

18 Noise figures: 2x75µm v1c (centered gate), vs (standard STFP), v9s1 (reduced STFP) Main trends Optimum bias point for minimum noise figure: 100 to 150mA/mm: NF ~ 1.2dB at 10GHz NF ~ 2.0dB at 20GHz 18

19 NL Cold-FET models 1 topology available for switch applications V1C: centered gate GD=GS=1.7 µm, No Field-plate 2 transistor configurations (with associated model) Parallel (2-ports by default) Series (3-ports) Model validation range Number of gate fingers (N): fingers Gate finger width (Wu): 30 to 100 µm Frequency: DC - 30 GHz Gate voltage bias V GS : -25V to 1.8 V Back-side temperature: 25 C Additional model features Intrinsic quantities available: V gs, V ds, I ds, I gs 3-ports model available through Via parameter in the parallel configuration (transistors without via-holes) 19

20 NL model of GaN-based Diodes 1 diode topology available Gate=Anode, Drain/Source=Cathode, AC=1.7µm Model validation range Number of gate fingers (N): fingers Gate finger width (Wu): 50, 10, 20, 50 and 100 µm Frequency: DC - 25 GHz Anode-Cathode Voltage V AC : -40V to 2 V Back-side temperature: 25 C 20

21 Upcoming DK enhancement Embedding DRC ADS based on GH25-10 layout rules Embedding electro-thermal capability in the nonlinear hot-fet model Extension of the validity range to big transistor sizes Up to 12 fingers and up to 250 µm finger width for power application 10 fingers and up to 150 µm finger width for power switches Extension of the passive element set 16-vertices inductors Edition of GH25-10 Design Manual Long term enhancement: Stack definition in coordination with Agilent for accurate EM Simulations (already existing on other process such as PH25) 21

22 UMS available GaN products 22

23 Pout(dBm) & PAE(%) 180W L-Band HPA 0.5µm gate length GaN HEMT on SiC in SEB Package Picture of CHZ180A-SBE Quasi-MMIC process including Power Bare + Internal matching Possible co-simulation with the processes used Main Features: Wide band capability: GHz Pulsed operating mode High power: > 180W High PAE: up to 53% DC bias: V DS = I D_Q = 1.3A MTTF > 10 6 Tj = 200 C RoHS Hermetic Flange Ceramic package POUT V DS = 45V, I D_Q = 1.3A, Pin = 39dBm Pulsed mode (100µs-10%) PAE Pulsed Mode Gain Frequency (GHz) Power Gain (db) 23

24 15W X-Band HPA 250nm gate length GaN on HEMT on SiC performances on-wafer Main Features: Wide band capability: GHz Pulsed operating mode High power: Power peak 16,8W High PAE > 70% DC bias: V DS = I D_Q = 80mA/mm Layout of X-Band HPA Linear Gain P out (dbm), PAE (%) at P in =28dBm 24

25 Wide band Band SPDT 250nm gate length GaN on HEMT on SiC performances on-wafer Main Features: Wide band capability: DC 12GHz Isolation < -20dB Insertion loss > -1dB Layout of GaN-based wide band SPDT Small signal - Isolation Small signal - Insertion loss Power sweep - Insertion Loss at 3GHz 25

26 Qualification and GaN Roadmap Qualification of GH25-10 in progress, reliability tests running End of tests: mid 2014 Final report / Audit: September 2014 Some tests will continue after to improve MTTF determination GaN Roadmap on each process: GH25 & GH50 26