Semiconductor Equipment Assessment for Key Enabling Technologies

Transcription

1 Semiconductor Equipment Assessment for Key Enabling Technologies

2 Semiconductor Equipment Assessment for Key Enabling Technologies Introduction SEA programs proven principle: Take novel, innovative and promising equipment, that has left the R&D phase, into a joint assessment activity Collaboration of equipment supplier, end-user and research institute to perform assessment experiments for one specific equipment and finally develop the equipment according to the end-user s specifications Bridge the well-known gap between the phase of having an engineered tool available and finding the first user for it

3 Semiconductor Equipment Assessment for Key Enabling Technologies Introduction SEA Projects in IST SEA-NET 01/ /2009 SEAL 06/ /2013 SEA4KET 11/ /2016 Framework Programme: 6 Sub-Projects: 20 (incl. 1 Management SP and 1 cross-cut R&D SP) Partners: 31 Framework Programme: 7 Sub-Projects: 19 (incl. 1 Management SP and 1 cross-cut R&D SP) Partners: 36 Framework Programme: 7 Sub-Projects: 14 (incl. 1 Management SP and 1 cross-cut R&D SP) Partners:

4 Semiconductor Equipment Assessment for Key Enabling Technologies Introduction Project Objectives Strengthening the European equipment industry Bring together critical mass of research and development power to form synergies Make use of the excellent European research infrastructure at Fraunhofer IISB, LETI and IMEC Increase the chances for SME s to get access to IC makers Developing a common strategy for key enabling technologies in the EU Stimulate an approach to initiate sustaining partner-ships amongst equipment industry, IC industry and research institutions Sustainable research and development as horizontal activities Duration: Nov Oct. 2016

5 Semiconductor Equipment Assessment for Key Enabling Technologies Introduction

6 SP2 Cross-cut R&D Sustainable Support and Research and Development Provide an infrastructure to exchange wafers between partners Identify and solve common problems in respect of manufacturing science and equipment efficiency Investigate and provide wafer resizing Create and provide learning materials Advances proposed in SP2 Collaboration between SEA4KET partners allowing multisite processing or characterization Energy efficiency analysis and improvement in order to reduce energy consumption per processed unit Quality and advanced process control including automation, security, yield, COO and standard compliance Resizing 450 mm wafers to support further processing and characterization utilizing 300 mm equipment Create training materials and organizing events and workshops to guaranty knowledge exchange between partners Partners: Fraunhofer IISB, CEA-Leti, IMEC, FHWN

7 SP3 - SWCC450 Single Wafer Critical Cleaning 450 mm Assess a single wafer cleaning pilot line system In consultation between equipment supplier, pilot line operator and end user, this equipment assessment will focus on test cases related to front end of line wet cleaning and etching processes, relevant to 1x nm technology nodes on a Lam Research s single wafer spin clean system Advances proposed in SP3 Spin Clean Systems are being used for high volume production in FEOL, MOL and BEOL for 2x nm technology on 300mm wafers Industry transition to 450mm wafer size is intended to be combined with new technology nodes 1xnm and smaller. Currently 10nm and 7nm technology is at an early development stage on 300mm Project start has been postponed due to change of industry timing for introduction of 450mm Lam Spin Clean System Partners: LAM, Imec, Intel

8 SP04 - ABP Advanced Batch Processing Assessment of a 450mm Batch Oxidation System for 14nm technology node and beyond Prove general ability for future 450mm production requirements Characterize and understand behaviour of 450mm wafers in thermal processing Assessment location: G450C 450mm pilotline, utilizing Equipment Performance Metrics (EPM) and Demonstration Test Methods (DTM) as agreed between G450C and European consortia Advances proposed in SP4 Prove general ability of 450mm Batch Oxidation System for future 450mm production requirements in G450C pilot line, with respect to process capability, repeatability, cleanliness, equipment reliability, physical tool performance and system internal contamination Specific improvements are expected in the areas of reduction of logistics overhead time, contamination performance, efficient mini-environment purging, and isolation and uniform heat distribution of heating element and flange area. After validation several of the expected improvements can be considered for 300mm batch equipment Coordinator: ASM Partners: Fraunhofer IISB, TNO, Intel

9 SP5 CWH Critical Wafer Handling Assessment of clean handling technologies for ultra thin 300 mm and 450 mm wafers Evaluation of different end-effector handling concepts: Bernoulli, Ultrasound, Edge-grip and Backside grip Advances proposed in SP5 Clean and safe handling of ultra thin 300 mm wafers and 450 mm wafers Enabling contact free handling for 450 mm wafers and thinned wafer substrates with smaller wafer diameters Adapting end-effectors on a 450 mm cluster platform Comparison between the four different end-effectors relating to particle generation, contamination, bow, and placing accuracy Testing end-effectors with regard to industrial applicability Partners: Fraunhofer IISB, ZS-Handling, Mechatronic, HAP, Peter Wolters, Freiberg Instruments Coordinator: Ulrich Schöpka, Hassan Samadi / IISB Duration: 36 Months

10 SP6- AMLL450 Vacuum transportation interface for 450mm architecture Assessment of Vacuum transportation interface for 450mm architecture Studies of this new Handling concept for advanced equipment/fab architecture Advances proposed in SP6 Development & manufacturing of 450mm carrier and interface Attachment of the system to the 300/450mm cluster at FhG IISB Assessment of the tool/process in this 300/450mm cluster platform Partners: adixen, Fraunhofer IISB, ASM Coordinator: adixen Vacuum Products Duration: 36 Months

11 Analytical laboratory for 450 mm Metallic and ionic impurities Wafer surface analysis by VPD-ICPMS, VPD-AAS, VPD-IC Automated droplet scanner for 450 mm IISB facility 450 mm VPD chamber for sample preparation (available end 2014) IISB facility

12 Analytical laboratory for 450 mm Organic compounds Wafer surface analysis by TD GC-MS Thermodesorption tubes for the monitoring of clean room and process environment Thermodesorption furnace for silicon substrates (450 mm available end 2014) IISB facility

13 SP7 450DM 450mm defects metrology The subproject aims to evaluate 450mm defects metrology for process and materials characterization and qualification Advances proposed in SP7 An assessment of novel EDX module integration with AMIL s defect review tool 450mm and 300mm material analysis defectivity protocol for imec s 10nm technology node pilot line Material analysis base line creation for process tools qualification Partners: AMIL, FhG, imec, Intel

14 SP8 - MetroCom Metrology Components Set up of an open platform that serves as evaluation stand for different metrology components Evaluation of novel metrology components Advances proposed in SP8 An open 300/450 mm platform will be made available to support metrology companies in testing their sensors Sensor for carrier life-time measurement for silicon wafer characterization at low injection levels (high sensitivity to below 1 x 109 Fe atoms/cm³) Line-based spectroscopic ellipsometer for fast mapping of 450 mm wafers (throughput of up to 60 wafers/hr) Topography sensor for 450 mm wafers (Makyoh-based, field-of-view 300 mm + stitching) Partners: Fraunhofer IISB, Freiberg Instruments, MFA Budapest, E+H Metrology Coordinator: Dr. Martin Schellenberger / IISB Duration: 36 months

15 SP9-3DIMS 3D Integrated Measurement System Assess how the Integrated Test System of Cascade Microtech responds to the technical challenges along the 3D test flow Advances proposed in SP9 Presentations on emerging results to partners in IMEC s Industrial Affiliation Program on 3D Integration Analysis of the existing engineering probe solution Definition of the components of the components to add Integrate the probe card and test instrumentation in the prober Make the test head docking compatible with the vibration insulation of the engineering probe station Adaptation of fine-pitch probe cards Partners: Cascade Microtech, Imec, Global Foundries

16 SP10 - COVBOND Direct Covalent Bonding at Room Temperature Assessment of new manufacturing equipment allowing for room temperature covalent wafer bonding Evaluation of the new processes for applications in the area of engineered substrates, CMOS-MEMS and high vacuum MEMS Advances proposed in SP10 Development of a surface preparation method for enabling room temperature covalent bonding Characterization of the process for various combinations of materials/surface qualities Setup of a manufacturing environment-compatible process flow, enabling high productivity Process optimization for extremely low contamination levels Implementation of the newly-developed equipment and processes into volume manufacturing environment Partners: EVG, CEA LETI, ST Microelectronics

17 SP11 3DIPiCs Inspection for 3D Integrated Photonics Circuits The subproject aims to evaluate the possibility to adapt standard CMOS defectivity tool for KETs application: 3D Heterogeneous integration and Photonics Advances proposed in SP11 An assessment on available solutions have been establish amount the majors tool constructor excelling on this domain Initial assessment of feasibility and capability as well as identification of the hard points to improve in the tool have been done Discussion on chuck specification in order to improve capabilities and ease of use for both cases : standard CMOS defectivity and the targeted KETs applications Partners: ST, AMIL, Leti

18 SP12 - XMeCK X-ray Metrology Assessment of the latest generation X-ray metrology D8 FABLINE from Bruker AXS Assessment of high Brightness X-ray source for MicroHRXD Advances proposed in SP12 Availability of high brightness X-ray sources which will result in an improvement in throughput of a factor of ~ 10. Improved usability and algorithms targeted to advanced materials, photonics, and their heterogeneous integration Complete prototype Improved analytical software for HRXRD Partners: Bruker, ST, CEA

19 SP13 - REPSiC Rapid Electrical Field Driven Processing of Gate Dielectrics on Silicon Carbide Assessement of new equipment for efficient, rapid electrical field driven oxidation resp. nitridation for growing a gate dielectric on SiC at reduced temperatures (<1000 C) and time Evaluation of oxides grown on blanket SiC wafers and SiC test devices for implementation in the production of SiC MOS capacitors and MOSFETs as key emerging devices Advances proposed in SP13 Proposed concept uses a new electron charge driven method for enhanced oxidation rate of SiC without oxide damage Process has been demonstrated on Si wafers and SiC samples before Remarkable reduction of oxidation temperature and thermal budget Partners: HQ-Dielectrics, Fraunhofer IISB, Infineon Technologies Coordinator: Juergen Niess / HQ-D Duration: 24 Months

20 SP14 TLS4SiC Thermal Laser Separation for Fast High Quality Silicon Carbide Dicing Assessment of an innovative dicing technology able to fulfill the requirements of SiC volume production Advances proposed in SP14 Assessment of the kerf free dicing technology for Silicon Carbide product wafers with regard on throughput, reliability, edge quality and electrical characteristics of separated chips and handling issues Increased feed rate up to a factor of 100 compared to state of the art dicing technology Very high edge quality no chipping, smooth side walls and no delamination of backside metal promises good electrical characteristic and good long-term stability of separated chips High throughput and no tool wear results in a significantly reduction of process costs compared with state of the art dicing technology TLS4SiC will be an enabler for SiC volume production by providing a separation technology allowing for high quality results with high throughput far beyond state-ofthe-art Partners: 3D-Micromac, Infineon, Fraunhofer IISB, Fraunhofer CSP Coordinator: Dirk Lewke / Fraunhofer IISB Duration: 24 Months

21 Semiconductor Equipment Assessment for Key Enabling Technologies Introduction

22 Information and Acknowledgement Dr. Markus Pfeffer Fraunhofer Institute of Integrated Systems and Device Technology Erlangen, Germany The SEA projects were/are funded by the European Commission SEA-NET: IST SEAL: IST SEA4KET: IST Thank you!