Graduate Program on Microelectronics

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1 Graduate Program on Microelectronics

2 Formação de RH e Pesquisa na Área de Circuitos Tolerantes à Radiação no Programa de Pós-Graduação em Microeletrônica -PGMICRO/UFRGS Ricardo Reis

3 Formação de RH e Pesquisa na Área de Circuitos Tolerantes à Radiação no Programa de Pós-Graduação em Microeletrônica -PGMICRO/UFRGS por Ricardo Reis Preâmbulo 3

4 The Beginning Start of Computer Science Graduate Program Strong hardware activity 4

5 he Beginning... End of Seventies Spin of Several Companies Digitel, Altus, STI,... HR for EDISA 5

6 Start of Microelectronics Activities at UFRGS First formal work on microelectronics at Porto Alegre Ingrid Jansch Porto Advisor: Anatólio Lachuk Geração de Elipses em Processadores de Exibição Gráfica 6

7 Microelectronics Group: Altamiro Susin Tiaraju Wagner Ricardo Reis Start of SBCCI Symposium on Integrated Circuits and Systems Design Now Sponsored by: SBC, SBMicro, IEEE CAS, ACM SIGDA, IFIP WG10.5 7

8 First CHIP of several chips using CMP 8

9 Some prototypes RISC processor, opamp (1995), gate array (1996) 8051:VHDL & FPGA (1995)

10 Microelectronics Group Research Topics Embedded Systems Analog Design Digital Design Design Methodologies SoC - Systems on a Chip NoC - Networks on Chip MEMs VLSI Architectures and Dedicated Architectures DSP Systems (Audio and Video) Dedicated Architectures for Video and Audio Compression

11 Microelectronics Group Research Topics Fault Tolerant Circuits Circuits Tolerant to Radiation Effects Test (system, processor, analog) FPGA Design Methodologies Low Power Design Techniques Asynchronous Circuit Design Mixed Signal Logic Synthesis Physical Design EDA Tools EDA for 3D Chips

12 Microelectronics Group Design, Test and EDA 3 Graduate Programs at UFRGS: PPGC- Graduate Program on Computer Science PPGEE - Graduate Program on Electrical Engineering PGMicro - Graduate Program on Microelectronics

13 Graduate Program on Microelectronics

14 PGMicro The program activities started in It was an answer to a call from Capes to launch PhD Programs on microeletronics. First PhD students started on March Aproval at UFRGS: CONSUN decision of August First and unique Multidisciplinary Program on Microeletronics of the country. The PGMicro is associated to 4 units of UFRGS Escola de Engenharia (Dep. Engenharia Elétrica) Instituto de Informática Instituto de Física Instituto de Química

15 PGMICRO Research Areas Physics-Chemistry processing of Materials and Devices. Physics-Chemistry characterization of Materials Characterization and Modeling of Electronic Devices Integrated Circuits and Systems Design Test of Circuits and Electronic Systems EDA - Electronic Design Automation

16 PGMICRO Master Course Aproved in 2006 and the first students started in March master thesis were already completed. 37 students doing the Master.

17 PGMICRO PhD Course First Thesis was finished in 02/March/2007 Student: Alessandro Gonçalves Girardi (now he is professor at UNIPAMPA) Advisor: Sergio Bampi 12 PhD thesis were already presented. Another two are scheduled to December. 25 students doing the PhD.

18 Professors Permanent Professors: Altamiro Amadeu Susin Andre Inacio Reis Daniel Lorscheitter Baptista Fernanda Chiarello Stedile Fernanda Gusmão de Lima Kastensmidt Flavio Horowitz Gilson Inácio Wirth Henri Ivanov Boudinov Luigi Carro Marcelo de Oliveira Johann Marcelo Soares Lubaszewski Renato Perez Ribas Ricardo Augusto da Luz Reis Sergio Bampi

19 Professors Associated Professors: Livio Amaral Paulo Fernando Papaleo Fichtner Professors with Productivity Scholarship from CNPq: 16 3 Pos-Docs PNPD (Capes) Giovani Cheuiche Pesenti André Borin Soares Gustavo Wilke 1 Pos-Doc ProDoc (Capes) Karen Paz Bastos

20 Circuits Tolerants to Radiation Effects Activities on the subject since 1999 Thesis of Fernanda Limas Kastensmidt

21 TOPICS Design Methodologies to cope with Radiation Effects SRAM Memories Tolerant to Radiation Effect Radiation Hardened Programmable Devices Fault Model Asyncronous Circuits Tolerant to Radiation Effects Variability Aware Design Modeling and Simulation of TID and SET at Different Levels of Abstraction Quaternary Circuits for Fault Tolerant Applications Layout coping with Radiation Effects

22 Radiation Tolerance Test and Qualifica/on of ASIC and Programmable Circuits Electric Simula/on Device Simula/on Under Radia/on Development of SEE and TID mi/ga/on techniques at different levels Layout Electrical Logical Architectural

23 Radiation Hardened Programmable Devices Self-checking design for the protection of FPAAs against SEUs Diversity TMR for the protection of PSoCs against SETs

24 Study of Total Ionizing Dose Effects on FPAAs Practical Experiments at LRI - IEAv Remote measurements Target Circuit: Switched Capacitor FPAA Dose Rate 1 krad/h Accumulated dose: 27 krad Programmed application

25 Fault Model Variability Predic/on Measurement Cri/cal Path analysis Single Event Transient (SET) Suscep/bility analysis for different collected charges Analysis of the most sensi/ve nodes in the circuit

26 Modeling and Simulation of TID and SET at Different Levels of Abstraction Mixed Mode Simulation Synopsys Tools for 3D Device Simulation Combined with Circuit (Hspice) Level Simulation

27 Quaternary Circuits for Fault Tolerant Applications Fault Tolerant Quaternary LUT TG1 TG2 Error Correcting Quaternary LUT IN1 IN2 TG3 OUT TG4 TG5 TG6 IN3 Error Correcting Quaternary FF IN4 TG7 TG8 INV1 INV2 INV3 INV4 Analisys of the Variability Impact QLD0 QLD1 QLD2 QLD3 32 xstors SEL INV1 Error Detection Circuit INV2 INV3 INV4 ERROR

28 Aging Monitoring in Safety-Critical Applications Application: aging monitoring, aiming to sense speed degradation due to NBTI Variable guardband interval Much lower sensitivity to VT variations then the Agarwal et al. sensor Drawback: significant Si area overhead Published in IEEE IOLTS2009 CCG layout. Area = 30.8x13 µm 2 Delay Element: 1. CCG: Current Circuit Generator; 2. GB: Guardband Generator AMS 0.35 µm CMOS GG layout. Area = 70x13 µm2

29 Cell Layout Generation: the Astran Tool Netlist-to-layout Layout cell generation compliant to standard cell library format Large, complex cells with non-complementary logic, different number of PMOS, NMOS transistors Consider channel density during intra-cell MOSFET placement ST 65 nm CMOS: our sensor (8.4 x 2.6µm 2 )

30 Layout Coping with Radiation Effects Analysis of Transistor Sizing and Folding Effectiveness to Mitigate Soft Errors Thiago Rocha de Assis Advisor: Ricardo Augusto da Luz Reis Co- Advisor: Fernanda Gusmão de Lima Kastensmidt

31 Past PhD Students Fernanda Gusmão de Lima Kastensmidt Designing Single Event Upset Mitigation Techniques for Large SRAM-Based FPGA Components, September/2003, PPGC/UFRGS. Advisor: Ricardo Reis Gustavo Neuberger Protecting Digital Circuits Against Hold Time Violations Due to Process Variations, September 3, 2007, PGMicro/UFRGS. Advisor: Ricardo Reis Cristiano Lazzari, Transistor Level Automatic Generation of Radiation-Hardened Circuits, December 7, 2007, PGMicro/UFRGS. Advisor: Ricardo Reis Rodrigo Possamai Bastos, Transient-Fault Robust Systems Exploiting Quasi-Delay Insensitive Asynchronous Circuits, 9 de Julho de 2010, PGMicro/UFRGS. Advisor: Ricardo Reis. Co-Advisor: Fernanda Kastensmidt

32 Past Master Students Rodrigo Possomai Bastos, Design of a Soft Error Robust Microprocessor, Agosto de 2006, PPGC/UFRGS. Advisor: Ricardo Reis Thiago Rocha Assis, Analysis of Transistor Sizing And Folding Efectviness to Mitigate Soft Errors, 23 de Março de 2009, PPGC/UFRGS. Advisor: Ricardo Reis Co-Advisor: Fernanda Kastensmidt Jose Rodrigo Azambuja, SEE Mitigation Techniques Based on Software and Hardware for Microprocessor Fault Tolerance. 2010, PPGC/UFRGS. Advisor: Fernanda Kastensmidt Arthur Frantz, 2007, PPGC/UFRGS. Advisor: Fernanda Kastensmidt

33 Past Master Students Ivandro da Silva Ribero Desenvolvimento de Circuitos de Teste para Caracterização de Circuitos Integrados sob Radiação PGMicro/UFRGS. Advisor: Gilson Inacio Wirth. Ulisses Lyra dos Santos Projeto de um Amplificador Operacional CMOS de Dois Estágios e Simulação Elétrica do Efeito de Dose Total PGEE/UFRGS, Advisor: Gilson Inacio Wirth. Vitor Paniz Simulação Elétrica do Efeito de Dose Total em Células de Memória Estática (SRAM) PGEE/UFRGS. Advisor: Gilson Inacio Wirth. Franco Ripoll Leite Estudo e Implementação de um Microcontrolador Tolerante à Radiação PGEE/UFRGS Co-Advisor: Gilson Inacio Wirth.

34 Graduate Students on Radiation Hardening Research Areas Raul Chipana: Characterization and SET mitigation in clock trees and in logic of flash-based FPGAs. Samuel Pagliarini: Characterization and analysis of radiation effects in integrated systems from high level to layout. José Eduardo: Project of Radhard memory and standard memory cells for radiation hardening circuits. Jose Rodrigo Azambuja: SEE mitigation techniques based on software and hardware for microprocessor fault tolerance. Jimmy Tarrillo: Fault tolerant techniques for SpaceWire and System applications for Satellites. Eduardo Chielle: Selective software based techniques for microprocessors. Walter Bartra: Fault Simulation using Labview

35 Some Recent Publications: BASTOS, R., KASTENSMIDT, F., REIS, R. Design of a Soft-Error Robust Microprocessor, Microelectronics Journal, V. 40, N. 7, Elsevier Publishers, ISSN: , July 2009, p DOI: /j.mejo NEUBERGER, G., KASTENSMIDT, F., REIS, R., WIRTH, G., BREDERLOW, R., PACHA, C., Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies, IN: VLSI-SoC: Advanced Topics on Systems on Chip, Springer, 2009, p. 1-16, ISBN DOI / _1 BRUSAMARELLO, L., SILVA, R., WIRTH, G., REIS, R., Statistical and Numerical Approach for a Computer Efficient Circuit Yield Analysis, IN: VLSI-SoC: Advanced Topics on Systems on Chip, Springer, 2009, p , ISBN DOI: / _9 REORDA, M., VIOLANTE, M., MEINHARDT, C., REIS, R., An On-Board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Of-The-Shelf SRAM- Based FPGAs, DFT 2009, 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Chicago, USA, October 7-9, 2009.

36 Some Recent Publications: ASSIS, T., KASTENSMIDT, F., WIRTH, G., REIS, R., Avaliando a Eficiência do Redimensionamento Simétrico e Assimétrico de Transistores para a Redução de Single Event Effects em uma Tecnologia 90nm CMOS, In: 15th Workshop Iberchip, 2009, Buenos Aires, Argentina, Proceedings, March 24-27, p Ediciones Cientificas Americanas, ISBN: REORDA, M., VIOLANTE, M., MEINHARDT, C., REIS, R., A Low-Cost SEE Mitigation Solution For Soft-Processors Embedded in Systems on Programmable Chips, DATE 2009, Nice, France, April 24-27, 2009.p , ISBN BASTOS, R., MONNEY, Y., SICARD, G., KASTENSMIDT, F., RENAUDIN M., REIS, R., A Methodology to Evaluate Transient-Fault Effects on Asynchronous and Synchronous Circuits, ETS 2008, 14th IEEE European Test Symposium, Sevilha, Espanha, May 25-28, BASTOS, R., MONNEY, Y., SICARD, G., KASTENSMIDT, F., RENAUDIN M., REIS, R., Comparing Transient-Fault Effects on Synchronous and on Asynchronous Circuits, IEEE International On-Line Test Symposium, IOLTS 2009, Sesimbra, Portugal, June 24-27, p ISBN

37 Some Recent Publications: ASSIS, T., BRUSAMARELLO, L., KASTENSMIDT, F., WIRTH, G., REIS, R., Analyzing Transistor Size and Folding Method for Radiation Hardening, RADECS 2009, September 14-18, Brugge, Belgium, FRANCK, H.; WILKE, G.; REIS, R.; GÜNTZEL, J.. Somadores Tolerantes a Falhas Usando BSD e Codificação 1 de 3. In: WORKSHOP IBERCHIP, 16 (IBERCHIP 2010). Foz do Iguaçu, Brasil, de Fevereiro de ISSN BASTOS, R., SICARD, G., KASTENSMIDT, F., RENAUDIN M., REIS, R., Evaluating Transient-Fault Effects on Traditional Implementations of the C-element, IEEE International On-Line Test Symposium, IOLTS 2010, Corfu, Greece, July 4-7, P , ISBN: DOI: /IOLTS

38 Some Recent Publications: Da Silva, Roberto ; BRUSAMARELLO, Lucas ; Wirth, Gilson. Statistical fluctuations for the noise current from random telegraph signals in semiconductor devices: Monte Carlo computer simulations and best fits. Physica. A (Print), p. 1-13, Da Silva, Roberto ; Wirth, Gilson. Logarithmic behavior of the degradation dynamics of metal oxide semiconductor devices. Journal of Statistical Mechanics, v. 2010, p. P04025, Camargo, Vinícius V. A. ; Ashraf, Nabil ; Brusamarello, Lucas ; Vasileska, Dragica ; Wirth, Gilson. Impact of RDF and RTS on the performance of SRAM cells. Journal of Computational Electronics (Print), p. 1-6, Brusamarello, Lucas ; Neuberger, Gustavo ; Wirth, Gilson I. ; Silva, Roberto ; Reis, Ricardo ; Murgai, Rajeev ; Reddy, Subodh ; Walker, William. Statistical analysis of hold time violations. Journal of Computational Electronics (Print), p. 1-8, Balen, Tiago R. ; Leite, Franco ; Kastensmidt, Fernanda Lima ; Lubaszewski, Marcelo. A Self-Checking Scheme to Mitigate Single Event Upset Effects in SRAM-Based FPAAs. IEEE Transactions on Nuclear Science, v. 56, p , 2009.

39 Some Recent Publications: BASTOS, R., SICARD, G., KASTENSMIDT, F., RENAUDIN M., REIS, R., Asynchronous Circuits as Alternative for Mitigation of Long-Duration Transient Faults in Deep-Submicron Technologies, Microelectronics Reliability, Volume 50, p , published by Elsevier B.V. in ISSN: DOI: /j.microrel Azambuja, J. R., Sousa, F., Rosa, L., Kastensmidt, F. L. Non-Intrusive Hybrid Signature- Based Technique to Detect SEU and SET Faults in Microprocessors. IEEE Transactions on Nuclear Science, under revision. Kastensmidt, F. L., Fonseca, E. C., Vaz, R. G., Gonçalez, O., Chipana, R., Wirth, G. TID in Flash-based FPGA: Power Supply-current Rise and Logic Function Mapping Effects in Propagation-delay Degradation. IEEE Transactions on Nuclear Science, to appear December, VIOLANTE, M., MEINHARDT, C., REIS, R., REORDA, M., A Low-Cost Solution for Deploying Processor Cores in Harsh Environments, IEEE Transactions on Industrial Electronics, ISSN: , under final revision.

40 SERESSA 2005 International School on Effects of Radiation on Embedded Systems for Space Applications Ariau Hotel, Manaus, Brazil, November 20-25, 2005 PROGRAM DAY1: 1- Space Radiation Environment, J.-C. Boudenot (THALES), R. Gaillard (Consultant) 2 - Radiation Effects Overview, R. Schrimpf (VANDERBILT University), H. Barnaby (ASU) 3 - Single Event Effects and Errors Observed in Flight, R. Ecoffet (CNES) DAY2: 4- Multi-level SEU Simulation, M. Sonza Reorda (POLITO), L. Anghel (TIMA) 5 - Effects of Radiation on Analog Circuits, L. Carro (UFRGS), M. Lubaszewski (UFRGS) 6 - Laser based SEE Simulation, P. Fouillat (IXL), D. MacMorrow (NRL) DAY 3: 7 - Hardening by Design, Nicolaidis (iroc Tec), F. Faccio (CERN) 8 - Fault Tolerance in Programmable Circuits, F. Kastensmidt (UFRGS), R. Reis (UFRGS) 9 - Automatic Tools for Design Hardening, C. Lopez Ongill (Univ. Carlos III) DAY 4: 10 - Test Facilities for SEE and Dose Testing, S. Duzellier (ONERA ), G. Berger (UCL 11 - Error Rate Prediction of Digital Architectures, R. Velazco (TIMA) 12 - Demos and Case Studies, C. Chatry (TRAD), V. Pouget (IXL) DAY 5: 13 - Round Table Design Flow and Tools for Hardening Embedded Systems Operating in Space Environment an initiative Organized by: UFRGS, IXL, TIMA UFRGS of

41 SERESSA 2005 Organized by: UFRGS TIMA IXL

42 Livros VELAZCO, R, FOUILLAT, P, REIS, R., Radiation Effects on Embedded Systems, Springer, June ISBN

43 Livros KASTENSMIDT, F., CARRO,L.; REIS, R. Fault-Tolerance Techniques for SRAM-Based FPGA, Springer. April 2006, 183 p., ISBN

44 Livros KASTENSMIDT, F., CARRO,L.; REIS, R. Fault-Tolerance Techniques for SRAM-Based FPGA, Springer. Versão em Chinês, 2010.

45 First IEEE CASS Summer School Physical Design of Reliable Circuits January 12-15, 2010 Porto Alegre, Brazil

46 First IEEE CASS Summer School Physical Design of Reliable Circuits January 12-15, 2010 Porto Alegre, Brazil Program Tuesday, January 12: 1- Noise and Aging Effects [Gilson Wirth/Roberto Silva- UFRGS] 2- Atomistic Simulations on Reliability [Dragica Vasileska/Arizona State University, USA] 3- Radiation Effects and Tolerance Techniques [Ricardo Reis/Fernanda Kastensmidt-UFRGS] Wednesday, January 13: 4- Compact Modeling of CMOS Variability and Reliability [Yu Cao/Arizona State University, USA] 5- On-chip Characterization of Circuit Reliability [Chris Kim/Univ. Minnesota, USA] 6- Panel: Emerging Reliability Threats Thursday, January 14: 7- Circuit Resilience Roadmap [Kevin Nowka/IBM Austin Research Lab, USA] 8- Circuit Layout for Reliability [Frank Liu/IBM Austin Research Lab, USA] 9- Panel: The Need and Challenge of Design for Reliability Friday, January 15: 10- Leakage Power Minimization and Thermal Effects Compensation [Enrico Macii/Polito, Italy] 11- Variability Aware Clock Design [Matthew Guthaus, UCSC, USA / Gustavo Wilke, UFRGS] General Chair PROGRAM CHAIRS Ricardo Reis - UFRGS, Brazil Yu Cao, Arizona State University, USA Gilson Wirth - UFRGS, Brazil

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48 2 IEEE CASS Summer School nd Advanced low power techniques: from Architectures to Physical design January 18-21, 2011 Cusco, Peru

49 LASCAS 2011 Second IEEE Latin American Symposium on Circuits and Systems February 23-25, 2011 Bogotá, Colombia webpage: lascas.org

50 IBERCHIP 2011 XVII Iberchip Workshop February 23-25, 2011 Bogotá, Colombia

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54 Graduate Program on Microelectronics

55 Delay Sensing for Parametric Variations and Defects Monitoring in Safety- Critical Applications

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