Model Diagnoser TM. Ultimate Verification, Quality Assurance and Interactive Debugging for.lib Model of Cell Library
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1 TM Model Diagnoser TM Ultimate Verification, Quality Assurance and Interactive Debugging for.lib Model of Cell Library
2 Agenda Introduction Model Diagnoser Flow Setup/hold time diagnosis for function/noise violations Repairing library model from function/noise violations Inaccuracy diagnosis by library model comparison Function verification between views of library model CCS consistency check of library model Interactive Debugging The Conclusion
3 Legend s Products IP Library Verification/Characterization Products Model Diagnoser TM : Cell Library QA, Diagnosis and Debugging Charflo-Cell! TM : Automatic Cell/IO Library Characterization Charflo-Memory! TM : Automatic Memory Characterization Circuit Simulation Products MSIM : Accurate-Spice Simulator for Analog/RF/Mixed-Signal IC and IP, LCD, and PCB/IBIS/Package PCB Design Manager: Integrated Schematic & Simulation Environment with Test Bench Automation Turbo-MSIM : Fast-Spice Simulator
4 The Problems Standard /IO Cell Library Modeling The.Lib model of standard / IO cell library may be Incorrectly modeled or characterized Inappropriately applied at new PVTs Need QA process to assure the.lib timing model No functional failures shall be resulted Noise on output pins shall be within the margin Timing, power and noise models are valid in accuracy No over-excessive timings degrading speed seriously Need repairing.lib model to meet the QA criteria
5 The Solutions Model Diagnoser TM Functions Setup/hold time diagnosis for function/noise violations Repairing library model from function/noise violations Inaccuracy diagnosis by library model comparison Function verification between views of library model CCS consistency check of library model Interactive Debugging
6 The Necessities Model Diagnoser on top of Characterization Use ultimate validation, different from characterization Verify setup/hold time by directly plugging into final simulation, instead of bi-section with error tolerances Check internal nodes, not covered by characterization Examine glitches and noise strengths on internal nodes, instead of output pins only by simulator s bi-section Trust but verify possible errors in characterization from Characterization tools Simulation tools Human mistakes and manual settings
7 TSMC s Selection Model Diagnoser TM TSMC Selects Legend s Model Diagnoser for Standard Cell Library Quality Assurance "Legend s Model Diagnoser can help locate the functional issues in the.lib models of TSMC 90nm and 65nm standard cell libraries. We are satisfied with the tool results, and continue to work with Legend to ensure our library quality for advanced nanometer technologies," said Tom Quan, deputy director of design service marketing at TSMC.
8 Model Diagnoser TM Flow.Lib Model to be diagnosed Cell Library Layout Extraction Circuit Netlists Configuration File Spice Models Model Diagnoser TM Diagnosis Control SpiceCut-Cell TM Diagnosis Engine Model Repairing Engine Circuit Simulator MSIM Other Spice Setup/hold Time Diagnosis Repairing Timing Model Inaccuracy Diagnosis Function Verification Consistency Check Interactive Debugging Function and Noise Violations Automatic Adjust Margin Table Statistics Graphs.Function vs Spice netlist, Verilog,Vital CCS vs NLDM Receiver & Driver 5X~10X Productivity
9 Setup/Hold Time Diagnosis Function & Noise Check on Latch/Flip-flop Analyze the circuit of each cell by SpiceCut tool, and locate high-risk spots inside the cell. Build all possible state patterns based on functions and conditions in.lib, and set up corresponding stimulus. Simulate the cell by applying setup/hold time, and min. pulse width from.lib, with the stimulus built. Verify the simulation results for locating functional failures and noise violations (e.g. glitch) Locate over-excessive timings (e.g. min. clock width) to prevent from serious performance degrading
10 SpiceCut-Cell Functions Circuit Analysis & Pattern Recognition Build circuit database of nodes and MOSFETs, and extract subcircuit configurations. Locate the high-risk nodes inside the cells to monitor for ensuring the modeling quality. Identify the measurable nodes inside the cells before tri-state output for complex I/O cell characterization. Perform pattern recognition over the circuits of standard cells, complex cells and customized cells.
11 Function Violation Due to Insufficient Setup Time D1 D2 S CK Q SD SE D1 D2 S CK Q SD SE 0 state 1 state 0 state 1 state Model Diagnoser TM can locate function failures in.lib model. In Original.Lib Setup Time ns Failure! Correct Setup Time Setup Time ns Function!
12 Output-Pin 'Glitch Violation Due to Insufficient Hold Time The glitch is of 66% Vdd with the width 37ps. Q Output pin Q Output pin Glitch SN Input pin Insufficient Hold Time GN Related pin
13 Internal 'Glitch Violation Due to Insufficient Hold Time The glitch is of 96% Vdd with the width 0.303ns. Internal node n_8_m2_d Internal node n_8_m2_d Glitch E Insufficient Hold Time CK Q
14 Run-Statistics Examples Function & Noise Check on Latch/Flip-flop Diagnosing one cell library normally takes 2~4 hours Cell Library 40nm (857 cells) 55nm (1084 cells) 65nm (814 cells) Number of Latch & FlipFlop Cells nm (837 cells) 251 Add Margin 0.05ns/ 0.1ns/ 0.2ns Function Violation 46/ 4/ 2 2/ 0/ 0 28/ 0/ 0 Glitch* Violation 0/ 0/ 0 15/ 5/ 1 13/ 0/ 0 76/ 71/ / 126/ 1 Violation-Free Margin to add 0.25ns 0.22ns 0.1ns 0.3ns 0.18um (594 cells) 0.35um (588 cells) / 2/ 1 97/ 45/ 20 Add Margin 0.5ns/ 1.0ns/ 1.5ns 0/ 0/ 0 0/ 0/ 0 Violation-Free Margin to add 2.4ns 1.7ns * Report Glitch Violation only when (1) glitch_height > 40% of Vdd (2) glitch_width > 20ps (3) glitch_height_in_v * glitch_width_in_ps > 20 V-ps
15 Repairing Library Model To Prevent from Function/Noise Violations For setup/hold time & min pulse width in.lib model, the margin shall be automatically adjusted to ensure No functional violations No glitch violations on internal nodes and output pins No over-excessive timings degrading performance seriously Margin increment can be by values or by percent Margin adjustment for tabular setup/hold time can be determined by the worst corner, by four extreme corners and the central, or by all entries of that table.
16 Repair.Lib Model Add Margin 0.05ns to Setup Time Cell SDFMQM8NA: State Pattern D1 D2 S CK Q SD SE 0 state 1 state Pin 'S' Setup_Rise se=0 sd=1 d1=0 s=0 d2=1 state(q)=1 se=0 sd=1 d1=0 s=1 d2=1 state(q)=0 No margin added Setup Time ns Failure! D1 D2 S CK Q SD SE 0 state 1 state 0.05ns margin added Setup Time ns Function!
17 Correct Excessive Spike in.lib To Prevent from Serious Speed Degrading Excessive Spike entry in the table of setup/hold time & min pulse width in.lib model could cause Difficult to keep monotonic table as required by PrimeTime Large performance sacrifice (e.g. due to min clock width) Simulate the cell by applying the reduced setup/hold time & min pulse width, i.e. adding negative margin. At the various negative margins, verify the simulation results for locating functional success without noise violations. Then, report the necessary corrections.
18 Inaccuracy Diagnosis By Library Model Comparison Diagnose the inaccuracy of target library by comparing its.lib model with the re-characterized one by using Model Diagnoser. The difference between the tables of parameters will be represented by Table report Statistical report 2D Graphical report 3D Graphical report
19 Inaccuracy Report Sorted Timing-Arc and Statistical Report Statistical report can be used for measuring overall quality of target library, at cell or parameter level.
20 2D/3D Graphic Report Based on Statistics of Cell & Parameter 2D Graphic Report
21 Function Verification Between Views of Library Models Check the consistency between function description (i.e..function statements) in.lib and Spice netlist at transistor level Verilog descriptions *Vital descriptions Report the difference of their derived state patterns * Vital verification will be released in Q3, 2010
22 Extract Cell Functions Directly from Spice Circuit Netlist Standard cells are normally by static designs. Their subcircuits and functions are quite straightforward. SpiceCut-Cell can partition/recognize those subcircuit patterns, and extract their corresponding functions. Example: Exclusive-OR (XOR) Cell A B C E D Y C = -B; F = -C = B; E = -A; D = C * E + F * (-E) = (-B) * (-A) + B * A Y = (-A) * (-B) + A * B Y = A ^ B F
23 Verify Functions in.lib Against Functions Extracted from Circuits Extract the logic functions directly from cell circuit netlist by SpiceCut-Cell Validate the FUNCTION statement of each timing arc in the existed.lib model, by comparing with those circuit-extracted ones. Confirm the specifications of related_pin, timing_sense, when, and sdf_cond etc. in the existed.lib model.
24 CCS Model Check CCS Receiver Model Consistency Check Compare CCS C1 and C2 with NLDM input capacitance CCS Driver Model Consistency Check Compare CCS waveform s peak time with NLDM delay CCS Driver Model Integration Check 0 Time (t) Current (I) I = C * d V / d t => I d t /C = Vdd Difference between I d t /C and Vdd need be < 5%
25 CCS Driver Model CCS vs NLDM Consistency Check Input Voltage 0 NLDM Output Voltage 0 CCS Driver0 Output Current t1 t2 t_peak Time (t) Time (t) Time (t) NLDM_delay = t2 - t1 CCS_delay from driver model = t_peak - t1 Consistency can be checked by comparing CCS_delay with NLDM_delay, and reporting the difference.
26 Interactive Debugger Click the selected violation or timing-arc, and the windows of circuit stimulus/netlist and waveform viewer will automatically pop up. Users can Edit/Save, Simulate and View Waveforms.
27 Conclusion Model Diagnoser TM Enable quality assurance of cell library.lib models which are critical for SoC designs. Quickly locate the function, noise, timing and power violations in the cell library.lib model at any PVT. Repair.Lib model of latch/flip-flop by automatically adjusting the margins for production yields. Easy to use with Interactive Debugger by GUI, and programmable configurations. Fully proven for production flow.
28 Appendix
29 Pre-Driver Input Waveform For 45nm Cell Characterization Pre-driver method is analogous to taking the output of a PWL source and passing it through a low-pass filter. Model Diagnoser supports both ramp and pre-driver input Green: Ramp input Yellow: Exponential input Red: Pre-Driver input
30 Criteria for Glitch Violation Noise Check on Latch/Flip-flop Command Format for criteria of Glitch violation Glitch Report Glitch violation when (glitch_height > 60% of Vdd) AND (glitch_width > 50ps) AND (glitch_height_in_v * glitch_width_in_ps > 30 V-ps) Default values for criteria of Glitch violation Glitch
31 Legend s Patents Model Diagnoser TM United States Patent "Glitch and metastability checks using signal characteristics United States Patent "Reliability based characterization using bisection" United States Patent "Delay and signal integrity check and characterization United States Patent "Method for simulating ULSI/VLSI circuit designs"
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